ls1046afrwy.c 5.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2019 NXP
  4. */
  5. #include <common.h>
  6. #include <i2c.h>
  7. #include <fdt_support.h>
  8. #include <init.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch/fsl_serdes.h>
  12. #include <asm/arch/soc.h>
  13. #include <asm/arch-fsl-layerscape/fsl_icid.h>
  14. #include <hwconfig.h>
  15. #include <ahci.h>
  16. #include <mmc.h>
  17. #include <scsi.h>
  18. #include <fm_eth.h>
  19. #include <fsl_csu.h>
  20. #include <fsl_esdhc.h>
  21. #include <fsl_sec.h>
  22. #include <fsl_dspi.h>
  23. #define LS1046A_PORSR1_REG 0x1EE0000
  24. #define BOOT_SRC_SD 0x20000000
  25. #define BOOT_SRC_MASK 0xFF800000
  26. #define BOARD_REV_GPIO_SHIFT 17
  27. #define BOARD_REV_MASK 0x03
  28. #define USB2_SEL_MASK 0x00000100
  29. #define BYTE_SWAP_32(word) ((((word) & 0xff000000) >> 24) | \
  30. (((word) & 0x00ff0000) >> 8) | \
  31. (((word) & 0x0000ff00) << 8) | \
  32. (((word) & 0x000000ff) << 24))
  33. #define SPI_MCR_REG 0x2100000
  34. DECLARE_GLOBAL_DATA_PTR;
  35. int select_i2c_ch_pca9547(u8 ch, int bus_num)
  36. {
  37. int ret;
  38. #ifdef CONFIG_DM_I2C
  39. struct udevice *dev;
  40. ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
  41. 1, &dev);
  42. if (ret) {
  43. printf("%s: Cannot find udev for a bus %d\n", __func__,
  44. bus_num);
  45. return ret;
  46. }
  47. ret = dm_i2c_write(dev, 0, &ch, 1);
  48. #else
  49. ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  50. #endif
  51. if (ret) {
  52. puts("PCA: failed to select proper channel\n");
  53. return ret;
  54. }
  55. return 0;
  56. }
  57. static inline void demux_select_usb2(void)
  58. {
  59. u32 val;
  60. struct ccsr_gpio *pgpio = (void *)(GPIO3_BASE_ADDR);
  61. val = in_be32(&pgpio->gpdir);
  62. val |= USB2_SEL_MASK;
  63. out_be32(&pgpio->gpdir, val);
  64. val = in_be32(&pgpio->gpdat);
  65. val |= USB2_SEL_MASK;
  66. out_be32(&pgpio->gpdat, val);
  67. }
  68. static inline void set_spi_cs_signal_inactive(void)
  69. {
  70. /* default: all CS signals inactive state is high */
  71. uint mcr_val;
  72. uint mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK |
  73. DSPI_MCR_CRXF | DSPI_MCR_CTXF;
  74. mcr_val = in_be32(SPI_MCR_REG);
  75. mcr_val |= DSPI_MCR_HALT;
  76. out_be32(SPI_MCR_REG, mcr_val);
  77. out_be32(SPI_MCR_REG, mcr_cfg_val);
  78. mcr_val = in_be32(SPI_MCR_REG);
  79. mcr_val &= ~DSPI_MCR_HALT;
  80. out_be32(SPI_MCR_REG, mcr_val);
  81. }
  82. int board_early_init_f(void)
  83. {
  84. fsl_lsch2_early_init_f();
  85. return 0;
  86. }
  87. static inline uint8_t get_board_version(void)
  88. {
  89. struct ccsr_gpio *pgpio = (void *)(GPIO2_BASE_ADDR);
  90. /* GPIO 13 and GPIO 14 are used for Board Rev */
  91. u32 gpio_val = ((in_be32(&pgpio->gpdat) >> BOARD_REV_GPIO_SHIFT))
  92. & BOARD_REV_MASK;
  93. /* GPIOs' are 0..31 in Big Endiness, swap GPIO 13 and GPIO 14 */
  94. u8 val = ((gpio_val >> 1) | (gpio_val << 1)) & BOARD_REV_MASK;
  95. return val;
  96. }
  97. int checkboard(void)
  98. {
  99. static const char *freq[2] = {"100.00MHZ", "100.00MHZ"};
  100. u32 boot_src;
  101. u8 rev;
  102. rev = get_board_version();
  103. switch (rev) {
  104. case 0x00:
  105. puts("Board: LS1046AFRWY, Rev: A, boot from ");
  106. break;
  107. case 0x01:
  108. puts("Board: LS1046AFRWY, Rev: B, boot from ");
  109. break;
  110. default:
  111. puts("Board: LS1046AFRWY, Rev: Unknown, boot from ");
  112. break;
  113. }
  114. boot_src = BYTE_SWAP_32(readl(LS1046A_PORSR1_REG));
  115. if ((boot_src & BOOT_SRC_MASK) == BOOT_SRC_SD)
  116. puts("SD\n");
  117. else
  118. puts("QSPI\n");
  119. printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[0], freq[1]);
  120. return 0;
  121. }
  122. int board_init(void)
  123. {
  124. #ifdef CONFIG_NXP_ESBC
  125. /*
  126. * In case of Secure Boot, the IBR configures the SMMU
  127. * to allow only Secure transactions.
  128. * SMMU must be reset in bypass mode.
  129. * Set the ClientPD bit and Clear the USFCFG Bit
  130. */
  131. u32 val;
  132. val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
  133. out_le32(SMMU_SCR0, val);
  134. val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
  135. out_le32(SMMU_NSCR0, val);
  136. #endif
  137. #ifdef CONFIG_FSL_CAAM
  138. sec_init();
  139. #endif
  140. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
  141. return 0;
  142. }
  143. int board_setup_core_volt(u32 vdd)
  144. {
  145. return 0;
  146. }
  147. void config_board_mux(void)
  148. {
  149. #ifdef CONFIG_HAS_FSL_XHCI_USB
  150. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  151. u32 usb_pwrfault;
  152. /*
  153. * USB2 is used, configure mux to USB2_DRVVBUS/USB2_PWRFAULT
  154. * USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA
  155. */
  156. out_be32(&scfg->rcwpmuxcr0, 0x3300);
  157. #ifdef CONFIG_HAS_FSL_IIC3
  158. /* IIC3 is used, configure mux to use IIC3_SCL/IIC3/SDA */
  159. out_be32(&scfg->rcwpmuxcr0, 0x0000);
  160. #endif
  161. out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
  162. usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
  163. SCFG_USBPWRFAULT_USB3_SHIFT) |
  164. (SCFG_USBPWRFAULT_DEDICATED <<
  165. SCFG_USBPWRFAULT_USB2_SHIFT) |
  166. (SCFG_USBPWRFAULT_SHARED <<
  167. SCFG_USBPWRFAULT_USB1_SHIFT);
  168. out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
  169. #ifndef CONFIG_HAS_FSL_IIC3
  170. /*
  171. * LS1046A FRWY board has demultiplexer NX3DV42GU with GPIO3_23 as input
  172. * to select I2C3_USB2_SEL_IO
  173. * I2C3_USB2_SEL = 0: I2C3_SCL/SDA signals are routed to
  174. * I2C3 header (default)
  175. * I2C3_USB2_SEL = 1: USB2_DRVVBUS/PWRFAULT signals are routed to
  176. * USB2 port
  177. * programmed to select USB2 by setting GPIO3_23 output to one
  178. */
  179. demux_select_usb2();
  180. #endif
  181. #endif
  182. set_spi_cs_signal_inactive();
  183. }
  184. #ifdef CONFIG_MISC_INIT_R
  185. int misc_init_r(void)
  186. {
  187. config_board_mux();
  188. return 0;
  189. }
  190. #endif
  191. int ft_board_setup(void *blob, struct bd_info *bd)
  192. {
  193. u64 base[CONFIG_NR_DRAM_BANKS];
  194. u64 size[CONFIG_NR_DRAM_BANKS];
  195. /* fixup DT for the two DDR banks */
  196. base[0] = gd->bd->bi_dram[0].start;
  197. size[0] = gd->bd->bi_dram[0].size;
  198. base[1] = gd->bd->bi_dram[1].start;
  199. size[1] = gd->bd->bi_dram[1].size;
  200. fdt_fixup_memory_banks(blob, base, size, 2);
  201. ft_cpu_setup(blob, bd);
  202. #ifdef CONFIG_SYS_DPAA_FMAN
  203. #ifndef CONFIG_DM_ETH
  204. fdt_fixup_fman_ethernet(blob);
  205. #endif
  206. #endif
  207. fdt_fixup_icid(blob);
  208. return 0;
  209. }