eth.c 2.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2019 NXP
  4. */
  5. #include <common.h>
  6. #include <fdt_support.h>
  7. #include <net.h>
  8. #include <asm/io.h>
  9. #include <netdev.h>
  10. #include <fm_eth.h>
  11. #include <fsl_dtsec.h>
  12. #include <fsl_mdio.h>
  13. #include <malloc.h>
  14. #include "../common/fman.h"
  15. int board_eth_init(struct bd_info *bis)
  16. {
  17. #ifdef CONFIG_FMAN_ENET
  18. struct memac_mdio_info dtsec_mdio_info;
  19. struct mii_dev *dev;
  20. u32 srds_s1;
  21. struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  22. srds_s1 = in_be32(&gur->rcwsr[4]) &
  23. FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
  24. srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
  25. dtsec_mdio_info.regs =
  26. (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
  27. dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
  28. /* Register the 1G MDIO bus */
  29. fm_memac_mdio_init(bis, &dtsec_mdio_info);
  30. /* QSGMII on lane B, MAC 6/5/10/1 */
  31. fm_info_set_phy_address(FM1_DTSEC6, QSGMII_PORT1_PHY_ADDR);
  32. fm_info_set_phy_address(FM1_DTSEC5, QSGMII_PORT2_PHY_ADDR);
  33. fm_info_set_phy_address(FM1_DTSEC10, QSGMII_PORT3_PHY_ADDR);
  34. fm_info_set_phy_address(FM1_DTSEC1, QSGMII_PORT4_PHY_ADDR);
  35. switch (srds_s1) {
  36. case 0x3040:
  37. break;
  38. default:
  39. printf("Invalid SerDes protocol 0x%x for LS1046AFRWY\n",
  40. srds_s1);
  41. break;
  42. }
  43. dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
  44. fm_info_set_mdio(FM1_DTSEC6, dev);
  45. fm_info_set_mdio(FM1_DTSEC5, dev);
  46. fm_info_set_mdio(FM1_DTSEC10, dev);
  47. fm_info_set_mdio(FM1_DTSEC1, dev);
  48. fm_disable_port(FM1_DTSEC9);
  49. cpu_eth_init(bis);
  50. #endif
  51. return pci_eth_init(bis);
  52. }
  53. #ifdef CONFIG_FMAN_ENET
  54. int fdt_update_ethernet_dt(void *blob)
  55. {
  56. u32 srds_s1;
  57. int i, prop;
  58. int offset, nodeoff;
  59. const char *path;
  60. struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  61. srds_s1 = in_be32(&gur->rcwsr[4]) &
  62. FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
  63. srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
  64. /* Cycle through all aliases */
  65. for (prop = 0; ; prop++) {
  66. const char *name;
  67. /* FDT might have been edited, recompute the offset */
  68. offset = fdt_first_property_offset(blob,
  69. fdt_path_offset(blob,
  70. "/aliases")
  71. );
  72. /* Select property number 'prop' */
  73. for (i = 0; i < prop; i++)
  74. offset = fdt_next_property_offset(blob, offset);
  75. if (offset < 0)
  76. break;
  77. path = fdt_getprop_by_offset(blob, offset, &name, NULL);
  78. nodeoff = fdt_path_offset(blob, path);
  79. switch (srds_s1) {
  80. case 0x3040:
  81. if (!strcmp(name, "ethernet1"))
  82. fdt_status_disabled(blob, nodeoff);
  83. if (!strcmp(name, "ethernet2"))
  84. fdt_status_disabled(blob, nodeoff);
  85. if (!strcmp(name, "ethernet3"))
  86. fdt_status_disabled(blob, nodeoff);
  87. if (!strcmp(name, "ethernet6"))
  88. fdt_status_disabled(blob, nodeoff);
  89. break;
  90. default:
  91. printf("%s:Invalid SerDes prtcl 0x%x for LS1046AFRWY\n",
  92. __func__, srds_s1);
  93. break;
  94. }
  95. }
  96. return 0;
  97. }
  98. #endif