ls1043aqds.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2015 Freescale Semiconductor, Inc.
  4. * Copyright 2019-2020 NXP
  5. */
  6. #include <common.h>
  7. #include <i2c.h>
  8. #include <fdt_support.h>
  9. #include <fsl_ddr_sdram.h>
  10. #include <init.h>
  11. #include <log.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/clock.h>
  14. #include <asm/arch/fsl_serdes.h>
  15. #include <asm/arch/ppa.h>
  16. #include <asm/arch/fdt.h>
  17. #include <asm/arch/mmu.h>
  18. #include <asm/arch/cpu.h>
  19. #include <asm/arch/soc.h>
  20. #include <asm/arch-fsl-layerscape/fsl_icid.h>
  21. #include <ahci.h>
  22. #include <hwconfig.h>
  23. #include <mmc.h>
  24. #include <scsi.h>
  25. #include <fm_eth.h>
  26. #include <fsl_esdhc.h>
  27. #include <fsl_ifc.h>
  28. #include <spl.h>
  29. #include "../common/qixis.h"
  30. #include "ls1043aqds_qixis.h"
  31. DECLARE_GLOBAL_DATA_PTR;
  32. enum {
  33. MUX_TYPE_GPIO,
  34. };
  35. /* LS1043AQDS serdes mux */
  36. #define CFG_SD_MUX1_SLOT2 0x0 /* SLOT2 TX/RX0 */
  37. #define CFG_SD_MUX1_SLOT1 0x1 /* SLOT1 TX/RX1 */
  38. #define CFG_SD_MUX2_SLOT3 0x0 /* SLOT3 TX/RX0 */
  39. #define CFG_SD_MUX2_SLOT1 0x1 /* SLOT1 TX/RX2 */
  40. #define CFG_SD_MUX3_SLOT4 0x0 /* SLOT4 TX/RX0 */
  41. #define CFG_SD_MUX3_MUX4 0x1 /* MUX4 */
  42. #define CFG_SD_MUX4_SLOT3 0x0 /* SLOT3 TX/RX1 */
  43. #define CFG_SD_MUX4_SLOT1 0x1 /* SLOT1 TX/RX3 */
  44. #define CFG_UART_MUX_MASK 0x6
  45. #define CFG_UART_MUX_SHIFT 1
  46. #define CFG_LPUART_EN 0x1
  47. #ifdef CONFIG_SYS_I2C_EARLY_INIT
  48. void i2c_early_init_f(void);
  49. #endif
  50. #ifdef CONFIG_TFABOOT
  51. struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  52. {
  53. "nor0",
  54. CONFIG_SYS_NOR0_CSPR,
  55. CONFIG_SYS_NOR0_CSPR_EXT,
  56. CONFIG_SYS_NOR_AMASK,
  57. CONFIG_SYS_NOR_CSOR,
  58. {
  59. CONFIG_SYS_NOR_FTIM0,
  60. CONFIG_SYS_NOR_FTIM1,
  61. CONFIG_SYS_NOR_FTIM2,
  62. CONFIG_SYS_NOR_FTIM3
  63. },
  64. },
  65. {
  66. "nor1",
  67. CONFIG_SYS_NOR1_CSPR,
  68. CONFIG_SYS_NOR1_CSPR_EXT,
  69. CONFIG_SYS_NOR_AMASK,
  70. CONFIG_SYS_NOR_CSOR,
  71. {
  72. CONFIG_SYS_NOR_FTIM0,
  73. CONFIG_SYS_NOR_FTIM1,
  74. CONFIG_SYS_NOR_FTIM2,
  75. CONFIG_SYS_NOR_FTIM3
  76. },
  77. },
  78. {
  79. "nand",
  80. CONFIG_SYS_NAND_CSPR,
  81. CONFIG_SYS_NAND_CSPR_EXT,
  82. CONFIG_SYS_NAND_AMASK,
  83. CONFIG_SYS_NAND_CSOR,
  84. {
  85. CONFIG_SYS_NAND_FTIM0,
  86. CONFIG_SYS_NAND_FTIM1,
  87. CONFIG_SYS_NAND_FTIM2,
  88. CONFIG_SYS_NAND_FTIM3
  89. },
  90. },
  91. {
  92. "fpga",
  93. CONFIG_SYS_FPGA_CSPR,
  94. CONFIG_SYS_FPGA_CSPR_EXT,
  95. CONFIG_SYS_FPGA_AMASK,
  96. CONFIG_SYS_FPGA_CSOR,
  97. {
  98. CONFIG_SYS_FPGA_FTIM0,
  99. CONFIG_SYS_FPGA_FTIM1,
  100. CONFIG_SYS_FPGA_FTIM2,
  101. CONFIG_SYS_FPGA_FTIM3
  102. },
  103. }
  104. };
  105. struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  106. {
  107. "nand",
  108. CONFIG_SYS_NAND_CSPR,
  109. CONFIG_SYS_NAND_CSPR_EXT,
  110. CONFIG_SYS_NAND_AMASK,
  111. CONFIG_SYS_NAND_CSOR,
  112. {
  113. CONFIG_SYS_NAND_FTIM0,
  114. CONFIG_SYS_NAND_FTIM1,
  115. CONFIG_SYS_NAND_FTIM2,
  116. CONFIG_SYS_NAND_FTIM3
  117. },
  118. },
  119. {
  120. "nor0",
  121. CONFIG_SYS_NOR0_CSPR,
  122. CONFIG_SYS_NOR0_CSPR_EXT,
  123. CONFIG_SYS_NOR_AMASK,
  124. CONFIG_SYS_NOR_CSOR,
  125. {
  126. CONFIG_SYS_NOR_FTIM0,
  127. CONFIG_SYS_NOR_FTIM1,
  128. CONFIG_SYS_NOR_FTIM2,
  129. CONFIG_SYS_NOR_FTIM3
  130. },
  131. },
  132. {
  133. "nor1",
  134. CONFIG_SYS_NOR1_CSPR,
  135. CONFIG_SYS_NOR1_CSPR_EXT,
  136. CONFIG_SYS_NOR_AMASK,
  137. CONFIG_SYS_NOR_CSOR,
  138. {
  139. CONFIG_SYS_NOR_FTIM0,
  140. CONFIG_SYS_NOR_FTIM1,
  141. CONFIG_SYS_NOR_FTIM2,
  142. CONFIG_SYS_NOR_FTIM3
  143. },
  144. },
  145. {
  146. "fpga",
  147. CONFIG_SYS_FPGA_CSPR,
  148. CONFIG_SYS_FPGA_CSPR_EXT,
  149. CONFIG_SYS_FPGA_AMASK,
  150. CONFIG_SYS_FPGA_CSOR,
  151. {
  152. CONFIG_SYS_FPGA_FTIM0,
  153. CONFIG_SYS_FPGA_FTIM1,
  154. CONFIG_SYS_FPGA_FTIM2,
  155. CONFIG_SYS_FPGA_FTIM3
  156. },
  157. }
  158. };
  159. void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
  160. {
  161. enum boot_src src = get_boot_src();
  162. if (src == BOOT_SOURCE_IFC_NAND)
  163. regs_info->regs = ifc_cfg_nand_boot;
  164. else
  165. regs_info->regs = ifc_cfg_nor_boot;
  166. regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
  167. }
  168. #endif
  169. int checkboard(void)
  170. {
  171. #ifdef CONFIG_TFABOOT
  172. enum boot_src src = get_boot_src();
  173. #endif
  174. char buf[64];
  175. #ifndef CONFIG_SD_BOOT
  176. u8 sw;
  177. #endif
  178. puts("Board: LS1043AQDS, boot from ");
  179. #ifdef CONFIG_TFABOOT
  180. if (src == BOOT_SOURCE_SD_MMC)
  181. puts("SD\n");
  182. else {
  183. #endif
  184. #ifdef CONFIG_SD_BOOT
  185. puts("SD\n");
  186. #else
  187. sw = QIXIS_READ(brdcfg[0]);
  188. sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  189. if (sw < 0x8)
  190. printf("vBank: %d\n", sw);
  191. else if (sw == 0x8)
  192. puts("PromJet\n");
  193. else if (sw == 0x9)
  194. puts("NAND\n");
  195. else if (sw == 0xF)
  196. printf("QSPI\n");
  197. else
  198. printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  199. #endif
  200. #ifdef CONFIG_TFABOOT
  201. }
  202. #endif
  203. printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
  204. QIXIS_READ(id), QIXIS_READ(arch));
  205. printf("FPGA: v%d (%s), build %d\n",
  206. (int)QIXIS_READ(scver), qixis_read_tag(buf),
  207. (int)qixis_read_minor());
  208. return 0;
  209. }
  210. bool if_board_diff_clk(void)
  211. {
  212. u8 diff_conf = QIXIS_READ(brdcfg[11]);
  213. return diff_conf & 0x40;
  214. }
  215. unsigned long get_board_sys_clk(void)
  216. {
  217. u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  218. switch (sysclk_conf & 0x0f) {
  219. case QIXIS_SYSCLK_64:
  220. return 64000000;
  221. case QIXIS_SYSCLK_83:
  222. return 83333333;
  223. case QIXIS_SYSCLK_100:
  224. return 100000000;
  225. case QIXIS_SYSCLK_125:
  226. return 125000000;
  227. case QIXIS_SYSCLK_133:
  228. return 133333333;
  229. case QIXIS_SYSCLK_150:
  230. return 150000000;
  231. case QIXIS_SYSCLK_160:
  232. return 160000000;
  233. case QIXIS_SYSCLK_166:
  234. return 166666666;
  235. }
  236. return 66666666;
  237. }
  238. unsigned long get_board_ddr_clk(void)
  239. {
  240. u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
  241. if (if_board_diff_clk())
  242. return get_board_sys_clk();
  243. switch ((ddrclk_conf & 0x30) >> 4) {
  244. case QIXIS_DDRCLK_100:
  245. return 100000000;
  246. case QIXIS_DDRCLK_125:
  247. return 125000000;
  248. case QIXIS_DDRCLK_133:
  249. return 133333333;
  250. }
  251. return 66666666;
  252. }
  253. int select_i2c_ch_pca9547(u8 ch, int bus_num)
  254. {
  255. int ret;
  256. #ifdef CONFIG_DM_I2C
  257. struct udevice *dev;
  258. ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
  259. 1, &dev);
  260. if (ret) {
  261. printf("%s: Cannot find udev for a bus %d\n", __func__,
  262. bus_num);
  263. return ret;
  264. }
  265. ret = dm_i2c_write(dev, 0, &ch, 1);
  266. #else
  267. ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  268. #endif
  269. if (ret) {
  270. puts("PCA: failed to select proper channel\n");
  271. return ret;
  272. }
  273. return 0;
  274. }
  275. int dram_init(void)
  276. {
  277. /*
  278. * When resuming from deep sleep, the I2C channel may not be
  279. * in the default channel. So, switch to the default channel
  280. * before accessing DDR SPD.
  281. *
  282. * PCA9547 mount on I2C1 bus
  283. */
  284. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
  285. fsl_initdram();
  286. #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
  287. defined(CONFIG_SPL_BUILD)
  288. /* This will break-before-make MMU for DDR */
  289. update_early_mmu_table();
  290. #endif
  291. return 0;
  292. }
  293. int i2c_multiplexer_select_vid_channel(u8 channel)
  294. {
  295. return select_i2c_ch_pca9547(channel, 0);
  296. }
  297. void board_retimer_init(void)
  298. {
  299. u8 reg;
  300. int bus_num = 0;
  301. /* Retimer is connected to I2C1_CH7_CH5 */
  302. select_i2c_ch_pca9547(I2C_MUX_CH7, bus_num);
  303. reg = I2C_MUX_CH5;
  304. #ifdef CONFIG_DM_I2C
  305. struct udevice *dev;
  306. int ret;
  307. ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_SEC,
  308. 1, &dev);
  309. if (ret) {
  310. printf("%s: Cannot find udev for a bus %d\n", __func__,
  311. bus_num);
  312. return;
  313. }
  314. dm_i2c_write(dev, 0, &reg, 1);
  315. /* Access to Control/Shared register */
  316. ret = i2c_get_chip_for_busnum(bus_num, I2C_RETIMER_ADDR,
  317. 1, &dev);
  318. if (ret) {
  319. printf("%s: Cannot find udev for a bus %d\n", __func__,
  320. bus_num);
  321. return;
  322. }
  323. reg = 0x0;
  324. dm_i2c_write(dev, 0xff, &reg, 1);
  325. /* Read device revision and ID */
  326. dm_i2c_read(dev, 1, &reg, 1);
  327. debug("Retimer version id = 0x%x\n", reg);
  328. /* Enable Broadcast. All writes target all channel register sets */
  329. reg = 0x0c;
  330. dm_i2c_write(dev, 0xff, &reg, 1);
  331. /* Reset Channel Registers */
  332. dm_i2c_read(dev, 0, &reg, 1);
  333. reg |= 0x4;
  334. dm_i2c_write(dev, 0, &reg, 1);
  335. /* Enable override divider select and Enable Override Output Mux */
  336. dm_i2c_read(dev, 9, &reg, 1);
  337. reg |= 0x24;
  338. dm_i2c_write(dev, 9, &reg, 1);
  339. /* Select VCO Divider to full rate (000) */
  340. dm_i2c_read(dev, 0x18, &reg, 1);
  341. reg &= 0x8f;
  342. dm_i2c_write(dev, 0x18, &reg, 1);
  343. /* Selects active PFD MUX Input as Re-timed Data (001) */
  344. dm_i2c_read(dev, 0x1e, &reg, 1);
  345. reg &= 0x3f;
  346. reg |= 0x20;
  347. dm_i2c_write(dev, 0x1e, &reg, 1);
  348. /* Set data rate as 10.3125 Gbps */
  349. reg = 0x0;
  350. dm_i2c_write(dev, 0x60, &reg, 1);
  351. reg = 0xb2;
  352. dm_i2c_write(dev, 0x61, &reg, 1);
  353. reg = 0x90;
  354. dm_i2c_write(dev, 0x62, &reg, 1);
  355. reg = 0xb3;
  356. dm_i2c_write(dev, 0x63, &reg, 1);
  357. reg = 0xcd;
  358. dm_i2c_write(dev, 0x64, &reg, 1);
  359. #else
  360. i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1);
  361. /* Access to Control/Shared register */
  362. reg = 0x0;
  363. i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
  364. /* Read device revision and ID */
  365. i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
  366. debug("Retimer version id = 0x%x\n", reg);
  367. /* Enable Broadcast. All writes target all channel register sets */
  368. reg = 0x0c;
  369. i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
  370. /* Reset Channel Registers */
  371. i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
  372. reg |= 0x4;
  373. i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
  374. /* Enable override divider select and Enable Override Output Mux */
  375. i2c_read(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
  376. reg |= 0x24;
  377. i2c_write(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
  378. /* Select VCO Divider to full rate (000) */
  379. i2c_read(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
  380. reg &= 0x8f;
  381. i2c_write(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
  382. /* Selects active PFD MUX Input as Re-timed Data (001) */
  383. i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
  384. reg &= 0x3f;
  385. reg |= 0x20;
  386. i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
  387. /* Set data rate as 10.3125 Gbps */
  388. reg = 0x0;
  389. i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
  390. reg = 0xb2;
  391. i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
  392. reg = 0x90;
  393. i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
  394. reg = 0xb3;
  395. i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
  396. reg = 0xcd;
  397. i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
  398. #endif
  399. /* Return the default channel */
  400. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, bus_num);
  401. }
  402. int board_early_init_f(void)
  403. {
  404. u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
  405. #ifdef CONFIG_HAS_FSL_XHCI_USB
  406. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  407. u32 usb_pwrfault;
  408. #endif
  409. #ifdef CONFIG_LPUART
  410. u8 uart;
  411. #endif
  412. /*
  413. * Enable secure system counter for timer
  414. */
  415. out_le32(cntcr, 0x1);
  416. #ifdef CONFIG_SYS_I2C_EARLY_INIT
  417. i2c_early_init_f();
  418. #endif
  419. fsl_lsch2_early_init_f();
  420. #ifdef CONFIG_HAS_FSL_XHCI_USB
  421. out_be32(&scfg->rcwpmuxcr0, 0x3333);
  422. out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
  423. usb_pwrfault =
  424. (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
  425. (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
  426. (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
  427. out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
  428. #endif
  429. #ifdef CONFIG_LPUART
  430. /* We use lpuart0 as system console */
  431. uart = QIXIS_READ(brdcfg[14]);
  432. uart &= ~CFG_UART_MUX_MASK;
  433. uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
  434. QIXIS_WRITE(brdcfg[14], uart);
  435. #endif
  436. return 0;
  437. }
  438. #ifdef CONFIG_FSL_DEEP_SLEEP
  439. /* determine if it is a warm boot */
  440. bool is_warm_boot(void)
  441. {
  442. #define DCFG_CCSR_CRSTSR_WDRFR (1 << 3)
  443. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  444. if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
  445. return 1;
  446. return 0;
  447. }
  448. #endif
  449. int config_board_mux(int ctrl_type)
  450. {
  451. u8 reg14;
  452. reg14 = QIXIS_READ(brdcfg[14]);
  453. switch (ctrl_type) {
  454. case MUX_TYPE_GPIO:
  455. reg14 = (reg14 & (~0x30)) | 0x20;
  456. break;
  457. default:
  458. puts("Unsupported mux interface type\n");
  459. return -1;
  460. }
  461. QIXIS_WRITE(brdcfg[14], reg14);
  462. return 0;
  463. }
  464. int config_serdes_mux(void)
  465. {
  466. return 0;
  467. }
  468. #ifdef CONFIG_MISC_INIT_R
  469. int misc_init_r(void)
  470. {
  471. if (hwconfig("gpio"))
  472. config_board_mux(MUX_TYPE_GPIO);
  473. return 0;
  474. }
  475. #endif
  476. int board_init(void)
  477. {
  478. #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
  479. erratum_a010315();
  480. #endif
  481. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
  482. board_retimer_init();
  483. #ifdef CONFIG_SYS_FSL_SERDES
  484. config_serdes_mux();
  485. #endif
  486. #ifdef CONFIG_FSL_LS_PPA
  487. ppa_init();
  488. #endif
  489. return 0;
  490. }
  491. #ifdef CONFIG_OF_BOARD_SETUP
  492. int ft_board_setup(void *blob, struct bd_info *bd)
  493. {
  494. u64 base[CONFIG_NR_DRAM_BANKS];
  495. u64 size[CONFIG_NR_DRAM_BANKS];
  496. u8 reg;
  497. /* fixup DT for the two DDR banks */
  498. base[0] = gd->bd->bi_dram[0].start;
  499. size[0] = gd->bd->bi_dram[0].size;
  500. base[1] = gd->bd->bi_dram[1].start;
  501. size[1] = gd->bd->bi_dram[1].size;
  502. fdt_fixup_memory_banks(blob, base, size, 2);
  503. ft_cpu_setup(blob, bd);
  504. #ifdef CONFIG_SYS_DPAA_FMAN
  505. #ifndef CONFIG_DM_ETH
  506. fdt_fixup_fman_ethernet(blob);
  507. #endif
  508. fdt_fixup_board_enet(blob);
  509. #endif
  510. fdt_fixup_icid(blob);
  511. reg = QIXIS_READ(brdcfg[0]);
  512. reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  513. /* Disable IFC if QSPI is enabled */
  514. if (reg == 0xF)
  515. do_fixup_by_compat(blob, "fsl,ifc",
  516. "status", "disabled", 8 + 1, 1);
  517. return 0;
  518. }
  519. #endif
  520. u8 flash_read8(void *addr)
  521. {
  522. return __raw_readb(addr + 1);
  523. }
  524. void flash_write16(u16 val, void *addr)
  525. {
  526. u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
  527. __raw_writew(shftval, addr);
  528. }
  529. u16 flash_read16(void *addr)
  530. {
  531. u16 val = __raw_readw(addr);
  532. return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
  533. }
  534. #if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
  535. void *env_sf_get_env_addr(void)
  536. {
  537. return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
  538. }
  539. #endif