ls1021atsn.c 5.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265
  1. // SPDX-License-Identifier: GPL-2.0
  2. /* Copyright 2016-2019 NXP Semiconductors
  3. */
  4. #include <common.h>
  5. #include <clock_legacy.h>
  6. #include <fdt_support.h>
  7. #include <init.h>
  8. #include <net.h>
  9. #include <asm/arch-ls102xa/ls102xa_soc.h>
  10. #include <asm/arch/ls102xa_devdis.h>
  11. #include <asm/arch/immap_ls102xa.h>
  12. #include <asm/arch/ls102xa_soc.h>
  13. #include <asm/arch/fsl_serdes.h>
  14. #include <linux/delay.h>
  15. #include "../common/sleep.h"
  16. #include <fsl_validate.h>
  17. #include <fsl_immap.h>
  18. #include <fsl_csu.h>
  19. #include <netdev.h>
  20. #include <spl.h>
  21. #ifdef CONFIG_U_QE
  22. #include <fsl_qe.h>
  23. #endif
  24. DECLARE_GLOBAL_DATA_PTR;
  25. static void ddrmc_init(void)
  26. {
  27. #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
  28. struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
  29. u32 temp_sdram_cfg, tmp;
  30. out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
  31. out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
  32. out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
  33. out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
  34. out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
  35. out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
  36. out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
  37. out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
  38. out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
  39. #ifdef CONFIG_DEEP_SLEEP
  40. if (is_warm_boot()) {
  41. out_be32(&ddr->sdram_cfg_2,
  42. DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
  43. out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
  44. out_be32(&ddr->init_ext_addr, (1 << 31));
  45. /* DRAM VRef will not be trained */
  46. out_be32(&ddr->ddr_cdr2,
  47. DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
  48. } else
  49. #endif
  50. {
  51. out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
  52. out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
  53. }
  54. out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
  55. out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
  56. out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
  57. out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
  58. out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
  59. out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
  60. out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
  61. out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
  62. out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
  63. out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
  64. /* DDR erratum A-009942 */
  65. tmp = in_be32(&ddr->debug[28]);
  66. out_be32(&ddr->debug[28], tmp | 0x0070006f);
  67. udelay(1);
  68. #ifdef CONFIG_DEEP_SLEEP
  69. if (is_warm_boot()) {
  70. /* enter self-refresh */
  71. temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
  72. temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
  73. out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
  74. temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
  75. } else
  76. #endif
  77. temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
  78. out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
  79. #ifdef CONFIG_DEEP_SLEEP
  80. if (is_warm_boot()) {
  81. /* exit self-refresh */
  82. temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
  83. temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
  84. out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
  85. }
  86. #endif
  87. #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
  88. }
  89. int dram_init(void)
  90. {
  91. ddrmc_init();
  92. erratum_a008850_post();
  93. gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  94. #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
  95. fsl_dp_resume();
  96. #endif
  97. return 0;
  98. }
  99. int board_eth_init(struct bd_info *bis)
  100. {
  101. return pci_eth_init(bis);
  102. }
  103. int board_early_init_f(void)
  104. {
  105. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  106. #ifdef CONFIG_TSEC_ENET
  107. /*
  108. * Clear BD & FR bits for big endian BD's and frame data (aka set
  109. * correct eTSEC endianness). This is crucial in ensuring that it does
  110. * not report Data Parity Errors in its RX/TX FIFOs when attempting to
  111. * send traffic.
  112. */
  113. clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
  114. /* EC3_GTX_CLK125 (of enet2) used for all RGMII interfaces */
  115. out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
  116. #endif
  117. arch_soc_init();
  118. #if defined(CONFIG_DEEP_SLEEP)
  119. if (is_warm_boot()) {
  120. timer_init();
  121. dram_init();
  122. }
  123. #endif
  124. return 0;
  125. }
  126. #ifdef CONFIG_SPL_BUILD
  127. void board_init_f(ulong dummy)
  128. {
  129. void (*second_uboot)(void);
  130. /* Clear the BSS */
  131. memset(__bss_start, 0, __bss_end - __bss_start);
  132. get_clocks();
  133. #if defined(CONFIG_DEEP_SLEEP)
  134. if (is_warm_boot())
  135. fsl_dp_disable_console();
  136. #endif
  137. preloader_console_init();
  138. dram_init();
  139. /* Allow OCRAM access permission as R/W */
  140. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  141. enable_layerscape_ns_access();
  142. enable_layerscape_ns_access();
  143. #endif
  144. /*
  145. * if it is woken up from deep sleep, then jump to second
  146. * stage U-Boot and continue executing without recopying
  147. * it from SD since it has already been reserved in memory
  148. * in last boot.
  149. */
  150. if (is_warm_boot()) {
  151. second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
  152. second_uboot();
  153. }
  154. board_init_r(NULL, 0);
  155. }
  156. #endif
  157. int board_init(void)
  158. {
  159. #ifndef CONFIG_SYS_FSL_NO_SERDES
  160. fsl_serdes_init();
  161. #endif
  162. ls102xa_smmu_stream_id_init();
  163. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  164. enable_layerscape_ns_access();
  165. #endif
  166. #ifdef CONFIG_U_QE
  167. u_qe_init();
  168. #endif
  169. return 0;
  170. }
  171. #if defined(CONFIG_SPL_BUILD)
  172. void spl_board_init(void)
  173. {
  174. ls102xa_smmu_stream_id_init();
  175. }
  176. #endif
  177. #ifdef CONFIG_BOARD_LATE_INIT
  178. int board_late_init(void)
  179. {
  180. #ifdef CONFIG_CHAIN_OF_TRUST
  181. fsl_setenv_chain_of_trust();
  182. #endif
  183. return 0;
  184. }
  185. #endif
  186. #if defined(CONFIG_MISC_INIT_R)
  187. int misc_init_r(void)
  188. {
  189. #ifdef CONFIG_FSL_DEVICE_DISABLE
  190. device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
  191. #endif
  192. #ifdef CONFIG_FSL_CAAM
  193. return sec_init();
  194. #endif
  195. }
  196. #endif
  197. #if defined(CONFIG_DEEP_SLEEP)
  198. void board_sleep_prepare(void)
  199. {
  200. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  201. enable_layerscape_ns_access();
  202. #endif
  203. }
  204. #endif
  205. int ft_board_setup(void *blob, struct bd_info *bd)
  206. {
  207. ft_cpu_setup(blob, bd);
  208. #ifdef CONFIG_PCI
  209. ft_pci_setup(blob, bd);
  210. #endif
  211. return 0;
  212. }