ls1021aqds.c 9.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. * Copyright 2019 NXP
  5. */
  6. #include <common.h>
  7. #include <clock_legacy.h>
  8. #include <fdt_support.h>
  9. #include <i2c.h>
  10. #include <init.h>
  11. #include <log.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/immap_ls102xa.h>
  14. #include <asm/arch/clock.h>
  15. #include <asm/arch/fsl_serdes.h>
  16. #include <asm/arch/ls102xa_soc.h>
  17. #include <asm/arch/ls102xa_devdis.h>
  18. #include <hwconfig.h>
  19. #include <mmc.h>
  20. #include <fsl_csu.h>
  21. #include <fsl_ifc.h>
  22. #include <fsl_sec.h>
  23. #include <spl.h>
  24. #include <fsl_devdis.h>
  25. #include <fsl_validate.h>
  26. #include <fsl_ddr.h>
  27. #include "../common/sleep.h"
  28. #include "../common/qixis.h"
  29. #include "ls1021aqds_qixis.h"
  30. #ifdef CONFIG_U_QE
  31. #include <fsl_qe.h>
  32. #endif
  33. #define PIN_MUX_SEL_CAN 0x03
  34. #define PIN_MUX_SEL_IIC2 0xa0
  35. #define PIN_MUX_SEL_RGMII 0x00
  36. #define PIN_MUX_SEL_SAI 0x0c
  37. #define PIN_MUX_SEL_SDHC 0x00
  38. #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0x0f) | value)
  39. #define SET_EC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
  40. enum {
  41. MUX_TYPE_CAN,
  42. MUX_TYPE_IIC2,
  43. MUX_TYPE_RGMII,
  44. MUX_TYPE_SAI,
  45. MUX_TYPE_SDHC,
  46. MUX_TYPE_SD_PCI4,
  47. MUX_TYPE_SD_PC_SA_SG_SG,
  48. MUX_TYPE_SD_PC_SA_PC_SG,
  49. MUX_TYPE_SD_PC_SG_SG,
  50. };
  51. enum {
  52. GE0_CLK125,
  53. GE2_CLK125,
  54. GE1_CLK125,
  55. };
  56. int checkboard(void)
  57. {
  58. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  59. char buf[64];
  60. #endif
  61. #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
  62. u8 sw;
  63. #endif
  64. puts("Board: LS1021AQDS\n");
  65. #ifdef CONFIG_SD_BOOT
  66. puts("SD\n");
  67. #elif CONFIG_QSPI_BOOT
  68. puts("QSPI\n");
  69. #else
  70. sw = QIXIS_READ(brdcfg[0]);
  71. sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  72. if (sw < 0x8)
  73. printf("vBank: %d\n", sw);
  74. else if (sw == 0x8)
  75. puts("PromJet\n");
  76. else if (sw == 0x9)
  77. puts("NAND\n");
  78. else if (sw == 0x15)
  79. printf("IFCCard\n");
  80. else
  81. printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  82. #endif
  83. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  84. printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
  85. QIXIS_READ(id), QIXIS_READ(arch));
  86. printf("FPGA: v%d (%s), build %d\n",
  87. (int)QIXIS_READ(scver), qixis_read_tag(buf),
  88. (int)qixis_read_minor());
  89. #endif
  90. return 0;
  91. }
  92. unsigned long get_board_sys_clk(void)
  93. {
  94. u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  95. switch (sysclk_conf & 0x0f) {
  96. case QIXIS_SYSCLK_64:
  97. return 64000000;
  98. case QIXIS_SYSCLK_83:
  99. return 83333333;
  100. case QIXIS_SYSCLK_100:
  101. return 100000000;
  102. case QIXIS_SYSCLK_125:
  103. return 125000000;
  104. case QIXIS_SYSCLK_133:
  105. return 133333333;
  106. case QIXIS_SYSCLK_150:
  107. return 150000000;
  108. case QIXIS_SYSCLK_160:
  109. return 160000000;
  110. case QIXIS_SYSCLK_166:
  111. return 166666666;
  112. }
  113. return 66666666;
  114. }
  115. unsigned long get_board_ddr_clk(void)
  116. {
  117. u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
  118. switch ((ddrclk_conf & 0x30) >> 4) {
  119. case QIXIS_DDRCLK_100:
  120. return 100000000;
  121. case QIXIS_DDRCLK_125:
  122. return 125000000;
  123. case QIXIS_DDRCLK_133:
  124. return 133333333;
  125. }
  126. return 66666666;
  127. }
  128. int select_i2c_ch_pca9547(u8 ch, int bus_num)
  129. {
  130. int ret;
  131. #ifdef CONFIG_DM_I2C
  132. struct udevice *dev;
  133. ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
  134. 1, &dev);
  135. if (ret) {
  136. printf("%s: Cannot find udev for a bus %d\n", __func__,
  137. bus_num);
  138. return ret;
  139. }
  140. ret = dm_i2c_write(dev, 0, &ch, 1);
  141. #else
  142. ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  143. #endif
  144. if (ret) {
  145. puts("PCA: failed to select proper channel\n");
  146. return ret;
  147. }
  148. return 0;
  149. }
  150. int dram_init(void)
  151. {
  152. /*
  153. * When resuming from deep sleep, the I2C channel may not be
  154. * in the default channel. So, switch to the default channel
  155. * before accessing DDR SPD.
  156. *
  157. * PCA9547(0x77) mount on I2C1 bus
  158. */
  159. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
  160. return fsl_initdram();
  161. }
  162. int board_early_init_f(void)
  163. {
  164. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  165. #ifdef CONFIG_TSEC_ENET
  166. /* clear BD & FR bits for BE BD's and frame data */
  167. clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
  168. #endif
  169. #ifdef CONFIG_FSL_IFC
  170. init_early_memctl_regs();
  171. #endif
  172. arch_soc_init();
  173. #if defined(CONFIG_DEEP_SLEEP)
  174. if (is_warm_boot())
  175. fsl_dp_disable_console();
  176. #endif
  177. return 0;
  178. }
  179. #ifdef CONFIG_SPL_BUILD
  180. void board_init_f(ulong dummy)
  181. {
  182. #ifdef CONFIG_NAND_BOOT
  183. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  184. u32 porsr1, pinctl;
  185. /*
  186. * There is LS1 SoC issue where NOR, FPGA are inaccessible during
  187. * NAND boot because IFC signals > IFC_AD7 are not enabled.
  188. * This workaround changes RCW source to make all signals enabled.
  189. */
  190. porsr1 = in_be32(&gur->porsr1);
  191. pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
  192. DCFG_CCSR_PORSR1_RCW_SRC_I2C);
  193. out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
  194. pinctl);
  195. #endif
  196. /* Clear the BSS */
  197. memset(__bss_start, 0, __bss_end - __bss_start);
  198. #ifdef CONFIG_FSL_IFC
  199. init_early_memctl_regs();
  200. #endif
  201. get_clocks();
  202. #if defined(CONFIG_DEEP_SLEEP)
  203. if (is_warm_boot())
  204. fsl_dp_disable_console();
  205. #endif
  206. preloader_console_init();
  207. #ifdef CONFIG_SPL_I2C_SUPPORT
  208. i2c_init_all();
  209. #endif
  210. timer_init();
  211. dram_init();
  212. /* Allow OCRAM access permission as R/W */
  213. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  214. enable_layerscape_ns_access();
  215. #endif
  216. board_init_r(NULL, 0);
  217. }
  218. #endif
  219. void config_etseccm_source(int etsec_gtx_125_mux)
  220. {
  221. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  222. switch (etsec_gtx_125_mux) {
  223. case GE0_CLK125:
  224. out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125);
  225. debug("etseccm set to GE0_CLK125\n");
  226. break;
  227. case GE2_CLK125:
  228. out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
  229. debug("etseccm set to GE2_CLK125\n");
  230. break;
  231. case GE1_CLK125:
  232. out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125);
  233. debug("etseccm set to GE1_CLK125\n");
  234. break;
  235. default:
  236. printf("Error! trying to set etseccm to invalid value\n");
  237. break;
  238. }
  239. }
  240. int config_board_mux(int ctrl_type)
  241. {
  242. u8 reg12, reg14;
  243. reg12 = QIXIS_READ(brdcfg[12]);
  244. reg14 = QIXIS_READ(brdcfg[14]);
  245. switch (ctrl_type) {
  246. case MUX_TYPE_CAN:
  247. config_etseccm_source(GE2_CLK125);
  248. reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
  249. break;
  250. case MUX_TYPE_IIC2:
  251. reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2);
  252. break;
  253. case MUX_TYPE_RGMII:
  254. reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
  255. break;
  256. case MUX_TYPE_SAI:
  257. config_etseccm_source(GE2_CLK125);
  258. reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
  259. break;
  260. case MUX_TYPE_SDHC:
  261. reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC);
  262. break;
  263. case MUX_TYPE_SD_PCI4:
  264. reg12 = 0x38;
  265. break;
  266. case MUX_TYPE_SD_PC_SA_SG_SG:
  267. reg12 = 0x01;
  268. break;
  269. case MUX_TYPE_SD_PC_SA_PC_SG:
  270. reg12 = 0x01;
  271. break;
  272. case MUX_TYPE_SD_PC_SG_SG:
  273. reg12 = 0x21;
  274. break;
  275. default:
  276. printf("Wrong mux interface type\n");
  277. return -1;
  278. }
  279. QIXIS_WRITE(brdcfg[12], reg12);
  280. QIXIS_WRITE(brdcfg[14], reg14);
  281. return 0;
  282. }
  283. int config_serdes_mux(void)
  284. {
  285. struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
  286. u32 cfg;
  287. cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
  288. cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
  289. switch (cfg) {
  290. case 0x0:
  291. config_board_mux(MUX_TYPE_SD_PCI4);
  292. break;
  293. case 0x30:
  294. config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG);
  295. break;
  296. case 0x60:
  297. config_board_mux(MUX_TYPE_SD_PC_SG_SG);
  298. break;
  299. case 0x70:
  300. config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG);
  301. break;
  302. default:
  303. printf("SRDS1 prtcl:0x%x\n", cfg);
  304. break;
  305. }
  306. return 0;
  307. }
  308. #ifdef CONFIG_BOARD_LATE_INIT
  309. int board_late_init(void)
  310. {
  311. #ifdef CONFIG_CHAIN_OF_TRUST
  312. fsl_setenv_chain_of_trust();
  313. #endif
  314. return 0;
  315. }
  316. #endif
  317. int misc_init_r(void)
  318. {
  319. int conflict_flag;
  320. /* some signals can not enable simultaneous*/
  321. conflict_flag = 0;
  322. if (hwconfig("sdhc"))
  323. conflict_flag++;
  324. if (hwconfig("iic2"))
  325. conflict_flag++;
  326. if (conflict_flag > 1) {
  327. printf("WARNING: pin conflict !\n");
  328. return 0;
  329. }
  330. conflict_flag = 0;
  331. if (hwconfig("rgmii"))
  332. conflict_flag++;
  333. if (hwconfig("can"))
  334. conflict_flag++;
  335. if (hwconfig("sai"))
  336. conflict_flag++;
  337. if (conflict_flag > 1) {
  338. printf("WARNING: pin conflict !\n");
  339. return 0;
  340. }
  341. if (hwconfig("can"))
  342. config_board_mux(MUX_TYPE_CAN);
  343. else if (hwconfig("rgmii"))
  344. config_board_mux(MUX_TYPE_RGMII);
  345. else if (hwconfig("sai"))
  346. config_board_mux(MUX_TYPE_SAI);
  347. if (hwconfig("iic2"))
  348. config_board_mux(MUX_TYPE_IIC2);
  349. else if (hwconfig("sdhc"))
  350. config_board_mux(MUX_TYPE_SDHC);
  351. #ifdef CONFIG_FSL_DEVICE_DISABLE
  352. device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
  353. #endif
  354. #ifdef CONFIG_FSL_CAAM
  355. return sec_init();
  356. #endif
  357. return 0;
  358. }
  359. int board_init(void)
  360. {
  361. #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
  362. erratum_a010315();
  363. #endif
  364. #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
  365. erratum_a009942_check_cpo();
  366. #endif
  367. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
  368. #ifndef CONFIG_SYS_FSL_NO_SERDES
  369. fsl_serdes_init();
  370. config_serdes_mux();
  371. #endif
  372. ls102xa_smmu_stream_id_init();
  373. #ifdef CONFIG_U_QE
  374. u_qe_init();
  375. #endif
  376. return 0;
  377. }
  378. #if defined(CONFIG_DEEP_SLEEP)
  379. void board_sleep_prepare(void)
  380. {
  381. #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  382. enable_layerscape_ns_access();
  383. #endif
  384. }
  385. #endif
  386. int ft_board_setup(void *blob, struct bd_info *bd)
  387. {
  388. ft_cpu_setup(blob, bd);
  389. #ifdef CONFIG_PCI
  390. ft_pci_setup(blob, bd);
  391. #endif
  392. return 0;
  393. }
  394. u8 flash_read8(void *addr)
  395. {
  396. return __raw_readb(addr + 1);
  397. }
  398. void flash_write16(u16 val, void *addr)
  399. {
  400. u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
  401. __raw_writew(shftval, addr);
  402. }
  403. u16 flash_read16(void *addr)
  404. {
  405. u16 val = __raw_readw(addr);
  406. return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
  407. }