ddr.c 4.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <fsl_ddr_sdram.h>
  7. #include <fsl_ddr_dimm_params.h>
  8. #include <init.h>
  9. #include <log.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/clock.h>
  12. #include <linux/delay.h>
  13. #include "ddr.h"
  14. DECLARE_GLOBAL_DATA_PTR;
  15. void fsl_ddr_board_options(memctl_options_t *popts,
  16. dimm_params_t *pdimm,
  17. unsigned int ctrl_num)
  18. {
  19. const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  20. ulong ddr_freq;
  21. if (ctrl_num > 3) {
  22. printf("Not supported controller number %d\n", ctrl_num);
  23. return;
  24. }
  25. if (!pdimm->n_ranks)
  26. return;
  27. pbsp = udimms[0];
  28. /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
  29. * freqency and n_banks specified in board_specific_parameters table.
  30. */
  31. ddr_freq = get_ddr_freq(0) / 1000000;
  32. while (pbsp->datarate_mhz_high) {
  33. if (pbsp->n_ranks == pdimm->n_ranks) {
  34. if (ddr_freq <= pbsp->datarate_mhz_high) {
  35. popts->clk_adjust = pbsp->clk_adjust;
  36. popts->wrlvl_start = pbsp->wrlvl_start;
  37. popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  38. popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  39. popts->cpo_override = pbsp->cpo_override;
  40. popts->write_data_delay =
  41. pbsp->write_data_delay;
  42. goto found;
  43. }
  44. pbsp_highest = pbsp;
  45. }
  46. pbsp++;
  47. }
  48. if (pbsp_highest) {
  49. printf("Error: board specific timing not found for %lu MT/s\n",
  50. ddr_freq);
  51. printf("Trying to use the highest speed (%u) parameters\n",
  52. pbsp_highest->datarate_mhz_high);
  53. popts->clk_adjust = pbsp_highest->clk_adjust;
  54. popts->wrlvl_start = pbsp_highest->wrlvl_start;
  55. popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  56. popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  57. } else {
  58. panic("DIMM is not supported by this board");
  59. }
  60. found:
  61. debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
  62. pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
  63. /* force DDR bus width to 32 bits */
  64. popts->data_bus_width = 1;
  65. popts->otf_burst_chop_en = 0;
  66. popts->burst_length = DDR_BL8;
  67. /*
  68. * Factors to consider for half-strength driver enable:
  69. * - number of DIMMs installed
  70. */
  71. popts->half_strength_driver_enable = 1;
  72. /*
  73. * Write leveling override
  74. */
  75. popts->wrlvl_override = 1;
  76. popts->wrlvl_sample = 0xf;
  77. /*
  78. * Rtt and Rtt_WR override
  79. */
  80. popts->rtt_override = 0;
  81. /* Enable ZQ calibration */
  82. popts->zq_en = 1;
  83. #ifdef CONFIG_SYS_FSL_DDR4
  84. popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
  85. popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
  86. DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
  87. #else
  88. popts->cswl_override = DDR_CSWL_CS0;
  89. /* optimize cpo for erratum A-009942 */
  90. popts->cpo_sample = 0x58;
  91. /* DHC_EN =1, ODT = 75 Ohm */
  92. popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
  93. popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
  94. #endif
  95. }
  96. #ifdef CONFIG_SYS_DDR_RAW_TIMING
  97. dimm_params_t ddr_raw_timing = {
  98. .n_ranks = 1,
  99. .rank_density = 1073741824u,
  100. .capacity = 1073741824u,
  101. .primary_sdram_width = 32,
  102. .ec_sdram_width = 0,
  103. .registered_dimm = 0,
  104. .mirrored_dimm = 0,
  105. .n_row_addr = 15,
  106. .n_col_addr = 10,
  107. .n_banks_per_sdram_device = 8,
  108. .edc_config = 0,
  109. .burst_lengths_bitmask = 0x0c,
  110. .tckmin_x_ps = 1071,
  111. .caslat_x = 0xfe << 4, /* 5,6,7,8 */
  112. .taa_ps = 13125,
  113. .twr_ps = 15000,
  114. .trcd_ps = 13125,
  115. .trrd_ps = 7500,
  116. .trp_ps = 13125,
  117. .tras_ps = 37500,
  118. .trc_ps = 50625,
  119. .trfc_ps = 160000,
  120. .twtr_ps = 7500,
  121. .trtp_ps = 7500,
  122. .refresh_rate_ps = 7800000,
  123. .tfaw_ps = 37500,
  124. };
  125. int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
  126. unsigned int controller_number,
  127. unsigned int dimm_number)
  128. {
  129. static const char dimm_model[] = "Fixed DDR on board";
  130. if (((controller_number == 0) && (dimm_number == 0)) ||
  131. ((controller_number == 1) && (dimm_number == 0))) {
  132. memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
  133. memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
  134. memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
  135. }
  136. return 0;
  137. }
  138. #endif
  139. #if defined(CONFIG_DEEP_SLEEP)
  140. void board_mem_sleep_setup(void)
  141. {
  142. void __iomem *qixis_base = (void *)QIXIS_BASE;
  143. /* does not provide HW signals for power management */
  144. clrbits_8(qixis_base + 0x21, 0x2);
  145. udelay(1);
  146. }
  147. #endif
  148. int fsl_initdram(void)
  149. {
  150. phys_size_t dram_size;
  151. #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
  152. puts("Initializing DDR....using SPD\n");
  153. dram_size = fsl_ddr_sdram();
  154. #else
  155. dram_size = fsl_ddr_sdram_size();
  156. #endif
  157. #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
  158. fsl_dp_resume();
  159. #endif
  160. erratum_a008850_post();
  161. gd->ram_size = dram_size;
  162. return 0;
  163. }
  164. int dram_init_banksize(void)
  165. {
  166. gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  167. gd->bd->bi_dram[0].size = gd->ram_size;
  168. return 0;
  169. }