dcu.c 2.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. * Copyright 2019 NXP
  5. *
  6. * FSL DCU Framebuffer driver
  7. */
  8. #include <asm/io.h>
  9. #include <common.h>
  10. #include <fsl_dcu_fb.h>
  11. #include <i2c.h>
  12. #include "div64.h"
  13. #include "../common/diu_ch7301.h"
  14. #include "ls1021aqds_qixis.h"
  15. DECLARE_GLOBAL_DATA_PTR;
  16. static int select_i2c_ch_pca9547(u8 ch, int bus_num)
  17. {
  18. int ret;
  19. #ifdef CONFIG_DM_I2C
  20. struct udevice *dev;
  21. ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
  22. 1, &dev);
  23. if (ret) {
  24. printf("%s: Cannot find udev for a bus %d\n", __func__,
  25. bus_num);
  26. return ret;
  27. }
  28. ret = dm_i2c_write(dev, 0, &ch, 1);
  29. #else
  30. ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  31. #endif
  32. if (ret) {
  33. puts("PCA: failed to select proper channel\n");
  34. return ret;
  35. }
  36. return 0;
  37. }
  38. unsigned int dcu_set_pixel_clock(unsigned int pixclock)
  39. {
  40. unsigned long long div;
  41. div = (unsigned long long)(gd->bus_clk / 1000);
  42. div *= (unsigned long long)pixclock;
  43. do_div(div, 1000000000);
  44. return div;
  45. }
  46. int platform_dcu_init(struct fb_info *fbinfo,
  47. unsigned int xres,
  48. unsigned int yres,
  49. const char *port,
  50. struct fb_videomode *dcu_fb_videomode)
  51. {
  52. const char *name;
  53. unsigned int pixel_format;
  54. int ret;
  55. u8 ch;
  56. /* Mux I2C3+I2C4 as HSYNC+VSYNC */
  57. #ifdef CONFIG_DM_I2C
  58. struct udevice *dev;
  59. /* QIXIS device mount on I2C1 bus*/
  60. ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_QIXIS_ADDR,
  61. 1, &dev);
  62. if (ret) {
  63. printf("%s: Cannot find udev for a bus %d\n", __func__,
  64. 0);
  65. return ret;
  66. }
  67. ret = dm_i2c_read(dev, QIXIS_DCU_BRDCFG5, &ch, 1);
  68. if (ret) {
  69. printf("Error: failed to read I2C @%02x\n",
  70. CONFIG_SYS_I2C_QIXIS_ADDR);
  71. return ret;
  72. }
  73. ch &= 0x1F;
  74. ch |= 0xA0;
  75. ret = dm_i2c_write(dev, QIXIS_DCU_BRDCFG5, &ch, 1);
  76. #else
  77. ret = i2c_read(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5,
  78. 1, &ch, 1);
  79. if (ret) {
  80. printf("Error: failed to read I2C @%02x\n",
  81. CONFIG_SYS_I2C_QIXIS_ADDR);
  82. return ret;
  83. }
  84. ch &= 0x1F;
  85. ch |= 0xA0;
  86. ret = i2c_write(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5,
  87. 1, &ch, 1);
  88. #endif
  89. if (ret) {
  90. printf("Error: failed to write I2C @%02x\n",
  91. CONFIG_SYS_I2C_QIXIS_ADDR);
  92. return ret;
  93. }
  94. if (strncmp(port, "hdmi", 4) == 0) {
  95. unsigned long pixval;
  96. name = "HDMI";
  97. pixval = 1000000000 / dcu_fb_videomode->pixclock;
  98. pixval *= 1000;
  99. #ifndef CONFIG_DM_I2C
  100. i2c_set_bus_num(CONFIG_SYS_I2C_DVI_BUS_NUM);
  101. #endif
  102. select_i2c_ch_pca9547(I2C_MUX_CH_CH7301,
  103. CONFIG_SYS_I2C_DVI_BUS_NUM);
  104. diu_set_dvi_encoder(pixval);
  105. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT,
  106. CONFIG_SYS_I2C_DVI_BUS_NUM);
  107. } else {
  108. return 0;
  109. }
  110. printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres);
  111. pixel_format = 32;
  112. fsl_dcu_init(fbinfo, xres, yres, pixel_format);
  113. return 0;
  114. }