spl.c 2.6 KB

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  1. /*
  2. * Copyright 2018-2019 NXP
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <command.h>
  8. #include <cpu_func.h>
  9. #include <hang.h>
  10. #include <image.h>
  11. #include <init.h>
  12. #include <log.h>
  13. #include <spl.h>
  14. #include <asm/io.h>
  15. #include <errno.h>
  16. #include <asm/io.h>
  17. #include <asm/mach-imx/iomux-v3.h>
  18. #include <asm/arch/imx8mp_pins.h>
  19. #include <asm/arch/sys_proto.h>
  20. #include <asm/mach-imx/boot_mode.h>
  21. #include <power/pmic.h>
  22. #include <power/pca9450.h>
  23. #include <asm/arch/clock.h>
  24. #include <asm/mach-imx/gpio.h>
  25. #include <asm/mach-imx/mxc_i2c.h>
  26. #include <fsl_esdhc.h>
  27. #include <mmc.h>
  28. #include <asm/arch/ddr.h>
  29. DECLARE_GLOBAL_DATA_PTR;
  30. int spl_board_boot_device(enum boot_device boot_dev_spl)
  31. {
  32. return BOOT_DEVICE_BOOTROM;
  33. }
  34. void spl_dram_init(void)
  35. {
  36. ddr_init(&dram_timing);
  37. }
  38. void spl_board_init(void)
  39. {
  40. puts("Normal Boot\n");
  41. }
  42. #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
  43. #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  44. struct i2c_pads_info i2c_pad_info1 = {
  45. .scl = {
  46. .i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
  47. .gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
  48. .gp = IMX_GPIO_NR(5, 14),
  49. },
  50. .sda = {
  51. .i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
  52. .gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
  53. .gp = IMX_GPIO_NR(5, 15),
  54. },
  55. };
  56. #ifdef CONFIG_POWER
  57. #define I2C_PMIC 0
  58. int power_init_board(void)
  59. {
  60. struct pmic *p;
  61. int ret;
  62. ret = power_pca9450_init(I2C_PMIC);
  63. if (ret)
  64. printf("power init failed");
  65. p = pmic_get("PCA9450");
  66. pmic_probe(p);
  67. /* BUCKxOUT_DVS0/1 control BUCK123 output */
  68. pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
  69. /*
  70. * increase VDD_SOC to typical value 0.95V before first
  71. * DRAM access, set DVS1 to 0.85v for suspend.
  72. * Enable DVS control through PMIC_STBY_REQ and
  73. * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
  74. */
  75. pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C);
  76. pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
  77. pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
  78. /* set WDOG_B_CFG to cold reset */
  79. pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
  80. return 0;
  81. }
  82. #endif
  83. #ifdef CONFIG_SPL_LOAD_FIT
  84. int board_fit_config_name_match(const char *name)
  85. {
  86. /* Just empty function now - can't decide what to choose */
  87. debug("%s: %s\n", __func__, name);
  88. return 0;
  89. }
  90. #endif
  91. /* Do not use BSS area in this phase */
  92. void board_init_f(ulong dummy)
  93. {
  94. int ret;
  95. arch_cpu_init();
  96. init_uart_clk(1);
  97. board_early_init_f();
  98. ret = spl_early_init();
  99. if (ret) {
  100. debug("spl_init() failed: %d\n", ret);
  101. hang();
  102. }
  103. preloader_console_init();
  104. enable_tzc380();
  105. setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  106. power_init_board();
  107. /* DDR initialization */
  108. spl_dram_init();
  109. }