imx8mm_evk.c 1.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2018 NXP
  4. */
  5. #include <common.h>
  6. #include <env.h>
  7. #include <init.h>
  8. #include <miiphy.h>
  9. #include <netdev.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch/sys_proto.h>
  12. #include <asm/io.h>
  13. DECLARE_GLOBAL_DATA_PTR;
  14. #if IS_ENABLED(CONFIG_FEC_MXC)
  15. static int setup_fec(void)
  16. {
  17. struct iomuxc_gpr_base_regs *gpr =
  18. (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  19. /* Use 125M anatop REF_CLK1 for ENET1, not from external */
  20. clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
  21. return 0;
  22. }
  23. int board_phy_config(struct phy_device *phydev)
  24. {
  25. /* enable rgmii rxc skew and phy mode select to RGMII copper */
  26. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
  27. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
  28. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
  29. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
  30. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
  31. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
  32. if (phydev->drv->config)
  33. phydev->drv->config(phydev);
  34. return 0;
  35. }
  36. #endif
  37. int board_init(void)
  38. {
  39. if (IS_ENABLED(CONFIG_FEC_MXC))
  40. setup_fec();
  41. return 0;
  42. }
  43. int board_mmc_get_env_dev(int devno)
  44. {
  45. return devno;
  46. }
  47. int board_late_init(void)
  48. {
  49. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  50. env_set("board_name", "EVK");
  51. env_set("board_rev", "iMX8MM");
  52. #endif
  53. return 0;
  54. }