idt8t49n222a_serdes_clk.h 3.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2013 Freescale Semiconductor, Inc.
  4. * Author: Shaveta Leekha <shaveta@freescale.com>
  5. */
  6. #ifndef __IDT8T49N222A_SERDES_CLK_H_
  7. #define __IDT8T49N222A_SERDES_CLK_H_ 1
  8. #include <common.h>
  9. #include <i2c.h>
  10. #include "qixis.h"
  11. #include "../b4860qds/b4860qds_qixis.h"
  12. #include <errno.h>
  13. #define NUM_IDT_REGS 23
  14. #define NUM_IDT_REGS_FEEDBACK 12
  15. #define NUM_IDT_REGS_156_25 11
  16. /* CLK */
  17. enum serdes_refclk {
  18. SERDES_REFCLK_100, /* refclk 100Mhz */
  19. SERDES_REFCLK_122_88, /* refclk 122.88Mhz */
  20. SERDES_REFCLK_125, /* refclk 125Mhz */
  21. SERDES_REFCLK_156_25, /* refclk 156.25Mhz */
  22. SERDES_REFCLK_NONE = -1,
  23. };
  24. /* configuration values for IDT registers for Output Refclks:
  25. * Refclk1 = 122.88MHz Refclk2 = 122.88MHz
  26. */
  27. static const u8 idt_conf_122_88[23][2] = { {0x00, 0x3C}, {0x01, 0x00},
  28. {0x02, 0x9F}, {0x03, 0x00}, {0x04, 0x0B}, {0x05, 0x00},
  29. {0x06, 0x00}, {0x07, 0x00}, {0x08, 0x7D}, {0x09, 0x00},
  30. {0x0A, 0x08}, {0x0B, 0x00}, {0x0C, 0xDC}, {0x0D, 0x00},
  31. {0x0E, 0x00}, {0x0F, 0x00}, {0x10, 0x12}, {0x11, 0x12},
  32. {0x12, 0xB9}, {0x13, 0xBC}, {0x14, 0x40}, {0x15, 0x08},
  33. {0x16, 0xA0} };
  34. /* configuration values for IDT registers for Output Refclks:
  35. * Refclk1 not equal to 122.88MHz Refclk2 not equal to 122.88MHz
  36. */
  37. static const u8 idt_conf_not_122_88[23][2] = { {0x00, 0x00}, {0x01, 0x00},
  38. {0x02, 0x00}, {0x03, 0x00}, {0x04, 0x0A}, {0x05, 0x00},
  39. {0x06, 0x00}, {0x07, 0x00}, {0x08, 0x7D}, {0x09, 0x00},
  40. {0x0A, 0x08}, {0x0B, 0x00}, {0x0C, 0xDC}, {0x0D, 0x00},
  41. {0x0E, 0x00}, {0x0F, 0x00}, {0x10, 0x14}, {0x11, 0x14},
  42. {0x12, 0x35}, {0x13, 0xBC}, {0x14, 0x40}, {0x15, 0x08},
  43. {0x16, 0xA0} };
  44. /* Reconfiguration values for some of IDT registers for
  45. * Output Refclks:
  46. * Refclk1 = 122.88MHz Refclk2 = 122.88MHz
  47. * and with feedback as 1
  48. */
  49. static const u8 idt_conf_122_88_feedback[12][2] = { {0x00, 0x50}, {0x02, 0xD7},
  50. {0x04, 0x89}, {0x06, 0xC3}, {0x08, 0xC0}, {0x0A, 0x07},
  51. {0x0C, 0x80}, {0x10, 0x10}, {0x11, 0x10}, {0x12, 0x1B},
  52. {0x14, 0x00}, {0x15, 0xE8} };
  53. /* configuration values for IDT registers for Output Refclks:
  54. * Refclk1 : 156.25MHz Refclk2 : 156.25MHz
  55. */
  56. static const u8 idt_conf_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03},
  57. {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
  58. {0x10, 0x10}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C},
  59. {0x15, 0xE8} };
  60. /* configuration values for IDT registers for Output Refclks:
  61. * Refclk1 : 100MHz Refclk2 : 156.25MHz
  62. */
  63. static const u8 idt_conf_100_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03},
  64. {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
  65. {0x10, 0x19}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C},
  66. {0x15, 0xE8} };
  67. /* configuration values for IDT registers for Output Refclks:
  68. * Refclk1 : 125MHz Refclk2 : 156.25MHz
  69. */
  70. static const u8 idt_conf_125_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03},
  71. {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
  72. {0x10, 0x14}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C},
  73. {0x15, 0xE8} };
  74. /* configuration values for IDT registers for Output Refclks:
  75. * Refclk1 : 156.25MHz Refclk2 : 100MHz
  76. */
  77. static const u8 idt_conf_156_25_100[11][2] = { {0x04, 0x19}, {0x06, 0x03},
  78. {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
  79. {0x10, 0x10}, {0x11, 0x19}, {0x12, 0xB5}, {0x13, 0x3C},
  80. {0x15, 0xE8} };
  81. /* configuration values for IDT registers for Output Refclks:
  82. * Refclk1 : 156.25MHz Refclk2 : 125MHz
  83. */
  84. static const u8 idt_conf_156_25_125[11][2] = { {0x04, 0x19}, {0x06, 0x03},
  85. {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
  86. {0x10, 0x10}, {0x11, 0x14}, {0x12, 0xB5}, {0x13, 0x3C},
  87. {0x15, 0xE8} };
  88. int set_serdes_refclk(u8 idt_addr, u8 serdes_num,
  89. enum serdes_refclk refclk1,
  90. enum serdes_refclk refclk2, u8 feedback);
  91. #endif /*__IDT8T49N222A_SERDES_CLK_H_ */