idt8t49n222a_serdes_clk.c 5.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2013 Freescale Semiconductor, Inc.
  4. * Author: Shaveta Leekha <shaveta@freescale.com>
  5. */
  6. #include "idt8t49n222a_serdes_clk.h"
  7. #include <log.h>
  8. #include <linux/delay.h>
  9. #define DEVICE_ID_REG 0x00
  10. static int check_pll_status(u8 idt_addr)
  11. {
  12. u8 val = 0;
  13. int ret;
  14. ret = i2c_read(idt_addr, 0x17, 1, &val, 1);
  15. if (ret < 0) {
  16. printf("IDT:0x%x could not read status register from device.\n",
  17. idt_addr);
  18. return ret;
  19. }
  20. if (val & 0x04) {
  21. debug("idt8t49n222a PLL is LOCKED: %x\n", val);
  22. } else {
  23. printf("idt8t49n222a PLL is not LOCKED: %x\n", val);
  24. return -1;
  25. }
  26. return 0;
  27. }
  28. int set_serdes_refclk(u8 idt_addr, u8 serdes_num,
  29. enum serdes_refclk refclk1,
  30. enum serdes_refclk refclk2, u8 feedback)
  31. {
  32. u8 dev_id = 0;
  33. int i, ret;
  34. debug("IDT:Configuring idt8t49n222a device at I2C address: 0x%2x\n",
  35. idt_addr);
  36. ret = i2c_read(idt_addr, DEVICE_ID_REG, 1, &dev_id, 1);
  37. if (ret < 0) {
  38. debug("IDT:0x%x could not read DEV_ID from device.\n",
  39. idt_addr);
  40. return ret;
  41. }
  42. if ((dev_id != 0x00) && (dev_id != 0x24) && (dev_id != 0x2a)) {
  43. debug("IDT: device at address 0x%x is not idt8t49n222a.\n",
  44. idt_addr);
  45. }
  46. if (serdes_num != 1 && serdes_num != 2) {
  47. debug("serdes_num should be 1 for SerDes1 and"
  48. " 2 for SerDes2.\n");
  49. return -1;
  50. }
  51. if ((refclk1 == SERDES_REFCLK_122_88 && refclk2 != SERDES_REFCLK_122_88)
  52. || (refclk1 != SERDES_REFCLK_122_88
  53. && refclk2 == SERDES_REFCLK_122_88)) {
  54. debug("Only one refclk at 122.88MHz is not supported."
  55. " Please set both refclk1 & refclk2 to 122.88MHz"
  56. " or both not to 122.88MHz.\n");
  57. return -1;
  58. }
  59. if (refclk1 != SERDES_REFCLK_100 && refclk1 != SERDES_REFCLK_122_88
  60. && refclk1 != SERDES_REFCLK_125
  61. && refclk1 != SERDES_REFCLK_156_25) {
  62. debug("refclk1 should be 100MHZ, 122.88MHz, 125MHz"
  63. " or 156.25MHz.\n");
  64. return -1;
  65. }
  66. if (refclk2 != SERDES_REFCLK_100 && refclk2 != SERDES_REFCLK_122_88
  67. && refclk2 != SERDES_REFCLK_125
  68. && refclk2 != SERDES_REFCLK_156_25) {
  69. debug("refclk2 should be 100MHZ, 122.88MHz, 125MHz"
  70. " or 156.25MHz.\n");
  71. return -1;
  72. }
  73. if (feedback != 0 && feedback != 1) {
  74. debug("valid values for feedback are 0(default) or 1.\n");
  75. return -1;
  76. }
  77. /* Configuring IDT for output refclks as
  78. * Refclk1 = 122.88MHz Refclk2 = 122.88MHz
  79. */
  80. if (refclk1 == SERDES_REFCLK_122_88 &&
  81. refclk2 == SERDES_REFCLK_122_88) {
  82. printf("Setting refclk1:122.88 and refclk2:122.88\n");
  83. for (i = 0; i < NUM_IDT_REGS; i++)
  84. i2c_reg_write(idt_addr, idt_conf_122_88[i][0],
  85. idt_conf_122_88[i][1]);
  86. if (feedback) {
  87. for (i = 0; i < NUM_IDT_REGS_FEEDBACK; i++)
  88. i2c_reg_write(idt_addr,
  89. idt_conf_122_88_feedback[i][0],
  90. idt_conf_122_88_feedback[i][1]);
  91. }
  92. }
  93. if (refclk1 != SERDES_REFCLK_122_88 &&
  94. refclk2 != SERDES_REFCLK_122_88) {
  95. for (i = 0; i < NUM_IDT_REGS; i++)
  96. i2c_reg_write(idt_addr, idt_conf_not_122_88[i][0],
  97. idt_conf_not_122_88[i][1]);
  98. }
  99. /* Configuring IDT for output refclks as
  100. * Refclk1 = 100MHz Refclk2 = 125MHz
  101. */
  102. if (refclk1 == SERDES_REFCLK_100 && refclk2 == SERDES_REFCLK_125) {
  103. printf("Setting refclk1:100 and refclk2:125\n");
  104. i2c_reg_write(idt_addr, 0x11, 0x10);
  105. }
  106. /* Configuring IDT for output refclks as
  107. * Refclk1 = 125MHz Refclk2 = 125MHz
  108. */
  109. if (refclk1 == SERDES_REFCLK_125 && refclk2 == SERDES_REFCLK_125) {
  110. printf("Setting refclk1:125 and refclk2:125\n");
  111. i2c_reg_write(idt_addr, 0x10, 0x10);
  112. i2c_reg_write(idt_addr, 0x11, 0x10);
  113. }
  114. /* Configuring IDT for output refclks as
  115. * Refclk1 = 125MHz Refclk2 = 100MHz
  116. */
  117. if (refclk1 == SERDES_REFCLK_125 && refclk2 == SERDES_REFCLK_100) {
  118. printf("Setting refclk1:125 and refclk2:100\n");
  119. i2c_reg_write(idt_addr, 0x10, 0x10);
  120. }
  121. /* Configuring IDT for output refclks as
  122. * Refclk1 = 156.25MHz Refclk2 = 156.25MHz
  123. */
  124. if (refclk1 == SERDES_REFCLK_156_25 &&
  125. refclk2 == SERDES_REFCLK_156_25) {
  126. printf("Setting refclk1:156.25 and refclk2:156.25\n");
  127. for (i = 0; i < NUM_IDT_REGS_156_25; i++)
  128. i2c_reg_write(idt_addr, idt_conf_156_25[i][0],
  129. idt_conf_156_25[i][1]);
  130. }
  131. /* Configuring IDT for output refclks as
  132. * Refclk1 = 100MHz Refclk2 = 156.25MHz
  133. */
  134. if (refclk1 == SERDES_REFCLK_100 &&
  135. refclk2 == SERDES_REFCLK_156_25) {
  136. printf("Setting refclk1:100 and refclk2:156.25\n");
  137. for (i = 0; i < NUM_IDT_REGS_156_25; i++)
  138. i2c_reg_write(idt_addr, idt_conf_100_156_25[i][0],
  139. idt_conf_100_156_25[i][1]);
  140. }
  141. /* Configuring IDT for output refclks as
  142. * Refclk1 = 125MHz Refclk2 = 156.25MHz
  143. */
  144. if (refclk1 == SERDES_REFCLK_125 &&
  145. refclk2 == SERDES_REFCLK_156_25) {
  146. printf("Setting refclk1:125 and refclk2:156.25\n");
  147. for (i = 0; i < NUM_IDT_REGS_156_25; i++)
  148. i2c_reg_write(idt_addr, idt_conf_125_156_25[i][0],
  149. idt_conf_125_156_25[i][1]);
  150. }
  151. /* Configuring IDT for output refclks as
  152. * Refclk1 = 156.25MHz Refclk2 = 100MHz
  153. */
  154. if (refclk1 == SERDES_REFCLK_156_25 &&
  155. refclk2 == SERDES_REFCLK_100) {
  156. printf("Setting refclk1:156.25 and refclk2:100\n");
  157. for (i = 0; i < NUM_IDT_REGS_156_25; i++)
  158. i2c_reg_write(idt_addr, idt_conf_156_25_100[i][0],
  159. idt_conf_156_25_100[i][1]);
  160. }
  161. /* Configuring IDT for output refclks as
  162. * Refclk1 = 156.25MHz Refclk2 = 125MHz
  163. */
  164. if (refclk1 == SERDES_REFCLK_156_25 &&
  165. refclk2 == SERDES_REFCLK_125) {
  166. printf("Setting refclk1:156.25 and refclk2:125\n");
  167. for (i = 0; i < NUM_IDT_REGS_156_25; i++)
  168. i2c_reg_write(idt_addr, idt_conf_156_25_125[i][0],
  169. idt_conf_156_25_125[i][1]);
  170. }
  171. /* waiting for maximum of 1 second if PLL doesn'r get locked
  172. * initially. then check the status again.
  173. */
  174. if (check_pll_status(idt_addr)) {
  175. mdelay(1000);
  176. if (check_pll_status(idt_addr))
  177. return -1;
  178. }
  179. return 0;
  180. }