ics307_clk.c 3.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2010-2011 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <log.h>
  7. #include <asm/io.h>
  8. #include "ics307_clk.h"
  9. #if defined(CONFIG_FSL_NGPIXIS)
  10. #include "ngpixis.h"
  11. #define fpga_reg pixis
  12. #elif defined(CONFIG_FSL_QIXIS)
  13. #include "qixis.h"
  14. #define fpga_reg ((struct qixis *)QIXIS_BASE)
  15. #else
  16. #include "pixis.h"
  17. #define fpga_reg pixis
  18. #endif
  19. /* define for SYS CLK or CLK1Frequency */
  20. #define TTL 1
  21. #define CLK2 0
  22. #define CRYSTAL 0
  23. #define MAX_VDW (511 + 8)
  24. #define MAX_RDW (127 + 2)
  25. #define MIN_VDW (4 + 8)
  26. #define MIN_RDW (1 + 2)
  27. #define NUM_OD_SETTING 8
  28. /*
  29. * These defines cover the industrial temperature range part,
  30. * for commercial, change below to 400000 and 55000, respectively
  31. */
  32. #define MAX_VCO 360000
  33. #define MIN_VCO 60000
  34. /* decode S[0-2] to Output Divider (OD) */
  35. static u8 ics307_s_to_od[] = {
  36. 10, 2, 8, 4, 5, 7, 3, 6
  37. };
  38. /*
  39. * Find one solution to generate required frequency for SYSCLK
  40. * out_freq: KHz, required frequency to the SYSCLK
  41. * the result will be retuned with component RDW, VDW, OD, TTL,
  42. * CLK2 and crystal
  43. */
  44. unsigned long ics307_sysclk_calculator(unsigned long out_freq)
  45. {
  46. const unsigned long input_freq = CONFIG_ICS307_REFCLK_HZ;
  47. unsigned long vdw, rdw, odp, s_vdw = 0, s_rdw = 0, s_odp = 0, od;
  48. unsigned long tmp_out, diff, result = 0;
  49. int found = 0;
  50. for (odp = 0; odp < NUM_OD_SETTING; odp++) {
  51. od = ics307_s_to_od[odp];
  52. if (od * out_freq < MIN_VCO || od * out_freq > MAX_VCO)
  53. continue;
  54. for (rdw = MIN_RDW; rdw <= MAX_RDW; rdw++) {
  55. /* Calculate the VDW */
  56. vdw = out_freq * 1000 * od * rdw / (input_freq * 2);
  57. if (vdw > MAX_VDW)
  58. vdw = MAX_VDW;
  59. if (vdw < MIN_VDW)
  60. continue;
  61. /* Calculate the temp out frequency */
  62. tmp_out = input_freq * 2 * vdw / (rdw * od * 1000);
  63. diff = max(out_freq, tmp_out) - min(out_freq, tmp_out);
  64. /*
  65. * calculate the percent, the precision is 1/1000
  66. * If greater than 1/1000, continue
  67. * otherwise, we think the solution is we required
  68. */
  69. if (diff * 1000 / out_freq > 1)
  70. continue;
  71. else {
  72. s_vdw = vdw;
  73. s_rdw = rdw;
  74. s_odp = odp;
  75. found = 1;
  76. break;
  77. }
  78. }
  79. }
  80. if (found)
  81. result = (s_rdw - 2) | (s_vdw - 8) << 7 | s_odp << 16 |
  82. CLK2 << 19 | TTL << 21 | CRYSTAL << 22;
  83. debug("ICS307-02: RDW: %ld, VDW: %ld, OD: %d\n", s_rdw - 2, s_vdw - 8,
  84. ics307_s_to_od[s_odp]);
  85. return result;
  86. }
  87. /*
  88. * Calculate frequency being generated by ICS307-02 clock chip based upon
  89. * the control bytes being programmed into it.
  90. */
  91. static unsigned long ics307_clk_freq(u8 cw0, u8 cw1, u8 cw2)
  92. {
  93. const unsigned long input_freq = CONFIG_ICS307_REFCLK_HZ;
  94. unsigned long vdw = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
  95. unsigned long rdw = cw2 & 0x7F;
  96. unsigned long od = ics307_s_to_od[cw0 & 0x7];
  97. unsigned long freq;
  98. /*
  99. * CLK1 Freq = Input Frequency * 2 * (VDW + 8) / ((RDW + 2) * OD)
  100. *
  101. * cw0: C1 C0 TTL F1 F0 S2 S1 S0
  102. * cw1: V8 V7 V6 V5 V4 V3 V2 V1
  103. * cw2: V0 R6 R5 R4 R3 R2 R1 R0
  104. *
  105. * R6:R0 = Reference Divider Word (RDW)
  106. * V8:V0 = VCO Divider Word (VDW)
  107. * S2:S0 = Output Divider Select (OD)
  108. * F1:F0 = Function of CLK2 Output
  109. * TTL = duty cycle
  110. * C1:C0 = internal load capacitance for cyrstal
  111. *
  112. */
  113. freq = input_freq * 2 * (vdw + 8) / ((rdw + 2) * od);
  114. debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2,
  115. freq);
  116. return freq;
  117. }
  118. unsigned long get_board_sys_clk(void)
  119. {
  120. return ics307_clk_freq(
  121. in_8(&fpga_reg->sclk[0]),
  122. in_8(&fpga_reg->sclk[1]),
  123. in_8(&fpga_reg->sclk[2]));
  124. }
  125. unsigned long get_board_ddr_clk(void)
  126. {
  127. return ics307_clk_freq(
  128. in_8(&fpga_reg->dclk[0]),
  129. in_8(&fpga_reg->dclk[1]),
  130. in_8(&fpga_reg->dclk[2]));
  131. }