cds_via.c 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2006 Freescale Semiconductor.
  4. */
  5. #include <common.h>
  6. #include <pci.h>
  7. /* Config the VIA chip */
  8. void mpc85xx_config_via(struct pci_controller *hose,
  9. pci_dev_t dev, struct pci_config_table *tab)
  10. {
  11. pci_dev_t bridge;
  12. unsigned int cmdstat;
  13. /* Enable USB and IDE functions */
  14. pci_hose_write_config_byte(hose, dev, 0x48, 0x08);
  15. pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
  16. cmdstat |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY| PCI_COMMAND_MASTER;
  17. pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
  18. pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
  19. pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
  20. /*
  21. * Force the backplane P2P bridge to have a window
  22. * open from 0x00000000-0x00001fff in PCI I/O space.
  23. * This allows legacy I/O (i8259, etc) on the VIA
  24. * southbridge to be accessed.
  25. */
  26. bridge = PCI_BDF(0,BRIDGE_ID,0);
  27. pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0);
  28. pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0);
  29. pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10);
  30. pci_hose_write_config_word(hose, bridge, PCI_IO_LIMIT_UPPER16, 0);
  31. }
  32. /* Function 1, IDE */
  33. void mpc85xx_config_via_usbide(struct pci_controller *hose,
  34. pci_dev_t dev, struct pci_config_table *tab)
  35. {
  36. pciauto_config_device(hose, dev);
  37. /*
  38. * Since the P2P window was forced to cover the fixed
  39. * legacy I/O addresses, it is necessary to manually
  40. * place the base addresses for the IDE and USB functions
  41. * within this window.
  42. */
  43. pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1ff8);
  44. pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1ff4);
  45. pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1fe8);
  46. pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_3, 0x1fe4);
  47. pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fd0);
  48. }
  49. /* Function 2, USB ports 0-1 */
  50. void mpc85xx_config_via_usb(struct pci_controller *hose,
  51. pci_dev_t dev, struct pci_config_table *tab)
  52. {
  53. pciauto_config_device(hose, dev);
  54. pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fa0);
  55. }
  56. /* Function 3, USB ports 2-3 */
  57. void mpc85xx_config_via_usb2(struct pci_controller *hose,
  58. pci_dev_t dev, struct pci_config_table *tab)
  59. {
  60. pciauto_config_device(hose, dev);
  61. pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1f80);
  62. }
  63. /* Function 5, Power Management */
  64. void mpc85xx_config_via_power(struct pci_controller *hose,
  65. pci_dev_t dev, struct pci_config_table *tab)
  66. {
  67. pciauto_config_device(hose, dev);
  68. pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1e00);
  69. pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1dfc);
  70. pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1df8);
  71. }
  72. /* Function 6, AC97 Interface */
  73. void mpc85xx_config_via_ac97(struct pci_controller *hose,
  74. pci_dev_t dev, struct pci_config_table *tab)
  75. {
  76. pciauto_config_device(hose, dev);
  77. pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1c00);
  78. }