imx6q.c 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Amarula Solutions B.V.
  4. * Copyright (C) 2016 Engicam S.r.l.
  5. * Author: Jagan Teki <jagan@amarulasolutions.com>
  6. */
  7. #include <common.h>
  8. #include <asm/io.h>
  9. #include <asm/gpio.h>
  10. #include <linux/sizes.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/crm_regs.h>
  13. #include <asm/arch/iomux.h>
  14. #include <asm/arch/mx6-pins.h>
  15. #include <asm/arch/sys_proto.h>
  16. #include <asm/mach-imx/iomux-v3.h>
  17. #include <asm/mach-imx/video.h>
  18. #include "../common/board.h"
  19. #ifdef CONFIG_NAND_MXS
  20. #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
  21. #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
  22. PAD_CTL_SRE_FAST)
  23. #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
  24. static iomux_v3_cfg_t gpmi_pads[] = {
  25. IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  26. IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  27. IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  28. IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0)),
  29. IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  30. IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  31. IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  32. IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  33. IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  34. IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  35. IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  36. IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  37. IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  38. IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  39. IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
  40. };
  41. void setup_gpmi_nand(void)
  42. {
  43. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  44. /* config gpmi nand iomux */
  45. SETUP_IOMUX_PADS(gpmi_pads);
  46. /* gate ENFC_CLK_ROOT clock first,before clk source switch */
  47. clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
  48. /* config gpmi and bch clock to 100 MHz */
  49. clrsetbits_le32(&mxc_ccm->cs2cdr,
  50. MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
  51. MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
  52. MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
  53. MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
  54. MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
  55. MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
  56. /* enable ENFC_CLK_ROOT clock */
  57. setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
  58. /* enable gpmi and bch clock gating */
  59. setbits_le32(&mxc_ccm->CCGR4,
  60. MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  61. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  62. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  63. MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  64. MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
  65. /* enable apbh clock gating */
  66. setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  67. }
  68. #endif
  69. #if defined(CONFIG_VIDEO_IPUV3)
  70. static iomux_v3_cfg_t const rgb_pads[] = {
  71. IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
  72. IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15),
  73. IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02),
  74. IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03),
  75. IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
  76. IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
  77. IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
  78. IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
  79. IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
  80. IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
  81. IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
  82. IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
  83. IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
  84. IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
  85. IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
  86. IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
  87. IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
  88. IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
  89. IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
  90. IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
  91. IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
  92. IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
  93. };
  94. static void enable_rgb(struct display_info_t const *dev)
  95. {
  96. SETUP_IOMUX_PADS(rgb_pads);
  97. }
  98. struct display_info_t const displays[] = {
  99. {
  100. .bus = -1,
  101. .addr = 0,
  102. .pixfmt = IPU_PIX_FMT_RGB666,
  103. .detect = NULL,
  104. .enable = enable_rgb,
  105. .mode = {
  106. .name = "Amp-WD",
  107. .refresh = 60,
  108. .xres = 800,
  109. .yres = 480,
  110. .pixclock = 30000,
  111. .left_margin = 30,
  112. .right_margin = 30,
  113. .upper_margin = 5,
  114. .lower_margin = 5,
  115. .hsync_len = 64,
  116. .vsync_len = 20,
  117. .sync = FB_SYNC_EXT,
  118. .vmode = FB_VMODE_NONINTERLACED
  119. }
  120. },
  121. };
  122. size_t display_count = ARRAY_SIZE(displays);
  123. void setup_display(void)
  124. {
  125. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  126. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  127. int reg;
  128. enable_ipu_clock();
  129. /* Turn on LDB0,IPU,IPU DI0 clocks */
  130. reg = __raw_readl(&mxc_ccm->CCGR3);
  131. reg |= (MXC_CCM_CCGR3_LDB_DI0_MASK | 0xffff);
  132. writel(reg, &mxc_ccm->CCGR3);
  133. /* set LDB0, LDB1 clk select to 011/011 */
  134. reg = readl(&mxc_ccm->cs2cdr);
  135. reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
  136. MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
  137. reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
  138. (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
  139. writel(reg, &mxc_ccm->cs2cdr);
  140. reg = readl(&mxc_ccm->cscmr2);
  141. reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
  142. writel(reg, &mxc_ccm->cscmr2);
  143. reg = readl(&mxc_ccm->chsccdr);
  144. reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
  145. MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  146. writel(reg, &mxc_ccm->chsccdr);
  147. reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
  148. IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
  149. IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
  150. IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
  151. IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
  152. IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
  153. IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
  154. IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED |
  155. IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
  156. writel(reg, &iomux->gpr[2]);
  157. reg = readl(&iomux->gpr[3]);
  158. reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) |
  159. (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
  160. IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
  161. writel(reg, &iomux->gpr[3]);
  162. }
  163. #endif /* CONFIG_VIDEO_IPUV3 */
  164. #ifdef CONFIG_ENV_IS_IN_MMC
  165. int board_mmc_get_env_dev(int devno)
  166. {
  167. /* i.CoreM6 RQS has USDHC3 for SD and USDHC4 for eMMC */
  168. return (devno == 0) ? 0: (devno - 1);
  169. }
  170. #endif