qemu-arm.c 3.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2017 Tuomas Tynkkynen
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <dm.h>
  8. #include <fdtdec.h>
  9. #include <init.h>
  10. #include <log.h>
  11. #include <virtio_types.h>
  12. #include <virtio.h>
  13. #ifdef CONFIG_ARM64
  14. #include <asm/armv8/mmu.h>
  15. static struct mm_region qemu_arm64_mem_map[] = {
  16. {
  17. /* Flash */
  18. .virt = 0x00000000UL,
  19. .phys = 0x00000000UL,
  20. .size = 0x08000000UL,
  21. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  22. PTE_BLOCK_INNER_SHARE
  23. }, {
  24. /* Lowmem peripherals */
  25. .virt = 0x08000000UL,
  26. .phys = 0x08000000UL,
  27. .size = 0x38000000,
  28. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  29. PTE_BLOCK_NON_SHARE |
  30. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  31. }, {
  32. /* RAM */
  33. .virt = 0x40000000UL,
  34. .phys = 0x40000000UL,
  35. .size = 255UL * SZ_1G,
  36. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  37. PTE_BLOCK_INNER_SHARE
  38. }, {
  39. /* Highmem PCI-E ECAM memory area */
  40. .virt = 0x4010000000ULL,
  41. .phys = 0x4010000000ULL,
  42. .size = 0x10000000,
  43. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  44. PTE_BLOCK_NON_SHARE |
  45. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  46. }, {
  47. /* Highmem PCI-E MMIO memory area */
  48. .virt = 0x8000000000ULL,
  49. .phys = 0x8000000000ULL,
  50. .size = 0x8000000000ULL,
  51. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  52. PTE_BLOCK_NON_SHARE |
  53. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  54. }, {
  55. /* List terminator */
  56. 0,
  57. }
  58. };
  59. struct mm_region *mem_map = qemu_arm64_mem_map;
  60. #endif
  61. int board_init(void)
  62. {
  63. /*
  64. * Make sure virtio bus is enumerated so that peripherals
  65. * on the virtio bus can be discovered by their drivers
  66. */
  67. virtio_init();
  68. return 0;
  69. }
  70. int dram_init(void)
  71. {
  72. if (fdtdec_setup_mem_size_base() != 0)
  73. return -EINVAL;
  74. return 0;
  75. }
  76. int dram_init_banksize(void)
  77. {
  78. fdtdec_setup_memory_banksize();
  79. return 0;
  80. }
  81. void *board_fdt_blob_setup(void)
  82. {
  83. /* QEMU loads a generated DTB for us at the start of RAM. */
  84. return (void *)CONFIG_SYS_SDRAM_BASE;
  85. }
  86. void enable_caches(void)
  87. {
  88. icache_enable();
  89. dcache_enable();
  90. }
  91. #if defined(CONFIG_EFI_RNG_PROTOCOL)
  92. #include <efi_loader.h>
  93. #include <efi_rng.h>
  94. #include <dm/device-internal.h>
  95. efi_status_t platform_get_rng_device(struct udevice **dev)
  96. {
  97. int ret;
  98. efi_status_t status = EFI_DEVICE_ERROR;
  99. struct udevice *bus, *devp;
  100. for (uclass_first_device(UCLASS_VIRTIO, &bus); bus;
  101. uclass_next_device(&bus)) {
  102. for (device_find_first_child(bus, &devp); devp;
  103. device_find_next_child(&devp)) {
  104. if (device_get_uclass_id(devp) == UCLASS_RNG) {
  105. *dev = devp;
  106. status = EFI_SUCCESS;
  107. break;
  108. }
  109. }
  110. }
  111. if (status != EFI_SUCCESS) {
  112. debug("No rng device found\n");
  113. return EFI_DEVICE_ERROR;
  114. }
  115. if (*dev) {
  116. ret = device_probe(*dev);
  117. if (ret)
  118. return EFI_DEVICE_ERROR;
  119. } else {
  120. debug("Couldn't get child device\n");
  121. return EFI_DEVICE_ERROR;
  122. }
  123. return EFI_SUCCESS;
  124. }
  125. #endif /* CONFIG_EFI_RNG_PROTOCOL */
  126. #ifdef CONFIG_ARM64
  127. #define __W "w"
  128. #else
  129. #define __W
  130. #endif
  131. u8 flash_read8(void *addr)
  132. {
  133. u8 ret;
  134. asm("ldrb %" __W "0, %1" : "=r"(ret) : "m"(*(u8 *)addr));
  135. return ret;
  136. }
  137. u16 flash_read16(void *addr)
  138. {
  139. u16 ret;
  140. asm("ldrh %" __W "0, %1" : "=r"(ret) : "m"(*(u16 *)addr));
  141. return ret;
  142. }
  143. u32 flash_read32(void *addr)
  144. {
  145. u32 ret;
  146. asm("ldr %" __W "0, %1" : "=r"(ret) : "m"(*(u32 *)addr));
  147. return ret;
  148. }
  149. void flash_write8(u8 value, void *addr)
  150. {
  151. asm("strb %" __W "1, %0" : "=m"(*(u8 *)addr) : "r"(value));
  152. }
  153. void flash_write16(u16 value, void *addr)
  154. {
  155. asm("strh %" __W "1, %0" : "=m"(*(u16 *)addr) : "r"(value));
  156. }
  157. void flash_write32(u32 value, void *addr)
  158. {
  159. asm("str %" __W "1, %0" : "=m"(*(u32 *)addr) : "r"(value));
  160. }