mx6boards.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Eukréa Electromatique
  4. * Author: Eric Bénard <eric@eukrea.com>
  5. * Fabio Estevam <fabio.estevam@freescale.com>
  6. * Jon Nettleton <jon.nettleton@gmail.com>
  7. *
  8. * based on sabresd.c which is :
  9. * Copyright (C) 2012 Freescale Semiconductor, Inc.
  10. * and on hummingboard.c which is :
  11. * Copyright (C) 2013 SolidRun ltd.
  12. * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>.
  13. */
  14. #include <common.h>
  15. #include <init.h>
  16. #include <net.h>
  17. #include <asm/arch/clock.h>
  18. #include <asm/arch/sys_proto.h>
  19. #include <asm/arch/imx-regs.h>
  20. #include <asm/arch/iomux.h>
  21. #include <asm/arch/mx6-pins.h>
  22. #include <linux/delay.h>
  23. #include <linux/errno.h>
  24. #include <asm/gpio.h>
  25. #include <asm/mach-imx/iomux-v3.h>
  26. #include <asm/mach-imx/boot_mode.h>
  27. #include <asm/mach-imx/mxc_i2c.h>
  28. #include <asm/mach-imx/spi.h>
  29. #include <asm/mach-imx/video.h>
  30. #include <i2c.h>
  31. #include <input.h>
  32. #include <mmc.h>
  33. #include <fsl_esdhc_imx.h>
  34. #include <miiphy.h>
  35. #include <netdev.h>
  36. #include <asm/arch/mxc_hdmi.h>
  37. #include <asm/arch/crm_regs.h>
  38. #include <linux/fb.h>
  39. #include <ipu_pixfmt.h>
  40. #include <asm/io.h>
  41. DECLARE_GLOBAL_DATA_PTR;
  42. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  43. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  44. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  45. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  46. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  47. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  48. #define USDHC_PAD_CLK_CTRL (PAD_CTL_SPEED_LOW | \
  49. PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \
  50. PAD_CTL_HYS)
  51. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  52. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  53. #define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \
  54. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  55. #define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
  56. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  57. #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  58. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  59. PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  60. #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  61. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  62. static int board_type = -1;
  63. #define BOARD_IS_MARSBOARD 0
  64. #define BOARD_IS_RIOTBOARD 1
  65. int dram_init(void)
  66. {
  67. gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  68. return 0;
  69. }
  70. static iomux_v3_cfg_t const uart2_pads[] = {
  71. MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  72. MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  73. };
  74. static void setup_iomux_uart(void)
  75. {
  76. imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
  77. }
  78. iomux_v3_cfg_t const enet_pads[] = {
  79. MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  80. MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  81. /* GPIO16 -> AR8035 25MHz */
  82. MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
  83. MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL),
  84. MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  85. MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  86. MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  87. MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  88. MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  89. /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
  90. MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
  91. MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  92. MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
  93. MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
  94. MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  95. MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  96. MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
  97. /* AR8035 PHY Reset */
  98. MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
  99. /* AR8035 PHY Interrupt */
  100. MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  101. };
  102. static void setup_iomux_enet(void)
  103. {
  104. imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
  105. /* Reset AR8035 PHY */
  106. gpio_direction_output(IMX_GPIO_NR(3, 31) , 0);
  107. mdelay(2);
  108. gpio_set_value(IMX_GPIO_NR(3, 31), 1);
  109. }
  110. int mx6_rgmii_rework(struct phy_device *phydev)
  111. {
  112. /* from linux/arch/arm/mach-imx/mach-imx6q.c :
  113. * Ar803x phy SmartEEE feature cause link status generates glitch,
  114. * which cause ethernet link down/up issue, so disable SmartEEE
  115. */
  116. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
  117. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
  118. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
  119. return 0;
  120. }
  121. int board_phy_config(struct phy_device *phydev)
  122. {
  123. mx6_rgmii_rework(phydev);
  124. if (phydev->drv->config)
  125. phydev->drv->config(phydev);
  126. return 0;
  127. }
  128. iomux_v3_cfg_t const usdhc2_pads[] = {
  129. MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
  130. MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  131. MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  132. MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  133. MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  134. MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  135. MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
  136. MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  137. };
  138. iomux_v3_cfg_t const usdhc3_pads[] = {
  139. MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
  140. MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  141. MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  142. MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  143. MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  144. MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  145. };
  146. iomux_v3_cfg_t const riotboard_usdhc3_pads[] = {
  147. MX6_PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
  148. MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  149. };
  150. iomux_v3_cfg_t const usdhc4_pads[] = {
  151. MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
  152. MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  153. MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  154. MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  155. MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  156. MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  157. /* eMMC RST */
  158. MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
  159. };
  160. #ifdef CONFIG_FSL_ESDHC_IMX
  161. struct fsl_esdhc_cfg usdhc_cfg[3] = {
  162. {USDHC2_BASE_ADDR},
  163. {USDHC3_BASE_ADDR},
  164. {USDHC4_BASE_ADDR},
  165. };
  166. #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
  167. #define USDHC3_CD_GPIO IMX_GPIO_NR(7, 0)
  168. int board_mmc_getcd(struct mmc *mmc)
  169. {
  170. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  171. int ret = 0;
  172. switch (cfg->esdhc_base) {
  173. case USDHC2_BASE_ADDR:
  174. ret = !gpio_get_value(USDHC2_CD_GPIO);
  175. break;
  176. case USDHC3_BASE_ADDR:
  177. if (board_type == BOARD_IS_RIOTBOARD)
  178. ret = !gpio_get_value(USDHC3_CD_GPIO);
  179. else if (board_type == BOARD_IS_MARSBOARD)
  180. ret = 1; /* eMMC/uSDHC3 is always present */
  181. break;
  182. case USDHC4_BASE_ADDR:
  183. ret = 1; /* eMMC/uSDHC4 is always present */
  184. break;
  185. }
  186. return ret;
  187. }
  188. int board_mmc_init(struct bd_info *bis)
  189. {
  190. int ret;
  191. int i;
  192. /*
  193. * According to the board_mmc_init() the following map is done:
  194. * (U-Boot device node) (Physical Port)
  195. * ** RiOTboard :
  196. * mmc0 SDCard slot (bottom)
  197. * mmc1 uSDCard slot (top)
  198. * mmc2 eMMC
  199. * ** MarSBoard :
  200. * mmc0 uSDCard slot (bottom)
  201. * mmc1 eMMC
  202. */
  203. for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  204. switch (i) {
  205. case 0:
  206. imx_iomux_v3_setup_multiple_pads(
  207. usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
  208. gpio_direction_input(USDHC2_CD_GPIO);
  209. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  210. usdhc_cfg[0].max_bus_width = 4;
  211. break;
  212. case 1:
  213. imx_iomux_v3_setup_multiple_pads(
  214. usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  215. if (board_type == BOARD_IS_RIOTBOARD) {
  216. imx_iomux_v3_setup_multiple_pads(
  217. riotboard_usdhc3_pads,
  218. ARRAY_SIZE(riotboard_usdhc3_pads));
  219. gpio_direction_input(USDHC3_CD_GPIO);
  220. } else {
  221. gpio_direction_output(IMX_GPIO_NR(7, 8) , 0);
  222. udelay(250);
  223. gpio_set_value(IMX_GPIO_NR(7, 8), 1);
  224. }
  225. usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  226. usdhc_cfg[1].max_bus_width = 4;
  227. break;
  228. case 2:
  229. imx_iomux_v3_setup_multiple_pads(
  230. usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
  231. usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
  232. usdhc_cfg[2].max_bus_width = 4;
  233. gpio_direction_output(IMX_GPIO_NR(6, 8) , 0);
  234. udelay(250);
  235. gpio_set_value(IMX_GPIO_NR(6, 8), 1);
  236. break;
  237. default:
  238. printf("Warning: you configured more USDHC controllers"
  239. "(%d) then supported by the board (%d)\n",
  240. i + 1, CONFIG_SYS_FSL_USDHC_NUM);
  241. return -EINVAL;
  242. }
  243. ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  244. if (ret)
  245. return ret;
  246. }
  247. return 0;
  248. }
  249. #endif
  250. #ifdef CONFIG_MXC_SPI
  251. iomux_v3_cfg_t const ecspi1_pads[] = {
  252. MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
  253. MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
  254. MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
  255. MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
  256. };
  257. int board_spi_cs_gpio(unsigned bus, unsigned cs)
  258. {
  259. return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
  260. }
  261. static void setup_spi(void)
  262. {
  263. imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
  264. }
  265. #endif
  266. struct i2c_pads_info i2c_pad_info1 = {
  267. .scl = {
  268. .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL
  269. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  270. .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27
  271. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  272. .gp = IMX_GPIO_NR(5, 27)
  273. },
  274. .sda = {
  275. .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA
  276. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  277. .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26
  278. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  279. .gp = IMX_GPIO_NR(5, 26)
  280. }
  281. };
  282. struct i2c_pads_info i2c_pad_info2 = {
  283. .scl = {
  284. .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL
  285. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  286. .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12
  287. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  288. .gp = IMX_GPIO_NR(4, 12)
  289. },
  290. .sda = {
  291. .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA
  292. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  293. .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13
  294. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  295. .gp = IMX_GPIO_NR(4, 13)
  296. }
  297. };
  298. struct i2c_pads_info i2c_pad_info3 = {
  299. .scl = {
  300. .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL
  301. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  302. .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05
  303. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  304. .gp = IMX_GPIO_NR(1, 5)
  305. },
  306. .sda = {
  307. .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA
  308. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  309. .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06
  310. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  311. .gp = IMX_GPIO_NR(1, 6)
  312. }
  313. };
  314. iomux_v3_cfg_t const tft_pads_riot[] = {
  315. /* LCD_PWR_EN */
  316. MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
  317. /* TOUCH_INT */
  318. MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
  319. /* LED_PWR_EN */
  320. MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
  321. /* BL LEVEL */
  322. MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
  323. };
  324. iomux_v3_cfg_t const tft_pads_mars[] = {
  325. /* LCD_PWR_EN */
  326. MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
  327. /* TOUCH_INT */
  328. MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
  329. /* LED_PWR_EN */
  330. MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
  331. /* BL LEVEL (PWM4) */
  332. MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
  333. };
  334. #if defined(CONFIG_VIDEO_IPUV3)
  335. static void enable_lvds(struct display_info_t const *dev)
  336. {
  337. struct iomuxc *iomux = (struct iomuxc *)
  338. IOMUXC_BASE_ADDR;
  339. setbits_le32(&iomux->gpr[2],
  340. IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT);
  341. /* set backlight level to ON */
  342. if (board_type == BOARD_IS_RIOTBOARD)
  343. gpio_direction_output(IMX_GPIO_NR(1, 18) , 1);
  344. else if (board_type == BOARD_IS_MARSBOARD)
  345. gpio_direction_output(IMX_GPIO_NR(2, 10) , 1);
  346. }
  347. static void disable_lvds(struct display_info_t const *dev)
  348. {
  349. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  350. /* set backlight level to OFF */
  351. if (board_type == BOARD_IS_RIOTBOARD)
  352. gpio_direction_output(IMX_GPIO_NR(1, 18) , 0);
  353. else if (board_type == BOARD_IS_MARSBOARD)
  354. gpio_direction_output(IMX_GPIO_NR(2, 10) , 0);
  355. clrbits_le32(&iomux->gpr[2],
  356. IOMUXC_GPR2_LVDS_CH0_MODE_MASK);
  357. }
  358. static void do_enable_hdmi(struct display_info_t const *dev)
  359. {
  360. disable_lvds(dev);
  361. imx_enable_hdmi_phy();
  362. }
  363. static int detect_i2c(struct display_info_t const *dev)
  364. {
  365. return (0 == i2c_set_bus_num(dev->bus)) &&
  366. (0 == i2c_probe(dev->addr));
  367. }
  368. struct display_info_t const displays[] = {{
  369. .bus = -1,
  370. .addr = 0,
  371. .pixfmt = IPU_PIX_FMT_RGB24,
  372. .detect = detect_hdmi,
  373. .enable = do_enable_hdmi,
  374. .mode = {
  375. .name = "HDMI",
  376. .refresh = 60,
  377. .xres = 1024,
  378. .yres = 768,
  379. .pixclock = 15385,
  380. .left_margin = 220,
  381. .right_margin = 40,
  382. .upper_margin = 21,
  383. .lower_margin = 7,
  384. .hsync_len = 60,
  385. .vsync_len = 10,
  386. .sync = FB_SYNC_EXT,
  387. .vmode = FB_VMODE_NONINTERLACED
  388. } }, {
  389. .bus = 2,
  390. .addr = 0x1,
  391. .pixfmt = IPU_PIX_FMT_LVDS666,
  392. .detect = detect_i2c,
  393. .enable = enable_lvds,
  394. .mode = {
  395. .name = "LCD8000-97C",
  396. .refresh = 60,
  397. .xres = 1024,
  398. .yres = 768,
  399. .pixclock = 15385,
  400. .left_margin = 100,
  401. .right_margin = 200,
  402. .upper_margin = 10,
  403. .lower_margin = 20,
  404. .hsync_len = 20,
  405. .vsync_len = 8,
  406. .sync = FB_SYNC_EXT,
  407. .vmode = FB_VMODE_NONINTERLACED
  408. } } };
  409. size_t display_count = ARRAY_SIZE(displays);
  410. static void setup_display(void)
  411. {
  412. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  413. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  414. int reg;
  415. enable_ipu_clock();
  416. imx_setup_hdmi();
  417. /* Turn on LDB0, IPU,IPU DI0 clocks */
  418. setbits_le32(&mxc_ccm->CCGR3,
  419. MXC_CCM_CCGR3_LDB_DI0_MASK);
  420. /* set LDB0 clk select to 011/011 */
  421. clrsetbits_le32(&mxc_ccm->cs2cdr,
  422. MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK,
  423. (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
  424. setbits_le32(&mxc_ccm->cscmr2,
  425. MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
  426. setbits_le32(&mxc_ccm->chsccdr,
  427. (CHSCCDR_CLK_SEL_LDB_DI0
  428. << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
  429. reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
  430. | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
  431. | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
  432. | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
  433. | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
  434. | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
  435. | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
  436. | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
  437. writel(reg, &iomux->gpr[2]);
  438. clrsetbits_le32(&iomux->gpr[3],
  439. IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
  440. IOMUXC_GPR3_HDMI_MUX_CTL_MASK,
  441. IOMUXC_GPR3_MUX_SRC_IPU1_DI0
  442. << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
  443. }
  444. #endif /* CONFIG_VIDEO_IPUV3 */
  445. /*
  446. * Do not overwrite the console
  447. * Use always serial for U-Boot console
  448. */
  449. int overwrite_console(void)
  450. {
  451. return 1;
  452. }
  453. int board_eth_init(struct bd_info *bis)
  454. {
  455. setup_iomux_enet();
  456. return cpu_eth_init(bis);
  457. }
  458. int board_early_init_f(void)
  459. {
  460. u32 cputype = cpu_type(get_cpu_rev());
  461. switch (cputype) {
  462. case MXC_CPU_MX6SOLO:
  463. board_type = BOARD_IS_RIOTBOARD;
  464. break;
  465. case MXC_CPU_MX6D:
  466. board_type = BOARD_IS_MARSBOARD;
  467. break;
  468. }
  469. setup_iomux_uart();
  470. if (board_type == BOARD_IS_RIOTBOARD)
  471. imx_iomux_v3_setup_multiple_pads(
  472. tft_pads_riot, ARRAY_SIZE(tft_pads_riot));
  473. else if (board_type == BOARD_IS_MARSBOARD)
  474. imx_iomux_v3_setup_multiple_pads(
  475. tft_pads_mars, ARRAY_SIZE(tft_pads_mars));
  476. #if defined(CONFIG_VIDEO_IPUV3)
  477. /* power ON LCD */
  478. gpio_direction_output(IMX_GPIO_NR(1, 29) , 1);
  479. /* touch interrupt is an input */
  480. gpio_direction_input(IMX_GPIO_NR(6, 14));
  481. /* power ON backlight */
  482. gpio_direction_output(IMX_GPIO_NR(6, 15) , 1);
  483. /* set backlight level to off */
  484. if (board_type == BOARD_IS_RIOTBOARD)
  485. gpio_direction_output(IMX_GPIO_NR(1, 18) , 0);
  486. else if (board_type == BOARD_IS_MARSBOARD)
  487. gpio_direction_output(IMX_GPIO_NR(2, 10) , 0);
  488. setup_display();
  489. #endif
  490. return 0;
  491. }
  492. int board_init(void)
  493. {
  494. /* address of boot parameters */
  495. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  496. /* i2c1 : PMIC, Audio codec on RiOT, Expansion connector on MarS */
  497. setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  498. /* i2c2 : HDMI EDID */
  499. setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
  500. /* i2c3 : LVDS, Expansion connector */
  501. setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
  502. #ifdef CONFIG_MXC_SPI
  503. setup_spi();
  504. #endif
  505. return 0;
  506. }
  507. #ifdef CONFIG_CMD_BMODE
  508. static const struct boot_mode riotboard_boot_modes[] = {
  509. {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  510. {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  511. {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
  512. {NULL, 0},
  513. };
  514. static const struct boot_mode marsboard_boot_modes[] = {
  515. {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  516. {"emmc", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  517. {NULL, 0},
  518. };
  519. #endif
  520. int board_late_init(void)
  521. {
  522. #ifdef CONFIG_CMD_BMODE
  523. if (board_type == BOARD_IS_RIOTBOARD)
  524. add_board_boot_modes(riotboard_boot_modes);
  525. else if (board_type == BOARD_IS_RIOTBOARD)
  526. add_board_boot_modes(marsboard_boot_modes);
  527. #endif
  528. return 0;
  529. }
  530. int checkboard(void)
  531. {
  532. puts("Board: ");
  533. if (board_type == BOARD_IS_MARSBOARD)
  534. puts("MarSBoard\n");
  535. else if (board_type == BOARD_IS_RIOTBOARD)
  536. puts("RIoTboard\n");
  537. else
  538. printf("unknown - cputype : %02x\n", cpu_type(get_cpu_rev()));
  539. return 0;
  540. }
  541. #ifdef CONFIG_SPL_BUILD
  542. #include <spl.h>
  543. void board_init_f(ulong dummy)
  544. {
  545. u32 cputype = cpu_type(get_cpu_rev());
  546. switch (cputype) {
  547. case MXC_CPU_MX6SOLO:
  548. board_type = BOARD_IS_RIOTBOARD;
  549. break;
  550. case MXC_CPU_MX6D:
  551. board_type = BOARD_IS_MARSBOARD;
  552. break;
  553. }
  554. arch_cpu_init();
  555. /* setup GP timer */
  556. timer_init();
  557. #ifdef CONFIG_SPL_SERIAL_SUPPORT
  558. setup_iomux_uart();
  559. preloader_console_init();
  560. #endif
  561. }
  562. void board_boot_order(u32 *spl_boot_list)
  563. {
  564. spl_boot_list[0] = BOOT_DEVICE_MMC1;
  565. }
  566. /*
  567. * In order to jump to standard u-boot shell, you have to connect pin 5 of J13
  568. * to pin 3 (ground).
  569. */
  570. int spl_start_uboot(void)
  571. {
  572. int gpio_key = IMX_GPIO_NR(4, 16);
  573. gpio_direction_input(gpio_key);
  574. if (gpio_get_value(gpio_key) == 0)
  575. return 1;
  576. else
  577. return 0;
  578. }
  579. #endif