spl.c 8.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * SPL specific code for Compulab CM-FX6 board
  4. *
  5. * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
  6. *
  7. * Author: Nikita Kiryanov <nikita@compulab.co.il>
  8. */
  9. #include <common.h>
  10. #include <clock_legacy.h>
  11. #include <hang.h>
  12. #include <init.h>
  13. #include <spl.h>
  14. #include <asm/io.h>
  15. #include <asm/gpio.h>
  16. #include <asm/arch/mx6-ddr.h>
  17. #include <asm/arch/clock.h>
  18. #include <asm/arch/sys_proto.h>
  19. #include <asm/arch/crm_regs.h>
  20. #include <asm/mach-imx/iomux-v3.h>
  21. #include <fsl_esdhc_imx.h>
  22. #include <linux/delay.h>
  23. #include "common.h"
  24. enum ddr_config {
  25. DDR_16BIT_256MB,
  26. DDR_32BIT_512MB,
  27. DDR_32BIT_1GB,
  28. DDR_64BIT_1GB,
  29. DDR_64BIT_2GB,
  30. DDR_64BIT_4GB,
  31. DDR_UNKNOWN,
  32. };
  33. /*
  34. * Below DRAM_RESET[DDR_SEL] = 0 which is incorrect according to
  35. * Freescale QRM, but this is exactly the value used by the automatic
  36. * calibration script and it works also in all our tests, so we leave
  37. * it as is at this point.
  38. */
  39. #define CM_FX6_DDR_IOMUX_CFG \
  40. .dram_sdqs0 = 0x00000038, \
  41. .dram_sdqs1 = 0x00000038, \
  42. .dram_sdqs2 = 0x00000038, \
  43. .dram_sdqs3 = 0x00000038, \
  44. .dram_sdqs4 = 0x00000038, \
  45. .dram_sdqs5 = 0x00000038, \
  46. .dram_sdqs6 = 0x00000038, \
  47. .dram_sdqs7 = 0x00000038, \
  48. .dram_dqm0 = 0x00000038, \
  49. .dram_dqm1 = 0x00000038, \
  50. .dram_dqm2 = 0x00000038, \
  51. .dram_dqm3 = 0x00000038, \
  52. .dram_dqm4 = 0x00000038, \
  53. .dram_dqm5 = 0x00000038, \
  54. .dram_dqm6 = 0x00000038, \
  55. .dram_dqm7 = 0x00000038, \
  56. .dram_cas = 0x00000038, \
  57. .dram_ras = 0x00000038, \
  58. .dram_sdclk_0 = 0x00000038, \
  59. .dram_sdclk_1 = 0x00000038, \
  60. .dram_sdcke0 = 0x00003000, \
  61. .dram_sdcke1 = 0x00003000, \
  62. .dram_reset = 0x00000038, \
  63. .dram_sdba2 = 0x00000000, \
  64. .dram_sdodt0 = 0x00000038, \
  65. .dram_sdodt1 = 0x00000038,
  66. #define CM_FX6_GPR_IOMUX_CFG \
  67. .grp_b0ds = 0x00000038, \
  68. .grp_b1ds = 0x00000038, \
  69. .grp_b2ds = 0x00000038, \
  70. .grp_b3ds = 0x00000038, \
  71. .grp_b4ds = 0x00000038, \
  72. .grp_b5ds = 0x00000038, \
  73. .grp_b6ds = 0x00000038, \
  74. .grp_b7ds = 0x00000038, \
  75. .grp_addds = 0x00000038, \
  76. .grp_ddrmode_ctl = 0x00020000, \
  77. .grp_ddrpke = 0x00000000, \
  78. .grp_ddrmode = 0x00020000, \
  79. .grp_ctlds = 0x00000038, \
  80. .grp_ddr_type = 0x000C0000,
  81. static struct mx6sdl_iomux_ddr_regs ddr_iomux_s = { CM_FX6_DDR_IOMUX_CFG };
  82. static struct mx6sdl_iomux_grp_regs grp_iomux_s = { CM_FX6_GPR_IOMUX_CFG };
  83. static struct mx6dq_iomux_ddr_regs ddr_iomux_q = { CM_FX6_DDR_IOMUX_CFG };
  84. static struct mx6dq_iomux_grp_regs grp_iomux_q = { CM_FX6_GPR_IOMUX_CFG };
  85. static struct mx6_mmdc_calibration cm_fx6_calib_s = {
  86. .p0_mpwldectrl0 = 0x005B0061,
  87. .p0_mpwldectrl1 = 0x004F0055,
  88. .p0_mpdgctrl0 = 0x0314030C,
  89. .p0_mpdgctrl1 = 0x025C0268,
  90. .p0_mprddlctl = 0x42464646,
  91. .p0_mpwrdlctl = 0x36322C34,
  92. };
  93. static struct mx6_ddr_sysinfo cm_fx6_sysinfo_s = {
  94. .cs1_mirror = 1,
  95. .cs_density = 16,
  96. .bi_on = 1,
  97. .rtt_nom = 1,
  98. .rtt_wr = 0,
  99. .ralat = 5,
  100. .walat = 1,
  101. .mif3_mode = 3,
  102. .rst_to_cke = 0x23,
  103. .sde_to_rst = 0x10,
  104. };
  105. static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_s = {
  106. .mem_speed = 800,
  107. .density = 4,
  108. .rowaddr = 14,
  109. .coladdr = 10,
  110. .pagesz = 2,
  111. .trcd = 1800,
  112. .trcmin = 5200,
  113. .trasmin = 3600,
  114. .SRT = 0,
  115. };
  116. static void spl_mx6s_dram_init(enum ddr_config dram_config, bool reset)
  117. {
  118. if (reset)
  119. ((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2;
  120. switch (dram_config) {
  121. case DDR_16BIT_256MB:
  122. cm_fx6_sysinfo_s.dsize = 0;
  123. cm_fx6_sysinfo_s.ncs = 1;
  124. break;
  125. case DDR_32BIT_512MB:
  126. cm_fx6_sysinfo_s.dsize = 1;
  127. cm_fx6_sysinfo_s.ncs = 1;
  128. break;
  129. case DDR_32BIT_1GB:
  130. cm_fx6_sysinfo_s.dsize = 1;
  131. cm_fx6_sysinfo_s.ncs = 2;
  132. break;
  133. default:
  134. puts("Tried to setup invalid DDR configuration\n");
  135. hang();
  136. }
  137. mx6_dram_cfg(&cm_fx6_sysinfo_s, &cm_fx6_calib_s, &cm_fx6_ddr3_cfg_s);
  138. udelay(100);
  139. }
  140. static struct mx6_mmdc_calibration cm_fx6_calib_q = {
  141. .p0_mpwldectrl0 = 0x00630068,
  142. .p0_mpwldectrl1 = 0x0068005D,
  143. .p0_mpdgctrl0 = 0x04140428,
  144. .p0_mpdgctrl1 = 0x037C037C,
  145. .p0_mprddlctl = 0x3C30303A,
  146. .p0_mpwrdlctl = 0x3A344038,
  147. .p1_mpwldectrl0 = 0x0035004C,
  148. .p1_mpwldectrl1 = 0x00170026,
  149. .p1_mpdgctrl0 = 0x0374037C,
  150. .p1_mpdgctrl1 = 0x0350032C,
  151. .p1_mprddlctl = 0x30322A3C,
  152. .p1_mpwrdlctl = 0x48304A3E,
  153. };
  154. static struct mx6_ddr_sysinfo cm_fx6_sysinfo_q = {
  155. .cs_density = 16,
  156. .cs1_mirror = 1,
  157. .bi_on = 1,
  158. .rtt_nom = 1,
  159. .rtt_wr = 0,
  160. .ralat = 5,
  161. .walat = 1,
  162. .mif3_mode = 3,
  163. .rst_to_cke = 0x23,
  164. .sde_to_rst = 0x10,
  165. .refsel = 1, /* Refresh cycles at 32KHz */
  166. .refr = 7, /* 8 refresh commands per refresh cycle */
  167. };
  168. static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_q = {
  169. .mem_speed = 1066,
  170. .density = 4,
  171. .rowaddr = 14,
  172. .coladdr = 10,
  173. .pagesz = 2,
  174. .trcd = 1324,
  175. .trcmin = 59500,
  176. .trasmin = 9750,
  177. .SRT = 0,
  178. };
  179. static void spl_mx6q_dram_init(enum ddr_config dram_config, bool reset)
  180. {
  181. if (reset)
  182. ((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2;
  183. cm_fx6_ddr3_cfg_q.rowaddr = 14;
  184. switch (dram_config) {
  185. case DDR_16BIT_256MB:
  186. cm_fx6_sysinfo_q.dsize = 0;
  187. cm_fx6_sysinfo_q.ncs = 1;
  188. break;
  189. case DDR_32BIT_512MB:
  190. cm_fx6_sysinfo_q.dsize = 1;
  191. cm_fx6_sysinfo_q.ncs = 1;
  192. break;
  193. case DDR_64BIT_1GB:
  194. cm_fx6_sysinfo_q.dsize = 2;
  195. cm_fx6_sysinfo_q.ncs = 1;
  196. break;
  197. case DDR_64BIT_2GB:
  198. cm_fx6_sysinfo_q.dsize = 2;
  199. cm_fx6_sysinfo_q.ncs = 2;
  200. break;
  201. case DDR_64BIT_4GB:
  202. cm_fx6_sysinfo_q.dsize = 2;
  203. cm_fx6_sysinfo_q.ncs = 2;
  204. cm_fx6_ddr3_cfg_q.rowaddr = 15;
  205. break;
  206. default:
  207. puts("Tried to setup invalid DDR configuration\n");
  208. hang();
  209. }
  210. mx6_dram_cfg(&cm_fx6_sysinfo_q, &cm_fx6_calib_q, &cm_fx6_ddr3_cfg_q);
  211. udelay(100);
  212. }
  213. static int cm_fx6_spl_dram_init(void)
  214. {
  215. unsigned long bank1_size, bank2_size;
  216. switch (get_cpu_type()) {
  217. case MXC_CPU_MX6SOLO:
  218. mx6sdl_dram_iocfg(64, &ddr_iomux_s, &grp_iomux_s);
  219. spl_mx6s_dram_init(DDR_32BIT_1GB, false);
  220. bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
  221. bank2_size = get_ram_size((long int *)PHYS_SDRAM_2, 0x80000000);
  222. if (bank1_size == 0x20000000) {
  223. if (bank2_size == 0x20000000)
  224. return 0;
  225. spl_mx6s_dram_init(DDR_32BIT_512MB, true);
  226. return 0;
  227. }
  228. spl_mx6s_dram_init(DDR_16BIT_256MB, true);
  229. bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
  230. if (bank1_size == 0x10000000)
  231. return 0;
  232. break;
  233. case MXC_CPU_MX6D:
  234. case MXC_CPU_MX6Q:
  235. mx6dq_dram_iocfg(64, &ddr_iomux_q, &grp_iomux_q);
  236. spl_mx6q_dram_init(DDR_64BIT_4GB, false);
  237. bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
  238. if (bank1_size == 0x80000000)
  239. return 0;
  240. if (bank1_size == 0x40000000) {
  241. bank2_size = get_ram_size((long int *)PHYS_SDRAM_2,
  242. 0x80000000);
  243. if (bank2_size == 0x40000000) {
  244. /* Don't do a full reset here */
  245. spl_mx6q_dram_init(DDR_64BIT_2GB, false);
  246. } else {
  247. spl_mx6q_dram_init(DDR_64BIT_1GB, true);
  248. }
  249. return 0;
  250. }
  251. spl_mx6q_dram_init(DDR_32BIT_512MB, true);
  252. bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
  253. if (bank1_size == 0x20000000)
  254. return 0;
  255. spl_mx6q_dram_init(DDR_16BIT_256MB, true);
  256. bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
  257. if (bank1_size == 0x10000000)
  258. return 0;
  259. break;
  260. }
  261. return -1;
  262. }
  263. static iomux_v3_cfg_t const uart4_pads[] = {
  264. IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  265. IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  266. };
  267. static void cm_fx6_setup_uart(void)
  268. {
  269. SETUP_IOMUX_PADS(uart4_pads);
  270. enable_uart_clk(1);
  271. }
  272. #ifdef CONFIG_SPL_SPI_SUPPORT
  273. static void cm_fx6_setup_ecspi(void)
  274. {
  275. cm_fx6_set_ecspi_iomux();
  276. enable_spi_clk(1, 0);
  277. }
  278. #else
  279. static void cm_fx6_setup_ecspi(void) { }
  280. #endif
  281. void board_init_f(ulong dummy)
  282. {
  283. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  284. /*
  285. * We don't use DMA in SPL, but we do need it in U-Boot. U-Boot
  286. * initializes DMA very early (before all board code), so the only
  287. * opportunity we have to initialize APBHDMA clocks is in SPL.
  288. */
  289. setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  290. enable_usdhc_clk(1, 2);
  291. arch_cpu_init();
  292. timer_init();
  293. cm_fx6_setup_ecspi();
  294. cm_fx6_setup_uart();
  295. get_clocks();
  296. preloader_console_init();
  297. gpio_direction_output(CM_FX6_GREEN_LED, 1);
  298. if (cm_fx6_spl_dram_init()) {
  299. puts("!!!ERROR!!! DRAM detection failed!!!\n");
  300. hang();
  301. }
  302. }
  303. void board_boot_order(u32 *spl_boot_list)
  304. {
  305. spl_boot_list[0] = spl_boot_device();
  306. switch (spl_boot_list[0]) {
  307. case BOOT_DEVICE_SPI:
  308. spl_boot_list[1] = BOOT_DEVICE_MMC1;
  309. break;
  310. case BOOT_DEVICE_MMC1:
  311. spl_boot_list[1] = BOOT_DEVICE_SPI;
  312. break;
  313. }
  314. }
  315. #ifdef CONFIG_SPL_MMC_SUPPORT
  316. static struct fsl_esdhc_cfg usdhc_cfg = {
  317. .esdhc_base = USDHC3_BASE_ADDR,
  318. .max_bus_width = 4,
  319. };
  320. int board_mmc_init(struct bd_info *bis)
  321. {
  322. cm_fx6_set_usdhc_iomux();
  323. usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  324. return fsl_esdhc_initialize(bis, &usdhc_cfg);
  325. }
  326. #endif