ddr-setup.cfg 2.9 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2013 Boundary Devices
  4. *
  5. * Device Configuration Data (DCD)
  6. *
  7. * Each entry must have the format:
  8. * Addr-type Address Value
  9. *
  10. * where:
  11. * Addr-type register length (1,2 or 4 bytes)
  12. * Address absolute address of the register
  13. * value value to be stored in the register
  14. */
  15. /*
  16. * DDR3 settings
  17. * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock),
  18. * memory bus width: 64 bits x16/x32/x64
  19. * MX6DL ddr is limited to 800 MHz(400 MHz clock)
  20. * memory bus width: 64 bits x16/x32/x64
  21. * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
  22. * memory bus width: 32 bits x16/x32
  23. */
  24. DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
  25. DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
  26. DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
  27. DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
  28. DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
  29. DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
  30. DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
  31. DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
  32. DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
  33. DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
  34. DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
  35. DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
  36. DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
  37. DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
  38. DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
  39. DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
  40. DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
  41. /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
  42. DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
  43. DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030
  44. DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030
  45. DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030
  46. DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030
  47. DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030
  48. DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030
  49. DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030
  50. DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030
  51. DATA 4, MX6_IOM_DRAM_CAS, 0x00020030
  52. DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
  53. DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
  54. DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
  55. DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
  56. DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
  57. DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
  58. DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
  59. DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
  60. /* (differential input) */
  61. DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
  62. /* (differential input) */
  63. DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
  64. /* disable ddr pullups */
  65. DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
  66. DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
  67. /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
  68. DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
  69. /* Read data DQ Byte0-3 delay */
  70. DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
  71. DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
  72. DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
  73. DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
  74. DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
  75. DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
  76. DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
  77. DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
  78. /*
  79. * MDMISC mirroring interleaved (row/bank/col)
  80. */
  81. DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740
  82. /*
  83. * MDSCR con_req
  84. */
  85. DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000