sama5d27_som1_ek.c 4.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Microchip Corporation
  4. * Wenyou.Yang <wenyou.yang@microchip.com>
  5. */
  6. #include <common.h>
  7. #include <debug_uart.h>
  8. #include <init.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/at91_common.h>
  11. #include <asm/arch/atmel_pio4.h>
  12. #include <asm/arch/atmel_mpddrc.h>
  13. #include <asm/arch/atmel_sdhci.h>
  14. #include <asm/arch/clk.h>
  15. #include <asm/arch/gpio.h>
  16. #include <asm/arch/sama5d2.h>
  17. extern void at91_pda_detect(void);
  18. DECLARE_GLOBAL_DATA_PTR;
  19. #ifdef CONFIG_CMD_USB
  20. static void board_usb_hw_init(void)
  21. {
  22. atmel_pio4_set_pio_output(AT91_PIO_PORTA, 27, 1);
  23. }
  24. #endif
  25. #ifdef CONFIG_BOARD_LATE_INIT
  26. int board_late_init(void)
  27. {
  28. #ifdef CONFIG_DM_VIDEO
  29. at91_video_show_board_info();
  30. #endif
  31. at91_pda_detect();
  32. return 0;
  33. }
  34. #endif
  35. #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  36. static void board_uart1_hw_init(void)
  37. {
  38. atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, ATMEL_PIO_PUEN_MASK); /* URXD1 */
  39. atmel_pio4_set_a_periph(AT91_PIO_PORTD, 3, 0); /* UTXD1 */
  40. at91_periph_clk_enable(ATMEL_ID_UART1);
  41. }
  42. void board_debug_uart_init(void)
  43. {
  44. board_uart1_hw_init();
  45. }
  46. #endif
  47. #ifdef CONFIG_BOARD_EARLY_INIT_F
  48. int board_early_init_f(void)
  49. {
  50. #ifdef CONFIG_DEBUG_UART
  51. debug_uart_init();
  52. #endif
  53. return 0;
  54. }
  55. #endif
  56. int board_init(void)
  57. {
  58. /* address of boot parameters */
  59. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  60. #ifdef CONFIG_CMD_USB
  61. board_usb_hw_init();
  62. #endif
  63. return 0;
  64. }
  65. int dram_init(void)
  66. {
  67. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  68. CONFIG_SYS_SDRAM_SIZE);
  69. return 0;
  70. }
  71. #define MAC24AA_MAC_OFFSET 0xfa
  72. #ifdef CONFIG_MISC_INIT_R
  73. int misc_init_r(void)
  74. {
  75. #ifdef CONFIG_I2C_EEPROM
  76. at91_set_ethaddr(MAC24AA_MAC_OFFSET);
  77. #endif
  78. return 0;
  79. }
  80. #endif
  81. /* SPL */
  82. #ifdef CONFIG_SPL_BUILD
  83. void spl_board_init(void)
  84. {
  85. }
  86. static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
  87. {
  88. ddrc->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
  89. ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
  90. ATMEL_MPDDRC_CR_NR_ROW_13 |
  91. ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
  92. ATMEL_MPDDRC_CR_DIC_DS |
  93. ATMEL_MPDDRC_CR_ZQ_LONG |
  94. ATMEL_MPDDRC_CR_NB_8BANKS |
  95. ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
  96. ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
  97. ddrc->rtr = 0x511;
  98. ddrc->tpr0 = ((7 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) |
  99. (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) |
  100. (3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) |
  101. (9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) |
  102. (3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) |
  103. (4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) |
  104. (4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) |
  105. (2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET));
  106. ddrc->tpr1 = ((22 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) |
  107. (23 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) |
  108. (200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) |
  109. (3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET));
  110. ddrc->tpr2 = ((2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) |
  111. (8 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) |
  112. (4 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) |
  113. (4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) |
  114. (8 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET));
  115. }
  116. void mem_init(void)
  117. {
  118. struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  119. struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
  120. struct atmel_mpddrc_config ddrc_config;
  121. u32 reg;
  122. ddrc_conf(&ddrc_config);
  123. at91_periph_clk_enable(ATMEL_ID_MPDDRC);
  124. writel(AT91_PMC_DDR, &pmc->scer);
  125. reg = readl(&mpddrc->io_calibr);
  126. reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
  127. reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
  128. reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
  129. reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(101);
  130. writel(reg, &mpddrc->io_calibr);
  131. writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE,
  132. &mpddrc->rd_data_path);
  133. ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
  134. writel(0x3, &mpddrc->cal_mr4);
  135. writel(64, &mpddrc->tim_cal);
  136. }
  137. void at91_pmc_init(void)
  138. {
  139. u32 tmp;
  140. /*
  141. * while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz
  142. * so we need to slow down and configure MCKR accordingly.
  143. * This is why we have a special flavor of the switching function.
  144. */
  145. tmp = AT91_PMC_MCKR_PLLADIV_2 |
  146. AT91_PMC_MCKR_MDIV_3 |
  147. AT91_PMC_MCKR_CSS_MAIN;
  148. at91_mck_init_down(tmp);
  149. tmp = AT91_PMC_PLLAR_29 |
  150. AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
  151. AT91_PMC_PLLXR_MUL(40) |
  152. AT91_PMC_PLLXR_DIV(1);
  153. at91_plla_init(tmp);
  154. tmp = AT91_PMC_MCKR_H32MXDIV |
  155. AT91_PMC_MCKR_PLLADIV_2 |
  156. AT91_PMC_MCKR_MDIV_3 |
  157. AT91_PMC_MCKR_CSS_PLLA;
  158. at91_mck_init(tmp);
  159. }
  160. #endif