x530.c 4.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Allied Telesis Labs
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <dm.h>
  8. #include <env.h>
  9. #include <i2c.h>
  10. #include <init.h>
  11. #include <wdt.h>
  12. #include <asm/gpio.h>
  13. #include <linux/bitops.h>
  14. #include <linux/mbus.h>
  15. #include <linux/io.h>
  16. #include <asm/arch/cpu.h>
  17. #include <asm/arch/soc.h>
  18. #include "../common/gpio_hog.h"
  19. #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
  20. #include <../serdes/a38x/high_speed_env_spec.h>
  21. DECLARE_GLOBAL_DATA_PTR;
  22. #define MVEBU_DEV_BUS_BASE (MVEBU_REGISTER(0x10400))
  23. #define CONFIG_NVS_LOCATION 0xf4800000
  24. #define CONFIG_NVS_SIZE (512 << 10)
  25. static struct serdes_map board_serdes_map[] = {
  26. {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  27. {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  28. {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  29. {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  30. {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  31. {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}
  32. };
  33. int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
  34. {
  35. *serdes_map_array = board_serdes_map;
  36. *count = ARRAY_SIZE(board_serdes_map);
  37. return 0;
  38. }
  39. /*
  40. * Define the DDR layout / topology here in the board file. This will
  41. * be used by the DDR3 init code in the SPL U-Boot version to configure
  42. * the DDR3 controller.
  43. */
  44. static struct mv_ddr_topology_map board_topology_map = {
  45. DEBUG_LEVEL_ERROR,
  46. 0x1, /* active interfaces */
  47. /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
  48. { { { {0x1, 0, 0, 0},
  49. {0x1, 0, 0, 0},
  50. {0x1, 0, 0, 0},
  51. {0x1, 0, 0, 0},
  52. {0x1, 0, 0, 0} },
  53. SPEED_BIN_DDR_1866M, /* speed_bin */
  54. MV_DDR_DEV_WIDTH_16BIT, /* sdram device width */
  55. MV_DDR_DIE_CAP_4GBIT, /* die capacity */
  56. MV_DDR_FREQ_SAR, /* frequency */
  57. 0, 0, /* cas_l cas_wl */
  58. MV_DDR_TEMP_LOW, /* temperature */
  59. MV_DDR_TIM_2T} }, /* timing */
  60. BUS_MASK_32BIT_ECC, /* subphys mask */
  61. MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
  62. { {0} }, /* raw spd data */
  63. {0}, /* timing parameters */
  64. { {0} }, /* electrical configuration */
  65. {0}, /* electrical parameters */
  66. 0, /* Clock enable mask */
  67. 160 /* Clock delay */
  68. };
  69. struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
  70. {
  71. /* Return the board topology as defined in the board code */
  72. return &board_topology_map;
  73. }
  74. int board_early_init_f(void)
  75. {
  76. /* Configure MPP */
  77. writel(0x00001111, MVEBU_MPP_BASE + 0x00);
  78. writel(0x00000000, MVEBU_MPP_BASE + 0x04);
  79. writel(0x55000000, MVEBU_MPP_BASE + 0x08);
  80. writel(0x55550550, MVEBU_MPP_BASE + 0x0c);
  81. writel(0x55555555, MVEBU_MPP_BASE + 0x10);
  82. writel(0x00100565, MVEBU_MPP_BASE + 0x14);
  83. writel(0x40000000, MVEBU_MPP_BASE + 0x18);
  84. writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
  85. return 0;
  86. }
  87. void spl_board_init(void)
  88. {
  89. }
  90. int board_init(void)
  91. {
  92. /* address of boot parameters */
  93. gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  94. /* window for NVS */
  95. mbus_dt_setup_win(&mbus_state, CONFIG_NVS_LOCATION, CONFIG_NVS_SIZE,
  96. CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS1);
  97. /* DEV_READYn is not needed for NVS, ignore it when accessing CS1 */
  98. writel(0x00004001, MVEBU_DEV_BUS_BASE + 0xc8);
  99. spl_board_init();
  100. return 0;
  101. }
  102. void arch_preboot_os(void)
  103. {
  104. #ifdef CONFIG_WATCHDOG
  105. wdt_stop(gd->watchdog_dev);
  106. #endif
  107. }
  108. static int led_7seg_init(unsigned int segments)
  109. {
  110. int node;
  111. int ret;
  112. int i;
  113. struct gpio_desc desc[8];
  114. node = fdt_node_offset_by_compatible(gd->fdt_blob, 0,
  115. "atl,of-led-7seg");
  116. if (node < 0)
  117. return -ENODEV;
  118. ret = gpio_request_list_by_name_nodev(offset_to_ofnode(node),
  119. "segment-gpios", desc,
  120. ARRAY_SIZE(desc), GPIOD_IS_OUT);
  121. if (ret < 0)
  122. return ret;
  123. for (i = 0; i < ARRAY_SIZE(desc); i++) {
  124. ret = dm_gpio_set_value(&desc[i], !(segments & BIT(i)));
  125. if (ret)
  126. return ret;
  127. }
  128. return 0;
  129. }
  130. #ifdef CONFIG_MISC_INIT_R
  131. int misc_init_r(void)
  132. {
  133. static struct gpio_desc usb_en = {}, nand_wp = {}, phy_reset[2] = {},
  134. led_en = {};
  135. gpio_hog(&usb_en, "atl,usb-enable", "enable-gpio", 1);
  136. gpio_hog(&nand_wp, "atl,nand-protect", "protect-gpio", 1);
  137. gpio_hog_list(phy_reset, ARRAY_SIZE(phy_reset), "atl,phy-reset", "reset-gpio", 0);
  138. gpio_hog(&led_en, "atl,led-enable", "enable-gpio", 1);
  139. #ifdef MTDPARTS_MTDOOPS
  140. env_set("mtdoops", MTDPARTS_MTDOOPS);
  141. #endif
  142. led_7seg_init(0xff);
  143. return 0;
  144. }
  145. #endif
  146. #ifdef CONFIG_DISPLAY_BOARDINFO
  147. int checkboard(void)
  148. {
  149. puts("Board: " CONFIG_SYS_BOARD "\n");
  150. return 0;
  151. }
  152. #endif