openocd.cfg 4.2 KB

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  1. # Synology DS109
  2. interface ftdi
  3. ftdi_vid_pid 0x0403 0x6010
  4. ftdi_layout_init 0x0008 0x000b
  5. ftdi_layout_signal nTRST -data 0x0010 -oe 0x0010
  6. ftdi_layout_signal nSRST -data 0x0040 -oe 0x0040
  7. adapter_khz 2000
  8. # length of reset signal: [ms]
  9. adapter_nsrst_assert_width 1000
  10. # don't talk to JTAG after reset for: [ms]
  11. adapter_nsrst_delay 200
  12. source [find target/feroceon.cfg]
  13. reset_config trst_and_srst srst_nogate
  14. proc ds109_init { } {
  15. # We need to assert DBGRQ while holding nSRST down.
  16. # However DBGACK will be set only when nSRST is released.
  17. # Furthermore, the JTAG interface doesn't respond at all when
  18. # the CPU is in the WFI (wait for interrupts) state, so it is
  19. # possible that initial tap examination failed. So let's
  20. # re-examine the target again here when nSRST is asserted which
  21. # should then succeed.
  22. jtag_reset 0 1
  23. feroceon.cpu arp_examine
  24. halt 0
  25. jtag_reset 0 0
  26. wait_halt
  27. #reset run
  28. #soft_reset_halt
  29. arm mcr 15 0 0 1 0 0x00052078
  30. mww 0xD00100e0 0x1b1b1b9b ;#
  31. mww 0xD0020134 0xbbbbbbbb ;#
  32. mww 0xD0020138 0x00bbbbbb ;#
  33. mww 0xD0001400 0x43000C30 ;# DDR SDRAM Configuration Register
  34. mww 0xD0001404 0x39743000 ;# Dunit Control Low Register
  35. mww 0xD0001408 0x22125551 ;# DDR SDRAM Timing (Low) Register
  36. mww 0xD000140C 0x00000833 ;# DDR SDRAM Timing (High) Register
  37. mww 0xD0001410 0x0000000d ;# DDR SDRAM Address Control Register
  38. mww 0xD0001414 0x00000000 ;# DDR SDRAM Open Pages Control Register
  39. mww 0xD0001418 0x00000000 ;# DDR SDRAM Operation Register
  40. mww 0xD000141C 0x00000C62 ;# DDR SDRAM Mode Register
  41. mww 0xD0001420 0x00000042 ;# DDR SDRAM Extended Mode Register
  42. mww 0xD0001424 0x0000F1FF ;# Dunit Control High Register
  43. mww 0xD0001428 0x00085520 ;# Dunit Control High Register
  44. mww 0xD000147c 0x00008552 ;# Dunit Control High Register
  45. mww 0xD0001500 0x00000000 ;#
  46. mww 0xD0001504 0x07FFFFF1 ;# CS0n Size Register
  47. mww 0xD0001508 0x10000000 ;# CS1n Base Register
  48. mww 0xD000150C 0x00000000 ;# CS1n Size Register
  49. mww 0xD0001510 0x20000000 ;#
  50. mww 0xD0001514 0x00000000 ;# CS2n Size Register
  51. mww 0xD000151C 0x00000000 ;# CS3n Size Register
  52. mww 0xD0001494 0x003C0000 ;# DDR2 SDRAM ODT Control (Low) Register
  53. mww 0xD0001498 0x00000000 ;# DDR2 SDRAM ODT Control (High) REgister
  54. mww 0xD000149C 0x0000F80F ;# DDR2 Dunit ODT Control Register
  55. mww 0xD0001480 0x00000001 ;# DDR SDRAM Initialization Control Register
  56. mww 0xD0020204 0x00000000 ;# Main IRQ Interrupt Mask Register
  57. mww 0xD0020204 0x00000000 ;# "
  58. mww 0xD0020204 0x00000000 ;# "
  59. mww 0xD0020204 0x00000000 ;# "
  60. mww 0xD0020204 0x00000000 ;# "
  61. mww 0xD0020204 0x00000000 ;# "
  62. mww 0xD0020204 0x00000000 ;# "
  63. mww 0xD0020204 0x00000000 ;# "
  64. mww 0xD0020204 0x00000000 ;# "
  65. mww 0xD0020204 0x00000000 ;# "
  66. mww 0xD0020204 0x00000000 ;# "
  67. mww 0xD0020204 0x00000000 ;# "
  68. mww 0xD0020204 0x00000000 ;# "
  69. mww 0xD0020204 0x00000000 ;# "
  70. mww 0xD0020204 0x00000000 ;# "
  71. mww 0xD0020204 0x00000000 ;# "
  72. mww 0xD0020204 0x00000000 ;# "
  73. mww 0xD0020204 0x00000000 ;# "
  74. mww 0xD0020204 0x00000000 ;# "
  75. mww 0xD0020204 0x00000000 ;# "
  76. mww 0xD0020204 0x00000000 ;# "
  77. mww 0xD0020204 0x00000000 ;# "
  78. mww 0xD0020204 0x00000000 ;# "
  79. mww 0xD0020204 0x00000000 ;# "
  80. mww 0xD0020204 0x00000000 ;# "
  81. mww 0xD0020204 0x00000000 ;# "
  82. mww 0xD0020204 0x00000000 ;# "
  83. mww 0xD0020204 0x00000000 ;# "
  84. mww 0xD0020204 0x00000000 ;# "
  85. mww 0xD0020204 0x00000000 ;# "
  86. mww 0xD0020204 0x00000000 ;# "
  87. mww 0xD0020204 0x00000000 ;# "
  88. mww 0xD0020204 0x00000000 ;# "
  89. mww 0xD0020204 0x00000000 ;# "
  90. mww 0xD0020204 0x00000000 ;# "
  91. mww 0xD0020204 0x00000000 ;# "
  92. mww 0xD0020204 0x00000000 ;# "
  93. mww 0xD0010000 0x01111111 ;# MPP 0 to 7
  94. mww 0xD0010004 0x11113322 ;# MPP 8 to 15
  95. mww 0xD0010008 0x00001111 ;# MPP 16 to 23
  96. }
  97. proc ds109_load { } {
  98. # load u-Boot into RAM and execute it
  99. ds109_init
  100. load_image u-boot.bin 0x00600000 bin
  101. resume 0x00600000
  102. }