mux.c 7.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * mux.c
  4. *
  5. * Pinmux Setting for B&R LEIT Board(s)
  6. *
  7. * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
  8. * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
  9. */
  10. #include <common.h>
  11. #include <asm/arch/sys_proto.h>
  12. #include <asm/arch/hardware.h>
  13. #include <asm/arch/mux.h>
  14. #include <asm/io.h>
  15. #include <i2c.h>
  16. static struct module_pin_mux spi0_pin_mux[] = {
  17. /* SPI1_SCLK */
  18. {OFFSET(spi0_sclk), MODE(0) | PULLUDEN | RXACTIVE},
  19. /* SPI1_D0 */
  20. {OFFSET(spi0_d0), MODE(0) | PULLUDEN | RXACTIVE},
  21. /* SPI1_D1 */
  22. {OFFSET(spi0_d1), MODE(0) | PULLUDEN | RXACTIVE},
  23. /* SPI1_CS0 */
  24. {OFFSET(spi0_cs0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},
  25. /* SPI1_CS1 */
  26. {OFFSET(spi0_cs1), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},
  27. {-1},
  28. };
  29. static struct module_pin_mux dcan0_pin_mux[] = {
  30. /* DCAN0 TX */
  31. {OFFSET(uart1_ctsn), MODE(2) | PULLUDEN | PULLUP_EN},
  32. /* DCAN0 RX */
  33. {OFFSET(uart1_rtsn), MODE(2) | RXACTIVE},
  34. {-1},
  35. };
  36. static struct module_pin_mux dcan1_pin_mux[] = {
  37. /* DCAN1 TX */
  38. {OFFSET(uart1_rxd), MODE(2) | PULLUDEN | PULLUP_EN},
  39. /* DCAN1 RX */
  40. {OFFSET(uart1_txd), MODE(2) | RXACTIVE},
  41. {-1},
  42. };
  43. static struct module_pin_mux gpios[] = {
  44. /* GPIO0_7 (PWW0 OUT) - CAN TERM */
  45. {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | RXACTIVE)},
  46. /* GPIO0_19 (DMA_INTR0) - TA602 */
  47. {OFFSET(xdma_event_intr0), (MODE(7) | PULLUDDIS | RXACTIVE)},
  48. /* GPIO0_20 (DMA_INTR1) - SPI0 nCS1 */
  49. {OFFSET(xdma_event_intr1), (MODE(7) | PULLUDDIS | RXACTIVE)},
  50. /* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */
  51. {OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS)},
  52. /* GPIO0_30 (GPMC_WAIT0) - TA601 */
  53. {OFFSET(gpmc_wait0), (MODE(7) | PULLUDDIS | RXACTIVE)},
  54. /* GPIO0_31 (GPMC_nWP) - SW601 PushButton */
  55. {OFFSET(gpmc_wpn), (MODE(7) | PULLUDDIS | RXACTIVE)},
  56. /* GPIO1_28 (GPMC_nWE) - FRAM_nWP */
  57. {OFFSET(gpmc_be1n), (MODE(7) | PULLUDDIS)},
  58. /* GPIO1_29 (gpmc_csn0) - MMC nRST */
  59. {OFFSET(gpmc_csn0), (MODE(7) | PULLUDDIS)},
  60. /* GPIO2_0 (GPMC_nCS3) - VBAT_OK */
  61. {OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) },
  62. /* GPIO2_2 (GPMC_nADV_ALE) - DCOK */
  63. {OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS | RXACTIVE)},
  64. /* GPIO2_4 (GPMC_nWE) - TST_BAST */
  65. {OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS)},
  66. /* GPIO2_5 (gpmc_be0n_cle) - DISPLAY_ON_OFF */
  67. {OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDDIS)},
  68. /* GPIO3_16 (mcasp0_axr0) - ETH-LED green */
  69. {OFFSET(mcasp0_axr0), (MODE(7) | PULLUDDIS | RXACTIVE)},
  70. /* GPIO3_17 (mcasp0_ahclkr) - CAN_STB */
  71. {OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS | RXACTIVE)},
  72. /* GPIO3_18 (MCASP0_ACLKR) - SW601 CNTup, mapped to Counter eQEB0A_in */
  73. {OFFSET(mcasp0_aclkr), (MODE(1) | PULLUDDIS | RXACTIVE)},
  74. /* GPIO3_19 (MCASP0_FSR) - SW601 CNTdown, mapped to Counter eQEB0B_in */
  75. {OFFSET(mcasp0_fsr), (MODE(1) | PULLUDDIS | RXACTIVE)},
  76. /* GPIO3_20 (MCASP0_AXR1) - SW601 CNTdown, map to Counter eQEB0_index */
  77. {OFFSET(mcasp0_axr1), (MODE(1) | PULLUDDIS | RXACTIVE)},
  78. {-1},
  79. };
  80. static struct module_pin_mux uart0_pin_mux[] = {
  81. /* UART0_CTS */
  82. {OFFSET(uart0_ctsn), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
  83. /* UART0_RXD */
  84. {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
  85. /* UART0_TXD */
  86. {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
  87. {-1},
  88. };
  89. static struct module_pin_mux i2c0_pin_mux[] = {
  90. /* I2C_DATA */
  91. {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
  92. /* I2C_SCLK */
  93. {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
  94. {-1},
  95. };
  96. static struct module_pin_mux mii1_pin_mux[] = {
  97. {OFFSET(mii1_crs), MODE(0) | RXACTIVE}, /* MII1_CRS */
  98. {OFFSET(mii1_col), MODE(0) | RXACTIVE}, /* MII1_COL */
  99. {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
  100. {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
  101. {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
  102. {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
  103. {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
  104. {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
  105. {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
  106. {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
  107. {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
  108. {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
  109. {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
  110. {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
  111. {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
  112. {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
  113. {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
  114. {-1},
  115. };
  116. static struct module_pin_mux mmc1_pin_mux[] = {
  117. {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */
  118. {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */
  119. {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */
  120. {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */
  121. {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
  122. {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
  123. {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
  124. {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
  125. {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
  126. {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
  127. {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
  128. {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */
  129. {-1},
  130. };
  131. static struct module_pin_mux lcd_pin_mux[] = {
  132. {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD-Data(0) */
  133. {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD-Data(1) */
  134. {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD-Data(2) */
  135. {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD-Data(3) */
  136. {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD-Data(4) */
  137. {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD-Data(5) */
  138. {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD-Data(6) */
  139. {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD-Data(7) */
  140. {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD-Data(8) */
  141. {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD-Data(9) */
  142. {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD-Data(10) */
  143. {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD-Data(11) */
  144. {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD-Data(12) */
  145. {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD-Data(13) */
  146. {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD-Data(14) */
  147. {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD-Data(15) */
  148. {OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, /* LCD-Data(16) */
  149. {OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, /* LCD-Data(17) */
  150. {OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, /* LCD-Data(18) */
  151. {OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, /* LCD-Data(19) */
  152. {OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, /* LCD-Data(20) */
  153. {OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, /* LCD-Data(21) */
  154. {OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, /* LCD-Data(22) */
  155. {OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, /* LCD-Data(23) */
  156. {OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)}, /* LCD-VSync */
  157. {OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)}, /* LCD-HSync */
  158. {OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
  159. {OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)}, /* LCD-CLK */
  160. {-1},
  161. };
  162. void enable_uart0_pin_mux(void)
  163. {
  164. configure_module_pin_mux(uart0_pin_mux);
  165. }
  166. void enable_i2c_pin_mux(void)
  167. {
  168. configure_module_pin_mux(i2c0_pin_mux);
  169. }
  170. void enable_board_pin_mux(void)
  171. {
  172. configure_module_pin_mux(i2c0_pin_mux);
  173. configure_module_pin_mux(mii1_pin_mux);
  174. configure_module_pin_mux(spi0_pin_mux);
  175. configure_module_pin_mux(dcan0_pin_mux);
  176. configure_module_pin_mux(dcan1_pin_mux);
  177. configure_module_pin_mux(mmc1_pin_mux);
  178. configure_module_pin_mux(lcd_pin_mux);
  179. configure_module_pin_mux(gpios);
  180. }