Kconfig 16 KB

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  1. menu "MIPS architecture"
  2. depends on MIPS
  3. config SYS_ARCH
  4. default "mips"
  5. config SYS_CPU
  6. default "mips32" if CPU_MIPS32
  7. default "mips64" if CPU_MIPS64
  8. choice
  9. prompt "Target select"
  10. optional
  11. config TARGET_QEMU_MIPS
  12. bool "Support qemu-mips"
  13. select ROM_EXCEPTION_VECTORS
  14. select SUPPORTS_BIG_ENDIAN
  15. select SUPPORTS_CPU_MIPS32_R1
  16. select SUPPORTS_CPU_MIPS32_R2
  17. select SUPPORTS_CPU_MIPS64_R1
  18. select SUPPORTS_CPU_MIPS64_R2
  19. select SUPPORTS_LITTLE_ENDIAN
  20. config TARGET_MALTA
  21. bool "Support malta"
  22. select DM
  23. select DM_SERIAL
  24. select DYNAMIC_IO_PORT_BASE
  25. select MIPS_CM
  26. select MIPS_INSERT_BOOT_CONFIG
  27. select MIPS_L1_CACHE_SHIFT_6
  28. select MIPS_L2_CACHE
  29. select OF_CONTROL
  30. select OF_ISA_BUS
  31. select ROM_EXCEPTION_VECTORS
  32. select SUPPORTS_BIG_ENDIAN
  33. select SUPPORTS_CPU_MIPS32_R1
  34. select SUPPORTS_CPU_MIPS32_R2
  35. select SUPPORTS_CPU_MIPS32_R6
  36. select SUPPORTS_CPU_MIPS64_R1
  37. select SUPPORTS_CPU_MIPS64_R2
  38. select SUPPORTS_CPU_MIPS64_R6
  39. select SUPPORTS_LITTLE_ENDIAN
  40. select SWAP_IO_SPACE
  41. imply CMD_DM
  42. config TARGET_VCT
  43. bool "Support vct"
  44. select ROM_EXCEPTION_VECTORS
  45. select SUPPORTS_BIG_ENDIAN
  46. select SUPPORTS_CPU_MIPS32_R1
  47. select SUPPORTS_CPU_MIPS32_R2
  48. select SYS_MIPS_CACHE_INIT_RAM_LOAD
  49. config ARCH_ATH79
  50. bool "Support QCA/Atheros ath79"
  51. select DM
  52. select OF_CONTROL
  53. imply CMD_DM
  54. config ARCH_MSCC
  55. bool "Support MSCC VCore-III"
  56. select OF_CONTROL
  57. select DM
  58. config ARCH_BMIPS
  59. bool "Support BMIPS SoCs"
  60. select CLK
  61. select CPU
  62. select DM
  63. select OF_CONTROL
  64. select RAM
  65. select SYSRESET
  66. imply CMD_DM
  67. config ARCH_MTMIPS
  68. bool "Support MediaTek MIPS platforms"
  69. select CLK
  70. imply CMD_DM
  71. select DISPLAY_CPUINFO
  72. select DM
  73. imply DM_ETH
  74. imply DM_GPIO
  75. select DM_RESET
  76. select DM_SERIAL
  77. select PINCTRL
  78. select PINMUX
  79. select PINCONF
  80. select RESET_MTMIPS
  81. imply DM_SPI
  82. imply DM_SPI_FLASH
  83. select LAST_STAGE_INIT
  84. select MIPS_TUNE_24KC
  85. select OF_CONTROL
  86. select ROM_EXCEPTION_VECTORS
  87. select SUPPORTS_CPU_MIPS32_R1
  88. select SUPPORTS_CPU_MIPS32_R2
  89. select SUPPORTS_LITTLE_ENDIAN
  90. select SYSRESET
  91. select SUPPORT_SPL
  92. config ARCH_JZ47XX
  93. bool "Support Ingenic JZ47xx"
  94. select SUPPORT_SPL
  95. select OF_CONTROL
  96. select DM
  97. config ARCH_OCTEON
  98. bool "Support Marvell Octeon CN7xxx platforms"
  99. select CPU_CAVIUM_OCTEON
  100. select DISPLAY_CPUINFO
  101. select DMA_ADDR_T_64BIT
  102. select DM
  103. select DM_ETH
  104. select DM_GPIO
  105. select DM_I2C
  106. select DM_SERIAL
  107. select DM_SPI
  108. select MIPS_L2_CACHE
  109. select MIPS_MACH_EARLY_INIT
  110. select MIPS_TUNE_OCTEON3
  111. select ROM_EXCEPTION_VECTORS
  112. select SUPPORTS_BIG_ENDIAN
  113. select SUPPORTS_CPU_MIPS64_OCTEON
  114. select PHYS_64BIT
  115. select OF_CONTROL
  116. select OF_LIVE
  117. imply CMD_DM
  118. config MACH_PIC32
  119. bool "Support Microchip PIC32"
  120. select DM
  121. select OF_CONTROL
  122. imply CMD_DM
  123. config TARGET_BOSTON
  124. bool "Support Boston"
  125. select DM
  126. select DM_SERIAL
  127. select MIPS_CM
  128. select MIPS_L1_CACHE_SHIFT_6
  129. select MIPS_L2_CACHE
  130. select OF_BOARD_SETUP
  131. select OF_CONTROL
  132. select ROM_EXCEPTION_VECTORS
  133. select SUPPORTS_BIG_ENDIAN
  134. select SUPPORTS_CPU_MIPS32_R1
  135. select SUPPORTS_CPU_MIPS32_R2
  136. select SUPPORTS_CPU_MIPS32_R6
  137. select SUPPORTS_CPU_MIPS64_R1
  138. select SUPPORTS_CPU_MIPS64_R2
  139. select SUPPORTS_CPU_MIPS64_R6
  140. select SUPPORTS_LITTLE_ENDIAN
  141. imply CMD_DM
  142. config TARGET_XILFPGA
  143. bool "Support Imagination Xilfpga"
  144. select DM
  145. select DM_ETH
  146. select DM_GPIO
  147. select DM_SERIAL
  148. select MIPS_L1_CACHE_SHIFT_4
  149. select OF_CONTROL
  150. select ROM_EXCEPTION_VECTORS
  151. select SUPPORTS_CPU_MIPS32_R1
  152. select SUPPORTS_CPU_MIPS32_R2
  153. select SUPPORTS_LITTLE_ENDIAN
  154. imply CMD_DM
  155. help
  156. This supports IMGTEC MIPSfpga platform
  157. endchoice
  158. source "board/imgtec/boston/Kconfig"
  159. source "board/imgtec/malta/Kconfig"
  160. source "board/imgtec/xilfpga/Kconfig"
  161. source "board/qemu-mips/Kconfig"
  162. source "arch/mips/mach-ath79/Kconfig"
  163. source "arch/mips/mach-mscc/Kconfig"
  164. source "arch/mips/mach-bmips/Kconfig"
  165. source "arch/mips/mach-jz47xx/Kconfig"
  166. source "arch/mips/mach-pic32/Kconfig"
  167. source "arch/mips/mach-mtmips/Kconfig"
  168. source "arch/mips/mach-octeon/Kconfig"
  169. if MIPS
  170. choice
  171. prompt "Endianness selection"
  172. help
  173. Some MIPS boards can be configured for either little or big endian
  174. byte order. These modes require different U-Boot images. In general there
  175. is one preferred byteorder for a particular system but some systems are
  176. just as commonly used in the one or the other endianness.
  177. config SYS_BIG_ENDIAN
  178. bool "Big endian"
  179. depends on SUPPORTS_BIG_ENDIAN
  180. config SYS_LITTLE_ENDIAN
  181. bool "Little endian"
  182. depends on SUPPORTS_LITTLE_ENDIAN
  183. endchoice
  184. choice
  185. prompt "CPU selection"
  186. default CPU_MIPS32_R2
  187. config CPU_MIPS32_R1
  188. bool "MIPS32 Release 1"
  189. depends on SUPPORTS_CPU_MIPS32_R1
  190. select 32BIT
  191. help
  192. Choose this option to build an U-Boot for release 1 through 5 of the
  193. MIPS32 architecture.
  194. config CPU_MIPS32_R2
  195. bool "MIPS32 Release 2"
  196. depends on SUPPORTS_CPU_MIPS32_R2
  197. select 32BIT
  198. help
  199. Choose this option to build an U-Boot for release 2 through 5 of the
  200. MIPS32 architecture.
  201. config CPU_MIPS32_R6
  202. bool "MIPS32 Release 6"
  203. depends on SUPPORTS_CPU_MIPS32_R6
  204. select 32BIT
  205. help
  206. Choose this option to build an U-Boot for release 6 or later of the
  207. MIPS32 architecture.
  208. config CPU_MIPS64_R1
  209. bool "MIPS64 Release 1"
  210. depends on SUPPORTS_CPU_MIPS64_R1
  211. select 64BIT
  212. help
  213. Choose this option to build a kernel for release 1 through 5 of the
  214. MIPS64 architecture.
  215. config CPU_MIPS64_R2
  216. bool "MIPS64 Release 2"
  217. depends on SUPPORTS_CPU_MIPS64_R2
  218. select 64BIT
  219. help
  220. Choose this option to build a kernel for release 2 through 5 of the
  221. MIPS64 architecture.
  222. config CPU_MIPS64_R6
  223. bool "MIPS64 Release 6"
  224. depends on SUPPORTS_CPU_MIPS64_R6
  225. select 64BIT
  226. help
  227. Choose this option to build a kernel for release 6 or later of the
  228. MIPS64 architecture.
  229. config CPU_MIPS64_OCTEON
  230. bool "Marvell Octeon series of CPUs"
  231. depends on SUPPORTS_CPU_MIPS64_OCTEON
  232. select 64BIT
  233. help
  234. Choose this option for Marvell Octeon CPUs. These CPUs are between
  235. MIPS64 R5 and R6 with other extensions.
  236. endchoice
  237. menu "General setup"
  238. config ROM_EXCEPTION_VECTORS
  239. bool "Build U-Boot image with exception vectors"
  240. help
  241. Enable this to include exception vectors in the U-Boot image. This is
  242. required if the U-Boot entry point is equal to the address of the
  243. CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu,
  244. U-Boot booted from parallel NOR flash).
  245. Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL).
  246. In that case the image size will be reduced by 0x500 bytes.
  247. config MIPS_CM_BASE
  248. hex "MIPS CM GCR Base Address"
  249. depends on MIPS_CM
  250. default 0x16100000 if TARGET_BOSTON
  251. default 0x1fbf8000
  252. help
  253. The physical base address at which to map the MIPS Coherence Manager
  254. Global Configuration Registers (GCRs). This should be set such that
  255. the GCRs occupy a region of the physical address space which is
  256. otherwise unused, or at minimum that software doesn't need to access.
  257. config MIPS_CACHE_INDEX_BASE
  258. hex "Index base address for cache initialisation"
  259. default 0x80000000 if CPU_MIPS32
  260. default 0xffffffff80000000 if CPU_MIPS64
  261. help
  262. This is the base address for a memory block, which is used for
  263. initialising the cache lines. This is also the base address of a memory
  264. block which is used for loading and filling cache lines when
  265. SYS_MIPS_CACHE_INIT_RAM_LOAD is selected.
  266. Normally this is CKSEG0. If the MIPS system needs to move this block
  267. to some SRAM or ScratchPad RAM, adapt this option accordingly.
  268. config MIPS_MACH_EARLY_INIT
  269. bool "Enable mach specific very early init code"
  270. help
  271. Use this to enable the call to mips_mach_early_init() very early
  272. from start.S. This function can be used e.g. to do some very early
  273. CPU / SoC intitialization or image copying. Its called very early
  274. and at this stage the PC might not match the linking address
  275. (CONFIG_TEXT_BASE) - no absolute jump done until this call.
  276. config MIPS_CACHE_SETUP
  277. bool "Allow generic start code to initialize and setup caches"
  278. default n if SKIP_LOWLEVEL_INIT
  279. default y
  280. help
  281. This allows the generic start code to invoke the generic initialization
  282. of the CPU caches. Disabling this can be useful for RAM boot scenarios
  283. (EJTAG, SPL payload) or for machines which don't need cache initialization
  284. or which want to provide their own cache implementation.
  285. If unsure, say yes.
  286. config MIPS_CACHE_DISABLE
  287. bool "Allow generic start code to initially disable caches"
  288. default n if SKIP_LOWLEVEL_INIT
  289. default y
  290. help
  291. This allows the generic start code to initially disable the CPU caches
  292. and run uncached until the caches are initialized and enabled. Disabling
  293. this can be useful on machines which don't need cache initialization or
  294. which want to provide their own cache implementation.
  295. If unsure, say yes.
  296. config MIPS_RELOCATION_TABLE_SIZE
  297. hex "Relocation table size"
  298. range 0x100 0x10000
  299. default "0x8000"
  300. ---help---
  301. A table of relocation data will be appended to the U-Boot binary
  302. and parsed in relocate_code() to fix up all offsets in the relocated
  303. U-Boot.
  304. This option allows the amount of space reserved for the table to be
  305. adjusted in a range from 256 up to 64k. The default is 32k and should
  306. be ok in most cases. Reduce this value to shrink the size of U-Boot
  307. binary.
  308. The build will fail and a valid size suggested if this is too small.
  309. If unsure, leave at the default value.
  310. config RESTORE_EXCEPTION_VECTOR_BASE
  311. bool "Restore exception vector base before booting linux kernel"
  312. default n
  313. help
  314. In U-Boot the exception vector base will be moved to top of memory,
  315. to be used to display register dump when exception occurs.
  316. But some old linux kernel does not honor the base set in CP0_EBASE.
  317. A modified exception vector base will cause kernel crash.
  318. This option will restore the exception vector base to its previous
  319. value.
  320. If unsure, say N.
  321. config OVERRIDE_EXCEPTION_VECTOR_BASE
  322. bool "Override the exception vector base to be restored"
  323. depends on RESTORE_EXCEPTION_VECTOR_BASE
  324. default n
  325. help
  326. Enable this option if you want to use a different exception vector
  327. base rather than the previously saved one.
  328. config NEW_EXCEPTION_VECTOR_BASE
  329. hex "New exception vector base"
  330. depends on OVERRIDE_EXCEPTION_VECTOR_BASE
  331. range 0x80000000 0xbffff000
  332. default 0x80000000
  333. help
  334. The exception vector base to be restored before booting linux kernel
  335. config INIT_STACK_WITHOUT_MALLOC_F
  336. bool "Do not reserve malloc space on initial stack"
  337. default n
  338. help
  339. Enable this option if you don't want to reserve malloc space on
  340. initial stack. This is useful if the initial stack can't hold large
  341. malloc space. Platform should set the malloc_base later when DRAM is
  342. ready to use.
  343. config SPL_INIT_STACK_WITHOUT_MALLOC_F
  344. bool "Do not reserve malloc space on initial stack in SPL"
  345. default n
  346. help
  347. Enable this option if you don't want to reserve malloc space on
  348. initial stack. This is useful if the initial stack can't hold large
  349. malloc space. Platform should set the malloc_base later when DRAM is
  350. ready to use.
  351. config SPL_LOADER_SUPPORT
  352. bool
  353. default n
  354. help
  355. Enable this option if you want to use SPL loaders without DM enabled.
  356. endmenu
  357. menu "OS boot interface"
  358. config MIPS_BOOT_CMDLINE_LEGACY
  359. bool "Hand over legacy command line to Linux kernel"
  360. default y
  361. help
  362. Enable this option if you want U-Boot to hand over the Yamon-style
  363. command line to the kernel. All bootargs will be prepared as argc/argv
  364. compatible list. The argument count (argc) is stored in register $a0.
  365. The address of the argument list (argv) is stored in register $a1.
  366. config MIPS_BOOT_ENV_LEGACY
  367. bool "Hand over legacy environment to Linux kernel"
  368. default y
  369. help
  370. Enable this option if you want U-Boot to hand over the Yamon-style
  371. environment to the kernel. Information like memory size, initrd
  372. address and size will be prepared as zero-terminated key/value list.
  373. The address of the environment is stored in register $a2.
  374. config MIPS_BOOT_FDT
  375. bool "Hand over a flattened device tree to Linux kernel"
  376. default n
  377. help
  378. Enable this option if you want U-Boot to hand over a flattened
  379. device tree to the kernel. According to UHI register $a0 will be set
  380. to -2 and the FDT address is stored in $a1.
  381. endmenu
  382. config SUPPORTS_BIG_ENDIAN
  383. bool
  384. config SUPPORTS_LITTLE_ENDIAN
  385. bool
  386. config SUPPORTS_CPU_MIPS32_R1
  387. bool
  388. config SUPPORTS_CPU_MIPS32_R2
  389. bool
  390. config SUPPORTS_CPU_MIPS32_R6
  391. bool
  392. config SUPPORTS_CPU_MIPS64_R1
  393. bool
  394. config SUPPORTS_CPU_MIPS64_R2
  395. bool
  396. config SUPPORTS_CPU_MIPS64_R6
  397. bool
  398. config SUPPORTS_CPU_MIPS64_OCTEON
  399. bool
  400. config CPU_CAVIUM_OCTEON
  401. bool
  402. config CPU_MIPS32
  403. bool
  404. default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
  405. config CPU_MIPS64
  406. bool
  407. default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
  408. default y if CPU_MIPS64_OCTEON
  409. config MIPS_TUNE_4KC
  410. bool
  411. config MIPS_TUNE_14KC
  412. bool
  413. config MIPS_TUNE_24KC
  414. bool
  415. config MIPS_TUNE_34KC
  416. bool
  417. config MIPS_TUNE_74KC
  418. bool
  419. config MIPS_TUNE_OCTEON3
  420. bool
  421. config 32BIT
  422. bool
  423. config 64BIT
  424. bool
  425. config SWAP_IO_SPACE
  426. bool
  427. config SYS_MIPS_CACHE_INIT_RAM_LOAD
  428. bool
  429. config MIPS_INIT_STACK_IN_SRAM
  430. bool
  431. default n
  432. help
  433. Select this if the initial stack frame could be setup in SRAM.
  434. Normally the initial stack frame is set up in DRAM which is often
  435. only available after lowlevel_init. With this option the initial
  436. stack frame and the early C environment is set up before
  437. lowlevel_init. Thus lowlevel_init does not need to be implemented
  438. in assembler.
  439. config MIPS_SRAM_INIT
  440. bool
  441. default n
  442. depends on MIPS_INIT_STACK_IN_SRAM
  443. help
  444. Select this if the SRAM for initial stack needs to be initialized
  445. before it can be used. If enabled, a function mips_sram_init() will
  446. be called just before setup_stack_gd.
  447. config DMA_ADDR_T_64BIT
  448. bool
  449. help
  450. Select this to enable 64-bit DMA addressing
  451. config SYS_DCACHE_SIZE
  452. int
  453. default 0
  454. help
  455. The total size of the L1 Dcache, if known at compile time.
  456. config SYS_DCACHE_LINE_SIZE
  457. int
  458. default 0
  459. help
  460. The size of L1 Dcache lines, if known at compile time.
  461. config SYS_ICACHE_SIZE
  462. int
  463. default 0
  464. help
  465. The total size of the L1 ICache, if known at compile time.
  466. config SYS_ICACHE_LINE_SIZE
  467. int
  468. default 0
  469. help
  470. The size of L1 Icache lines, if known at compile time.
  471. config SYS_SCACHE_LINE_SIZE
  472. int
  473. default 0
  474. help
  475. The size of L2 cache lines, if known at compile time.
  476. config SYS_CACHE_SIZE_AUTO
  477. def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
  478. SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 && \
  479. SYS_SCACHE_LINE_SIZE = 0
  480. help
  481. Select this (or let it be auto-selected by not defining any cache
  482. sizes) in order to allow U-Boot to automatically detect the sizes
  483. of caches at runtime. This has a small cost in code size & runtime
  484. so if you know the cache configuration for your system at compile
  485. time it would be beneficial to configure it.
  486. config MIPS_L1_CACHE_SHIFT_4
  487. bool
  488. config MIPS_L1_CACHE_SHIFT_5
  489. bool
  490. config MIPS_L1_CACHE_SHIFT_6
  491. bool
  492. config MIPS_L1_CACHE_SHIFT_7
  493. bool
  494. config MIPS_L1_CACHE_SHIFT
  495. int
  496. default "7" if MIPS_L1_CACHE_SHIFT_7
  497. default "6" if MIPS_L1_CACHE_SHIFT_6
  498. default "5" if MIPS_L1_CACHE_SHIFT_5
  499. default "4" if MIPS_L1_CACHE_SHIFT_4
  500. default "5"
  501. config MIPS_L2_CACHE
  502. bool
  503. help
  504. Select this if your system includes an L2 cache and you want U-Boot
  505. to initialise & maintain it.
  506. config DYNAMIC_IO_PORT_BASE
  507. bool
  508. config MIPS_CM
  509. bool
  510. help
  511. Select this if your system contains a MIPS Coherence Manager and you
  512. wish U-Boot to configure it or make use of it to retrieve system
  513. information such as cache configuration.
  514. config MIPS_INSERT_BOOT_CONFIG
  515. bool
  516. default n
  517. help
  518. Enable this to insert some board-specific boot configuration in
  519. the U-Boot binary at offset 0x10.
  520. config MIPS_BOOT_CONFIG_WORD0
  521. hex
  522. depends on MIPS_INSERT_BOOT_CONFIG
  523. default 0x420 if TARGET_MALTA
  524. default 0x0
  525. help
  526. Value which is inserted as boot config word 0.
  527. config MIPS_BOOT_CONFIG_WORD1
  528. hex
  529. depends on MIPS_INSERT_BOOT_CONFIG
  530. default 0x0
  531. help
  532. Value which is inserted as boot config word 1.
  533. endif
  534. endmenu