board.c 17 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709
  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
  4. */
  5. #include <common.h>
  6. #include <adc.h>
  7. #include <log.h>
  8. #include <net.h>
  9. #include <asm/arch/stm32.h>
  10. #include <asm/arch/sys_proto.h>
  11. #include <asm/gpio.h>
  12. #include <asm/io.h>
  13. #include <bootm.h>
  14. #include <clk.h>
  15. #include <config.h>
  16. #include <dm.h>
  17. #include <dm/device.h>
  18. #include <dm/uclass.h>
  19. #include <env.h>
  20. #include <env_internal.h>
  21. #include <g_dnl.h>
  22. #include <generic-phy.h>
  23. #include <hang.h>
  24. #include <i2c.h>
  25. #include <i2c_eeprom.h>
  26. #include <init.h>
  27. #include <led.h>
  28. #include <memalign.h>
  29. #include <misc.h>
  30. #include <mtd.h>
  31. #include <mtd_node.h>
  32. #include <netdev.h>
  33. #include <phy.h>
  34. #include <linux/bitops.h>
  35. #include <linux/delay.h>
  36. #include <power/regulator.h>
  37. #include <remoteproc.h>
  38. #include <reset.h>
  39. #include <syscon.h>
  40. #include <usb.h>
  41. #include <usb/dwc2_udc.h>
  42. #include <watchdog.h>
  43. #include "../../st/common/stpmic1.h"
  44. /* SYSCFG registers */
  45. #define SYSCFG_BOOTR 0x00
  46. #define SYSCFG_PMCSETR 0x04
  47. #define SYSCFG_IOCTRLSETR 0x18
  48. #define SYSCFG_ICNR 0x1C
  49. #define SYSCFG_CMPCR 0x20
  50. #define SYSCFG_CMPENSETR 0x24
  51. #define SYSCFG_PMCCLRR 0x44
  52. #define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0)
  53. #define SYSCFG_BOOTR_BOOTPD_SHIFT 4
  54. #define SYSCFG_IOCTRLSETR_HSLVEN_TRACE BIT(0)
  55. #define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI BIT(1)
  56. #define SYSCFG_IOCTRLSETR_HSLVEN_ETH BIT(2)
  57. #define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC BIT(3)
  58. #define SYSCFG_IOCTRLSETR_HSLVEN_SPI BIT(4)
  59. #define SYSCFG_CMPCR_SW_CTRL BIT(1)
  60. #define SYSCFG_CMPCR_READY BIT(8)
  61. #define SYSCFG_CMPENSETR_MPU_EN BIT(0)
  62. #define SYSCFG_PMCSETR_ETH_CLK_SEL BIT(16)
  63. #define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17)
  64. #define SYSCFG_PMCSETR_ETH_SELMII BIT(20)
  65. #define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21)
  66. #define SYSCFG_PMCSETR_ETH_SEL_GMII_MII 0
  67. #define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21)
  68. #define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23)
  69. /*
  70. * Get a global data pointer
  71. */
  72. DECLARE_GLOBAL_DATA_PTR;
  73. int setup_mac_address(void)
  74. {
  75. unsigned char enetaddr[6];
  76. bool skip_eth0 = false;
  77. bool skip_eth1 = false;
  78. struct udevice *dev;
  79. int off, ret;
  80. ret = eth_env_get_enetaddr("ethaddr", enetaddr);
  81. if (ret) /* ethaddr is already set */
  82. skip_eth0 = true;
  83. off = fdt_path_offset(gd->fdt_blob, "ethernet1");
  84. if (off < 0) {
  85. /* ethernet1 is not present in the system */
  86. skip_eth1 = true;
  87. } else {
  88. ret = eth_env_get_enetaddr("eth1addr", enetaddr);
  89. if (ret) /* eth1addr is already set */
  90. skip_eth1 = true;
  91. }
  92. if (skip_eth0 && skip_eth1)
  93. return 0;
  94. off = fdt_path_offset(gd->fdt_blob, "eeprom0");
  95. if (off < 0) {
  96. printf("%s: No eeprom0 path offset\n", __func__);
  97. return off;
  98. }
  99. ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
  100. if (ret) {
  101. printf("Cannot find EEPROM!\n");
  102. return ret;
  103. }
  104. ret = i2c_eeprom_read(dev, 0xfa, enetaddr, 0x6);
  105. if (ret) {
  106. printf("Error reading configuration EEPROM!\n");
  107. return ret;
  108. }
  109. if (is_valid_ethaddr(enetaddr)) {
  110. if (!skip_eth0)
  111. eth_env_set_enetaddr("ethaddr", enetaddr);
  112. enetaddr[5]++;
  113. if (!skip_eth1)
  114. eth_env_set_enetaddr("eth1addr", enetaddr);
  115. }
  116. return 0;
  117. }
  118. int checkboard(void)
  119. {
  120. char *mode;
  121. const char *fdt_compat;
  122. int fdt_compat_len;
  123. if (IS_ENABLED(CONFIG_TFABOOT))
  124. mode = "trusted";
  125. else
  126. mode = "basic";
  127. printf("Board: stm32mp1 in %s mode", mode);
  128. fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
  129. &fdt_compat_len);
  130. if (fdt_compat && fdt_compat_len)
  131. printf(" (%s)", fdt_compat);
  132. puts("\n");
  133. return 0;
  134. }
  135. #ifdef CONFIG_BOARD_EARLY_INIT_F
  136. static u8 brdcode __section("data");
  137. static u8 ddr3code __section("data");
  138. static u8 somcode __section("data");
  139. static u32 opp_voltage_mv __section(".data");
  140. static void board_get_coding_straps(void)
  141. {
  142. struct gpio_desc gpio[4];
  143. ofnode node;
  144. int i, ret;
  145. node = ofnode_path("/config");
  146. if (!ofnode_valid(node)) {
  147. printf("%s: no /config node?\n", __func__);
  148. return;
  149. }
  150. brdcode = 0;
  151. ddr3code = 0;
  152. somcode = 0;
  153. ret = gpio_request_list_by_name_nodev(node, "dh,som-coding-gpios",
  154. gpio, ARRAY_SIZE(gpio),
  155. GPIOD_IS_IN);
  156. for (i = 0; i < ret; i++)
  157. somcode |= !!dm_gpio_get_value(&(gpio[i])) << i;
  158. ret = gpio_request_list_by_name_nodev(node, "dh,ddr3-coding-gpios",
  159. gpio, ARRAY_SIZE(gpio),
  160. GPIOD_IS_IN);
  161. for (i = 0; i < ret; i++)
  162. ddr3code |= !!dm_gpio_get_value(&(gpio[i])) << i;
  163. ret = gpio_request_list_by_name_nodev(node, "dh,board-coding-gpios",
  164. gpio, ARRAY_SIZE(gpio),
  165. GPIOD_IS_IN);
  166. for (i = 0; i < ret; i++)
  167. brdcode |= !!dm_gpio_get_value(&(gpio[i])) << i;
  168. printf("Code: SoM:rev=%d,ddr3=%d Board:rev=%d\n",
  169. somcode, ddr3code, brdcode);
  170. }
  171. int board_stm32mp1_ddr_config_name_match(struct udevice *dev,
  172. const char *name)
  173. {
  174. if (ddr3code == 1 &&
  175. !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x1gb-533mhz"))
  176. return 0;
  177. if (ddr3code == 2 &&
  178. !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x2gb-533mhz"))
  179. return 0;
  180. if (ddr3code == 3 &&
  181. !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x4gb-533mhz"))
  182. return 0;
  183. return -EINVAL;
  184. }
  185. void board_vddcore_init(u32 voltage_mv)
  186. {
  187. if (IS_ENABLED(CONFIG_SPL_BUILD))
  188. opp_voltage_mv = voltage_mv;
  189. }
  190. int board_early_init_f(void)
  191. {
  192. if (IS_ENABLED(CONFIG_SPL_BUILD))
  193. stpmic1_init(opp_voltage_mv);
  194. board_get_coding_straps();
  195. return 0;
  196. }
  197. #ifdef CONFIG_SPL_LOAD_FIT
  198. int board_fit_config_name_match(const char *name)
  199. {
  200. const char *compat;
  201. char test[128];
  202. compat = fdt_getprop(gd->fdt_blob, 0, "compatible", NULL);
  203. snprintf(test, sizeof(test), "%s_somrev%d_boardrev%d",
  204. compat, somcode, brdcode);
  205. if (!strcmp(name, test))
  206. return 0;
  207. return -EINVAL;
  208. }
  209. #endif
  210. #endif
  211. static void board_key_check(void)
  212. {
  213. #if defined(CONFIG_FASTBOOT) || defined(CONFIG_CMD_STM32PROG)
  214. ofnode node;
  215. struct gpio_desc gpio;
  216. enum forced_boot_mode boot_mode = BOOT_NORMAL;
  217. node = ofnode_path("/config");
  218. if (!ofnode_valid(node)) {
  219. debug("%s: no /config node?\n", __func__);
  220. return;
  221. }
  222. #ifdef CONFIG_FASTBOOT
  223. if (gpio_request_by_name_nodev(node, "st,fastboot-gpios", 0,
  224. &gpio, GPIOD_IS_IN)) {
  225. debug("%s: could not find a /config/st,fastboot-gpios\n",
  226. __func__);
  227. } else {
  228. if (dm_gpio_get_value(&gpio)) {
  229. puts("Fastboot key pressed, ");
  230. boot_mode = BOOT_FASTBOOT;
  231. }
  232. dm_gpio_free(NULL, &gpio);
  233. }
  234. #endif
  235. #ifdef CONFIG_CMD_STM32PROG
  236. if (gpio_request_by_name_nodev(node, "st,stm32prog-gpios", 0,
  237. &gpio, GPIOD_IS_IN)) {
  238. debug("%s: could not find a /config/st,stm32prog-gpios\n",
  239. __func__);
  240. } else {
  241. if (dm_gpio_get_value(&gpio)) {
  242. puts("STM32Programmer key pressed, ");
  243. boot_mode = BOOT_STM32PROG;
  244. }
  245. dm_gpio_free(NULL, &gpio);
  246. }
  247. #endif
  248. if (boot_mode != BOOT_NORMAL) {
  249. puts("entering download mode...\n");
  250. clrsetbits_le32(TAMP_BOOT_CONTEXT,
  251. TAMP_BOOT_FORCED_MASK,
  252. boot_mode);
  253. }
  254. #endif
  255. }
  256. #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
  257. #include <usb/dwc2_udc.h>
  258. int g_dnl_board_usb_cable_connected(void)
  259. {
  260. struct udevice *dwc2_udc_otg;
  261. int ret;
  262. ret = uclass_get_device_by_driver(UCLASS_USB_GADGET_GENERIC,
  263. DM_GET_DRIVER(dwc2_udc_otg),
  264. &dwc2_udc_otg);
  265. if (!ret)
  266. debug("dwc2_udc_otg init failed\n");
  267. return dwc2_udc_B_session_valid(dwc2_udc_otg);
  268. }
  269. #define STM32MP1_G_DNL_DFU_PRODUCT_NUM 0xdf11
  270. #define STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM 0x0afb
  271. int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
  272. {
  273. if (!strcmp(name, "usb_dnl_dfu"))
  274. put_unaligned(STM32MP1_G_DNL_DFU_PRODUCT_NUM, &dev->idProduct);
  275. else if (!strcmp(name, "usb_dnl_fastboot"))
  276. put_unaligned(STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM,
  277. &dev->idProduct);
  278. else
  279. put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM, &dev->idProduct);
  280. return 0;
  281. }
  282. #endif /* CONFIG_USB_GADGET */
  283. #ifdef CONFIG_LED
  284. static int get_led(struct udevice **dev, char *led_string)
  285. {
  286. char *led_name;
  287. int ret;
  288. led_name = fdtdec_get_config_string(gd->fdt_blob, led_string);
  289. if (!led_name) {
  290. pr_debug("%s: could not find %s config string\n",
  291. __func__, led_string);
  292. return -ENOENT;
  293. }
  294. ret = led_get_by_label(led_name, dev);
  295. if (ret) {
  296. debug("%s: get=%d\n", __func__, ret);
  297. return ret;
  298. }
  299. return 0;
  300. }
  301. static int setup_led(enum led_state_t cmd)
  302. {
  303. struct udevice *dev;
  304. int ret;
  305. ret = get_led(&dev, "u-boot,boot-led");
  306. if (ret)
  307. return ret;
  308. ret = led_set_state(dev, cmd);
  309. return ret;
  310. }
  311. #endif
  312. static void __maybe_unused led_error_blink(u32 nb_blink)
  313. {
  314. #ifdef CONFIG_LED
  315. int ret;
  316. struct udevice *led;
  317. u32 i;
  318. #endif
  319. if (!nb_blink)
  320. return;
  321. #ifdef CONFIG_LED
  322. ret = get_led(&led, "u-boot,error-led");
  323. if (!ret) {
  324. /* make u-boot,error-led blinking */
  325. /* if U32_MAX and 125ms interval, for 17.02 years */
  326. for (i = 0; i < 2 * nb_blink; i++) {
  327. led_set_state(led, LEDST_TOGGLE);
  328. mdelay(125);
  329. WATCHDOG_RESET();
  330. }
  331. }
  332. #endif
  333. /* infinite: the boot process must be stopped */
  334. if (nb_blink == U32_MAX)
  335. hang();
  336. }
  337. static void sysconf_init(void)
  338. {
  339. #ifndef CONFIG_TFABOOT
  340. u8 *syscfg;
  341. #ifdef CONFIG_DM_REGULATOR
  342. struct udevice *pwr_dev;
  343. struct udevice *pwr_reg;
  344. struct udevice *dev;
  345. int ret;
  346. u32 otp = 0;
  347. #endif
  348. u32 bootr;
  349. syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
  350. /* interconnect update : select master using the port 1 */
  351. /* LTDC = AXI_M9 */
  352. /* GPU = AXI_M8 */
  353. /* today information is hardcoded in U-Boot */
  354. writel(BIT(9), syscfg + SYSCFG_ICNR);
  355. /* disable Pull-Down for boot pin connected to VDD */
  356. bootr = readl(syscfg + SYSCFG_BOOTR);
  357. bootr &= ~(SYSCFG_BOOTR_BOOT_MASK << SYSCFG_BOOTR_BOOTPD_SHIFT);
  358. bootr |= (bootr & SYSCFG_BOOTR_BOOT_MASK) << SYSCFG_BOOTR_BOOTPD_SHIFT;
  359. writel(bootr, syscfg + SYSCFG_BOOTR);
  360. #ifdef CONFIG_DM_REGULATOR
  361. /* High Speed Low Voltage Pad mode Enable for SPI, SDMMC, ETH, QSPI
  362. * and TRACE. Needed above ~50MHz and conditioned by AFMUX selection.
  363. * The customer will have to disable this for low frequencies
  364. * or if AFMUX is selected but the function not used, typically for
  365. * TRACE. Otherwise, impact on power consumption.
  366. *
  367. * WARNING:
  368. * enabling High Speed mode while VDD>2.7V
  369. * with the OTP product_below_2v5 (OTP 18, BIT 13)
  370. * erroneously set to 1 can damage the IC!
  371. * => U-Boot set the register only if VDD < 2.7V (in DT)
  372. * but this value need to be consistent with board design
  373. */
  374. ret = uclass_get_device_by_driver(UCLASS_PMIC,
  375. DM_GET_DRIVER(stm32mp_pwr_pmic),
  376. &pwr_dev);
  377. if (!ret) {
  378. ret = uclass_get_device_by_driver(UCLASS_MISC,
  379. DM_GET_DRIVER(stm32mp_bsec),
  380. &dev);
  381. if (ret) {
  382. pr_err("Can't find stm32mp_bsec driver\n");
  383. return;
  384. }
  385. ret = misc_read(dev, STM32_BSEC_SHADOW(18), &otp, 4);
  386. if (ret > 0)
  387. otp = otp & BIT(13);
  388. /* get VDD = vdd-supply */
  389. ret = device_get_supply_regulator(pwr_dev, "vdd-supply",
  390. &pwr_reg);
  391. /* check if VDD is Low Voltage */
  392. if (!ret) {
  393. if (regulator_get_value(pwr_reg) < 2700000) {
  394. writel(SYSCFG_IOCTRLSETR_HSLVEN_TRACE |
  395. SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI |
  396. SYSCFG_IOCTRLSETR_HSLVEN_ETH |
  397. SYSCFG_IOCTRLSETR_HSLVEN_SDMMC |
  398. SYSCFG_IOCTRLSETR_HSLVEN_SPI,
  399. syscfg + SYSCFG_IOCTRLSETR);
  400. if (!otp)
  401. pr_err("product_below_2v5=0: HSLVEN protected by HW\n");
  402. } else {
  403. if (otp)
  404. pr_err("product_below_2v5=1: HSLVEN update is destructive, no update as VDD>2.7V\n");
  405. }
  406. } else {
  407. debug("VDD unknown");
  408. }
  409. }
  410. #endif
  411. /* activate automatic I/O compensation
  412. * warning: need to ensure CSI enabled and ready in clock driver
  413. */
  414. writel(SYSCFG_CMPENSETR_MPU_EN, syscfg + SYSCFG_CMPENSETR);
  415. while (!(readl(syscfg + SYSCFG_CMPCR) & SYSCFG_CMPCR_READY))
  416. ;
  417. clrbits_le32(syscfg + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
  418. #endif
  419. }
  420. static void board_init_fmc2(void)
  421. {
  422. #define STM32_FMC2_BCR1 0x0
  423. #define STM32_FMC2_BTR1 0x4
  424. #define STM32_FMC2_BWTR1 0x104
  425. #define STM32_FMC2_BCR(x) ((x) * 0x8 + STM32_FMC2_BCR1)
  426. #define STM32_FMC2_BCRx_FMCEN BIT(31)
  427. #define STM32_FMC2_BCRx_WREN BIT(12)
  428. #define STM32_FMC2_BCRx_RSVD BIT(7)
  429. #define STM32_FMC2_BCRx_FACCEN BIT(6)
  430. #define STM32_FMC2_BCRx_MWID(n) ((n) << 4)
  431. #define STM32_FMC2_BCRx_MTYP(n) ((n) << 2)
  432. #define STM32_FMC2_BCRx_MUXEN BIT(1)
  433. #define STM32_FMC2_BCRx_MBKEN BIT(0)
  434. #define STM32_FMC2_BTR(x) ((x) * 0x8 + STM32_FMC2_BTR1)
  435. #define STM32_FMC2_BTRx_DATAHLD(n) ((n) << 30)
  436. #define STM32_FMC2_BTRx_BUSTURN(n) ((n) << 16)
  437. #define STM32_FMC2_BTRx_DATAST(n) ((n) << 8)
  438. #define STM32_FMC2_BTRx_ADDHLD(n) ((n) << 4)
  439. #define STM32_FMC2_BTRx_ADDSET(n) ((n) << 0)
  440. #define RCC_MP_AHB6RSTCLRR 0x218
  441. #define RCC_MP_AHB6RSTCLRR_FMCRST BIT(12)
  442. #define RCC_MP_AHB6ENSETR 0x19c
  443. #define RCC_MP_AHB6ENSETR_FMCEN BIT(12)
  444. const u32 bcr = STM32_FMC2_BCRx_WREN |STM32_FMC2_BCRx_RSVD |
  445. STM32_FMC2_BCRx_FACCEN | STM32_FMC2_BCRx_MWID(1) |
  446. STM32_FMC2_BCRx_MTYP(2) | STM32_FMC2_BCRx_MUXEN |
  447. STM32_FMC2_BCRx_MBKEN;
  448. const u32 btr = STM32_FMC2_BTRx_DATAHLD(3) |
  449. STM32_FMC2_BTRx_BUSTURN(2) |
  450. STM32_FMC2_BTRx_DATAST(0x22) |
  451. STM32_FMC2_BTRx_ADDHLD(2) |
  452. STM32_FMC2_BTRx_ADDSET(2);
  453. /* Set up FMC2 bus for KS8851-16MLL and X11 SRAM */
  454. writel(RCC_MP_AHB6RSTCLRR_FMCRST, STM32_RCC_BASE + RCC_MP_AHB6RSTCLRR);
  455. writel(RCC_MP_AHB6ENSETR_FMCEN, STM32_RCC_BASE + RCC_MP_AHB6ENSETR);
  456. /* KS8851-16MLL -- Muxed mode */
  457. writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(1));
  458. writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(1));
  459. /* AS7C34098 SRAM on X11 -- Muxed mode */
  460. writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(3));
  461. writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(3));
  462. setbits_le32(STM32_FMC2_BASE + STM32_FMC2_BCR1, STM32_FMC2_BCRx_FMCEN);
  463. }
  464. /* board dependent setup after realloc */
  465. int board_init(void)
  466. {
  467. /* address of boot parameters */
  468. gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
  469. if (CONFIG_IS_ENABLED(DM_GPIO_HOG))
  470. gpio_hog_probe_all();
  471. board_key_check();
  472. #ifdef CONFIG_DM_REGULATOR
  473. regulators_enable_boot_on(_DEBUG);
  474. #endif
  475. sysconf_init();
  476. board_init_fmc2();
  477. if (CONFIG_IS_ENABLED(LED))
  478. led_default_state();
  479. return 0;
  480. }
  481. int board_late_init(void)
  482. {
  483. char *boot_device;
  484. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  485. const void *fdt_compat;
  486. int fdt_compat_len;
  487. fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
  488. &fdt_compat_len);
  489. if (fdt_compat && fdt_compat_len) {
  490. if (strncmp(fdt_compat, "st,", 3) != 0)
  491. env_set("board_name", fdt_compat);
  492. else
  493. env_set("board_name", fdt_compat + 3);
  494. }
  495. #endif
  496. /* Check the boot-source to disable bootdelay */
  497. boot_device = env_get("boot_device");
  498. if (!strcmp(boot_device, "serial") || !strcmp(boot_device, "usb"))
  499. env_set("bootdelay", "0");
  500. #ifdef CONFIG_BOARD_EARLY_INIT_F
  501. env_set_ulong("dh_som_rev", somcode);
  502. env_set_ulong("dh_board_rev", brdcode);
  503. env_set_ulong("dh_ddr3_code", ddr3code);
  504. #endif
  505. return 0;
  506. }
  507. void board_quiesce_devices(void)
  508. {
  509. #ifdef CONFIG_LED
  510. setup_led(LEDST_OFF);
  511. #endif
  512. }
  513. /* eth init function : weak called in eqos driver */
  514. int board_interface_eth_init(struct udevice *dev,
  515. phy_interface_t interface_type)
  516. {
  517. u8 *syscfg;
  518. u32 value;
  519. bool eth_clk_sel_reg = false;
  520. bool eth_ref_clk_sel_reg = false;
  521. /* Gigabit Ethernet 125MHz clock selection. */
  522. eth_clk_sel_reg = dev_read_bool(dev, "st,eth_clk_sel");
  523. /* Ethernet 50Mhz RMII clock selection */
  524. eth_ref_clk_sel_reg =
  525. dev_read_bool(dev, "st,eth_ref_clk_sel");
  526. syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
  527. if (!syscfg)
  528. return -ENODEV;
  529. switch (interface_type) {
  530. case PHY_INTERFACE_MODE_MII:
  531. value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
  532. SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
  533. debug("%s: PHY_INTERFACE_MODE_MII\n", __func__);
  534. break;
  535. case PHY_INTERFACE_MODE_GMII:
  536. if (eth_clk_sel_reg)
  537. value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
  538. SYSCFG_PMCSETR_ETH_CLK_SEL;
  539. else
  540. value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII;
  541. debug("%s: PHY_INTERFACE_MODE_GMII\n", __func__);
  542. break;
  543. case PHY_INTERFACE_MODE_RMII:
  544. if (eth_ref_clk_sel_reg)
  545. value = SYSCFG_PMCSETR_ETH_SEL_RMII |
  546. SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
  547. else
  548. value = SYSCFG_PMCSETR_ETH_SEL_RMII;
  549. debug("%s: PHY_INTERFACE_MODE_RMII\n", __func__);
  550. break;
  551. case PHY_INTERFACE_MODE_RGMII:
  552. case PHY_INTERFACE_MODE_RGMII_ID:
  553. case PHY_INTERFACE_MODE_RGMII_RXID:
  554. case PHY_INTERFACE_MODE_RGMII_TXID:
  555. if (eth_clk_sel_reg)
  556. value = SYSCFG_PMCSETR_ETH_SEL_RGMII |
  557. SYSCFG_PMCSETR_ETH_CLK_SEL;
  558. else
  559. value = SYSCFG_PMCSETR_ETH_SEL_RGMII;
  560. debug("%s: PHY_INTERFACE_MODE_RGMII\n", __func__);
  561. break;
  562. default:
  563. debug("%s: Do not manage %d interface\n",
  564. __func__, interface_type);
  565. /* Do not manage others interfaces */
  566. return -EINVAL;
  567. }
  568. /* clear and set ETH configuration bits */
  569. writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII |
  570. SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL,
  571. syscfg + SYSCFG_PMCCLRR);
  572. writel(value, syscfg + SYSCFG_PMCSETR);
  573. return 0;
  574. }
  575. #if defined(CONFIG_OF_BOARD_SETUP)
  576. int ft_board_setup(void *blob, struct bd_info *bd)
  577. {
  578. return 0;
  579. }
  580. #endif
  581. static void board_copro_image_process(ulong fw_image, size_t fw_size)
  582. {
  583. int ret, id = 0; /* Copro id fixed to 0 as only one coproc on mp1 */
  584. if (!rproc_is_initialized())
  585. if (rproc_init()) {
  586. printf("Remote Processor %d initialization failed\n",
  587. id);
  588. return;
  589. }
  590. ret = rproc_load(id, fw_image, fw_size);
  591. printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
  592. id, fw_image, fw_size, ret ? " Failed!" : " Success!");
  593. if (!ret) {
  594. rproc_start(id);
  595. env_set("copro_state", "booted");
  596. }
  597. }
  598. U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_COPRO, board_copro_image_process);