sh7757lcr.c 9.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2011 Renesas Solutions Corp.
  4. */
  5. #include <common.h>
  6. #include <env.h>
  7. #include <environment.h>
  8. #include <malloc.h>
  9. #include <asm/processor.h>
  10. #include <asm/io.h>
  11. #include <asm/mmc.h>
  12. #include <spi.h>
  13. #include <spi_flash.h>
  14. int checkboard(void)
  15. {
  16. puts("BOARD: R0P7757LC0030RL board\n");
  17. return 0;
  18. }
  19. static void init_gctrl(void)
  20. {
  21. struct gctrl_regs *gctrl = GCTRL_BASE;
  22. unsigned long graofst;
  23. graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
  24. writel(graofst | 0x20000f00, &gctrl->gracr3);
  25. }
  26. static int init_pcie_bridge_from_spi(void *buf, size_t size)
  27. {
  28. #ifdef CONFIG_DEPRECATED
  29. struct spi_flash *spi;
  30. int ret;
  31. unsigned long pcie_addr;
  32. spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
  33. if (!spi) {
  34. printf("%s: spi_flash probe error.\n", __func__);
  35. return 1;
  36. }
  37. if (is_sh7757_b0())
  38. pcie_addr = SH7757LCR_PCIEBRG_ADDR_B0;
  39. else
  40. pcie_addr = SH7757LCR_PCIEBRG_ADDR;
  41. ret = spi_flash_read(spi, pcie_addr, size, buf);
  42. if (ret) {
  43. printf("%s: spi_flash read error.\n", __func__);
  44. spi_flash_free(spi);
  45. return 1;
  46. }
  47. spi_flash_free(spi);
  48. return 0;
  49. #else
  50. printf("No SPI support so no PCIe support\n");
  51. return 1;
  52. #endif
  53. }
  54. static void init_pcie_bridge(void)
  55. {
  56. struct pciebrg_regs *pciebrg = PCIEBRG_BASE;
  57. struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
  58. int i;
  59. unsigned char *data;
  60. unsigned short tmp;
  61. unsigned long pcie_size;
  62. if (!(readw(&pciebrg->ctrl_h8s) & 0x0001))
  63. return;
  64. if (is_sh7757_b0())
  65. pcie_size = SH7757LCR_PCIEBRG_SIZE_B0;
  66. else
  67. pcie_size = SH7757LCR_PCIEBRG_SIZE;
  68. data = malloc(pcie_size);
  69. if (!data) {
  70. printf("%s: malloc error.\n", __func__);
  71. return;
  72. }
  73. if (init_pcie_bridge_from_spi(data, pcie_size)) {
  74. free(data);
  75. return;
  76. }
  77. if (data[0] == 0xff && data[1] == 0xff && data[2] == 0xff &&
  78. data[3] == 0xff) {
  79. free(data);
  80. printf("%s: skipped initialization\n", __func__);
  81. return;
  82. }
  83. writew(0xa501, &pciebrg->ctrl_h8s); /* reset */
  84. writew(0x0000, &pciebrg->cp_ctrl);
  85. writew(0x0000, &pciebrg->cp_addr);
  86. for (i = 0; i < pcie_size; i += 2) {
  87. tmp = (data[i] << 8) | data[i + 1];
  88. writew(tmp, &pciebrg->cp_data);
  89. }
  90. writew(0xa500, &pciebrg->ctrl_h8s); /* start */
  91. if (!is_sh7757_b0())
  92. writel(0x00000001, &pcie_setup->pbictl3);
  93. free(data);
  94. }
  95. static void init_usb_phy(void)
  96. {
  97. struct usb_common_regs *common0 = USB0_COMMON_BASE;
  98. struct usb_common_regs *common1 = USB1_COMMON_BASE;
  99. struct usb0_phy_regs *phy = USB0_PHY_BASE;
  100. struct usb1_port_regs *port = USB1_PORT_BASE;
  101. struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
  102. writew(0x0100, &phy->reset); /* set reset */
  103. /* port0 = USB0, port1 = USB1 */
  104. writew(0x0002, &phy->portsel);
  105. writel(0x0001, &port->port1sel); /* port1 = Host */
  106. writew(0x0111, &phy->reset); /* clear reset */
  107. writew(0x4000, &common0->suspmode);
  108. writew(0x4000, &common1->suspmode);
  109. #if defined(__LITTLE_ENDIAN)
  110. writel(0x00000000, &align->ehcidatac);
  111. writel(0x00000000, &align->ohcidatac);
  112. #endif
  113. }
  114. static void set_mac_to_sh_eth_register(int channel, char *mac_string)
  115. {
  116. struct ether_mac_regs *ether;
  117. unsigned char mac[6];
  118. unsigned long val;
  119. eth_parse_enetaddr(mac_string, mac);
  120. if (!channel)
  121. ether = ETHER0_MAC_BASE;
  122. else
  123. ether = ETHER1_MAC_BASE;
  124. val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
  125. writel(val, &ether->mahr);
  126. val = (mac[4] << 8) | mac[5];
  127. writel(val, &ether->malr);
  128. }
  129. static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
  130. {
  131. struct ether_mac_regs *ether;
  132. unsigned char mac[6];
  133. unsigned long val;
  134. eth_parse_enetaddr(mac_string, mac);
  135. if (!channel)
  136. ether = GETHER0_MAC_BASE;
  137. else
  138. ether = GETHER1_MAC_BASE;
  139. val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
  140. writel(val, &ether->mahr);
  141. val = (mac[4] << 8) | mac[5];
  142. writel(val, &ether->malr);
  143. }
  144. /*****************************************************************
  145. * This PMB must be set on this timing. The lowlevel_init is run on
  146. * Area 0(phys 0x00000000), so we have to map it.
  147. *
  148. * The new PMB table is following:
  149. * ent virt phys v sz c wt
  150. * 0 0xa0000000 0x40000000 1 128M 0 1
  151. * 1 0xa8000000 0x48000000 1 128M 0 1
  152. * 2 0xb0000000 0x50000000 1 128M 0 1
  153. * 3 0xb8000000 0x58000000 1 128M 0 1
  154. * 4 0x80000000 0x40000000 1 128M 1 1
  155. * 5 0x88000000 0x48000000 1 128M 1 1
  156. * 6 0x90000000 0x50000000 1 128M 1 1
  157. * 7 0x98000000 0x58000000 1 128M 1 1
  158. */
  159. static void set_pmb_on_board_init(void)
  160. {
  161. struct mmu_regs *mmu = MMU_BASE;
  162. /* clear ITLB */
  163. writel(0x00000004, &mmu->mmucr);
  164. /* delete PMB for SPIBOOT */
  165. writel(0, PMB_ADDR_BASE(0));
  166. writel(0, PMB_DATA_BASE(0));
  167. /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
  168. /* ppn ub v s1 s0 c wt */
  169. writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
  170. writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
  171. writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
  172. writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
  173. writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
  174. writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
  175. writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
  176. writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
  177. writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
  178. writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
  179. writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
  180. writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
  181. }
  182. int board_init(void)
  183. {
  184. struct gether_control_regs *gether = GETHER_CONTROL_BASE;
  185. set_pmb_on_board_init();
  186. /* enable RMII's MDIO (disable GRMII's MDIO) */
  187. writel(0x00030000, &gether->gbecont);
  188. init_gctrl();
  189. init_usb_phy();
  190. return 0;
  191. }
  192. int board_mmc_init(bd_t *bis)
  193. {
  194. return mmcif_mmc_init();
  195. }
  196. static int get_sh_eth_mac_raw(unsigned char *buf, int size)
  197. {
  198. #ifdef CONFIG_DEPRECATED
  199. struct spi_flash *spi;
  200. int ret;
  201. spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
  202. if (spi == NULL) {
  203. printf("%s: spi_flash probe error.\n", __func__);
  204. return 1;
  205. }
  206. ret = spi_flash_read(spi, SH7757LCR_ETHERNET_MAC_BASE, size, buf);
  207. if (ret) {
  208. printf("%s: spi_flash read error.\n", __func__);
  209. spi_flash_free(spi);
  210. return 1;
  211. }
  212. spi_flash_free(spi);
  213. #endif
  214. return 0;
  215. }
  216. static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
  217. {
  218. memcpy(mac_string, &buf[channel * (SH7757LCR_ETHERNET_MAC_SIZE + 1)],
  219. SH7757LCR_ETHERNET_MAC_SIZE);
  220. mac_string[SH7757LCR_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
  221. return 0;
  222. }
  223. static void init_ethernet_mac(void)
  224. {
  225. char mac_string[64];
  226. char env_string[64];
  227. int i;
  228. unsigned char *buf;
  229. buf = malloc(256);
  230. if (!buf) {
  231. printf("%s: malloc error.\n", __func__);
  232. return;
  233. }
  234. get_sh_eth_mac_raw(buf, 256);
  235. /* Fast Ethernet */
  236. for (i = 0; i < SH7757LCR_ETHERNET_NUM_CH; i++) {
  237. get_sh_eth_mac(i, mac_string, buf);
  238. if (i == 0)
  239. env_set("ethaddr", mac_string);
  240. else {
  241. sprintf(env_string, "eth%daddr", i);
  242. env_set(env_string, mac_string);
  243. }
  244. set_mac_to_sh_eth_register(i, mac_string);
  245. }
  246. /* Gigabit Ethernet */
  247. for (i = 0; i < SH7757LCR_GIGA_ETHERNET_NUM_CH; i++) {
  248. get_sh_eth_mac(i + SH7757LCR_ETHERNET_NUM_CH, mac_string, buf);
  249. sprintf(env_string, "eth%daddr", i + SH7757LCR_ETHERNET_NUM_CH);
  250. env_set(env_string, mac_string);
  251. set_mac_to_sh_giga_eth_register(i, mac_string);
  252. }
  253. free(buf);
  254. }
  255. static void init_pcie(void)
  256. {
  257. struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
  258. struct pcie_system_bus_regs *pcie_sysbus = PCIE_SYSTEM_BUS_BASE;
  259. writel(0x00000ff2, &pcie_setup->ladmsk0);
  260. writel(0x00000001, &pcie_setup->barmap);
  261. writel(0xffcaa000, &pcie_setup->lad0);
  262. writel(0x00030000, &pcie_sysbus->endictl0);
  263. writel(0x00000003, &pcie_sysbus->endictl1);
  264. writel(0x00000004, &pcie_setup->pbictl2);
  265. }
  266. static void finish_spiboot(void)
  267. {
  268. struct gctrl_regs *gctrl = GCTRL_BASE;
  269. /*
  270. * SH7757 B0 does not use LBSC.
  271. * So if we set SPIBOOTCAN to 1, SH7757 can not access Area0.
  272. * This setting is not cleared by manual reset, So we have to set it
  273. * to 0.
  274. */
  275. writel(0x00000000, &gctrl->spibootcan);
  276. }
  277. int board_late_init(void)
  278. {
  279. init_ethernet_mac();
  280. init_pcie_bridge();
  281. init_pcie();
  282. finish_spiboot();
  283. return 0;
  284. }
  285. int do_sh_g200(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  286. {
  287. struct gctrl_regs *gctrl = GCTRL_BASE;
  288. unsigned long graofst;
  289. writel(0xfedcba98, &gctrl->wprotect);
  290. graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
  291. writel(graofst | 0xa0000f00, &gctrl->gracr3);
  292. return 0;
  293. }
  294. U_BOOT_CMD(
  295. sh_g200, 1, 1, do_sh_g200,
  296. "enable sh-g200",
  297. "enable SH-G200 bus (disable PCIe-G200)"
  298. );
  299. #ifdef CONFIG_DEPRECATED
  300. int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  301. {
  302. int i, ret;
  303. char mac_string[256];
  304. struct spi_flash *spi;
  305. unsigned char *buf;
  306. if (argc != 5) {
  307. buf = malloc(256);
  308. if (!buf) {
  309. printf("%s: malloc error.\n", __func__);
  310. return 1;
  311. }
  312. get_sh_eth_mac_raw(buf, 256);
  313. /* print current MAC address */
  314. for (i = 0; i < 4; i++) {
  315. get_sh_eth_mac(i, mac_string, buf);
  316. if (i < 2)
  317. printf(" ETHERC ch%d = %s\n", i, mac_string);
  318. else
  319. printf("GETHERC ch%d = %s\n", i-2, mac_string);
  320. }
  321. free(buf);
  322. return 0;
  323. }
  324. /* new setting */
  325. memset(mac_string, 0xff, sizeof(mac_string));
  326. sprintf(mac_string, "%s\t%s\t%s\t%s",
  327. argv[1], argv[2], argv[3], argv[4]);
  328. /* write MAC data to SPI rom */
  329. spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
  330. if (!spi) {
  331. printf("%s: spi_flash probe error.\n", __func__);
  332. return 1;
  333. }
  334. ret = spi_flash_erase(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
  335. SH7757LCR_SPI_SECTOR_SIZE);
  336. if (ret) {
  337. printf("%s: spi_flash erase error.\n", __func__);
  338. return 1;
  339. }
  340. ret = spi_flash_write(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
  341. sizeof(mac_string), mac_string);
  342. if (ret) {
  343. printf("%s: spi_flash write error.\n", __func__);
  344. spi_flash_free(spi);
  345. return 1;
  346. }
  347. spi_flash_free(spi);
  348. puts("The writing of the MAC address to SPI ROM was completed.\n");
  349. return 0;
  350. }
  351. U_BOOT_CMD(
  352. write_mac, 5, 1, do_write_mac,
  353. "write MAC address for ETHERC/GETHERC",
  354. "[ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1]\n"
  355. );
  356. #endif