board.c 6.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board.c
  4. *
  5. * Board functions for Phytec phyCORE-AM335x (pcm051) based boards
  6. *
  7. * Copyright (C) 2013 Lemonage Software GmbH
  8. * Author Lars Poeschel <poeschel@lemonage.de>
  9. */
  10. #include <common.h>
  11. #include <env.h>
  12. #include <environment.h>
  13. #include <errno.h>
  14. #include <spl.h>
  15. #include <asm/arch/cpu.h>
  16. #include <asm/arch/hardware.h>
  17. #include <asm/arch/omap.h>
  18. #include <asm/arch/ddr_defs.h>
  19. #include <asm/arch/clock.h>
  20. #include <asm/arch/gpio.h>
  21. #include <asm/arch/mmc_host_def.h>
  22. #include <asm/arch/sys_proto.h>
  23. #include <asm/io.h>
  24. #include <asm/emif.h>
  25. #include <asm/gpio.h>
  26. #include <i2c.h>
  27. #include <miiphy.h>
  28. #include <cpsw.h>
  29. #include "board.h"
  30. DECLARE_GLOBAL_DATA_PTR;
  31. /* MII mode defines */
  32. #define RMII_RGMII2_MODE_ENABLE 0x49
  33. static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  34. #ifdef CONFIG_SPL_BUILD
  35. /* DDR RAM defines */
  36. #define DDR_CLK_MHZ 303 /* DDR_DPLL_MULT value */
  37. #define OSC (V_OSCK/1000000)
  38. const struct dpll_params dpll_ddr = {
  39. DDR_CLK_MHZ, OSC-1, 1, -1, -1, -1, -1};
  40. const struct dpll_params *get_dpll_ddr_params(void)
  41. {
  42. return &dpll_ddr;
  43. }
  44. #ifdef CONFIG_REV1
  45. const struct ctrl_ioregs ioregs = {
  46. .cm0ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
  47. .cm1ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
  48. .cm2ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
  49. .dt0ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
  50. .dt1ioctl = MT41J256M8HX15E_IOCTRL_VALUE,
  51. };
  52. static const struct ddr_data ddr3_data = {
  53. .datardsratio0 = MT41J256M8HX15E_RD_DQS,
  54. .datawdsratio0 = MT41J256M8HX15E_WR_DQS,
  55. .datafwsratio0 = MT41J256M8HX15E_PHY_FIFO_WE,
  56. .datawrsratio0 = MT41J256M8HX15E_PHY_WR_DATA,
  57. };
  58. static const struct cmd_control ddr3_cmd_ctrl_data = {
  59. .cmd0csratio = MT41J256M8HX15E_RATIO,
  60. .cmd0iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
  61. .cmd1csratio = MT41J256M8HX15E_RATIO,
  62. .cmd1iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
  63. .cmd2csratio = MT41J256M8HX15E_RATIO,
  64. .cmd2iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
  65. };
  66. static struct emif_regs ddr3_emif_reg_data = {
  67. .sdram_config = MT41J256M8HX15E_EMIF_SDCFG,
  68. .ref_ctrl = MT41J256M8HX15E_EMIF_SDREF,
  69. .sdram_tim1 = MT41J256M8HX15E_EMIF_TIM1,
  70. .sdram_tim2 = MT41J256M8HX15E_EMIF_TIM2,
  71. .sdram_tim3 = MT41J256M8HX15E_EMIF_TIM3,
  72. .zq_config = MT41J256M8HX15E_ZQ_CFG,
  73. .emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY |
  74. PHY_EN_DYN_PWRDN,
  75. };
  76. void sdram_init(void)
  77. {
  78. config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data,
  79. &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
  80. }
  81. #else
  82. const struct ctrl_ioregs ioregs = {
  83. .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  84. .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  85. .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  86. .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  87. .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  88. };
  89. static const struct ddr_data ddr3_data = {
  90. .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  91. .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  92. .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  93. .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  94. };
  95. static const struct cmd_control ddr3_cmd_ctrl_data = {
  96. .cmd0csratio = MT41K256M16HA125E_RATIO,
  97. .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  98. .cmd1csratio = MT41K256M16HA125E_RATIO,
  99. .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  100. .cmd2csratio = MT41K256M16HA125E_RATIO,
  101. .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  102. };
  103. static struct emif_regs ddr3_emif_reg_data = {
  104. .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  105. .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  106. .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  107. .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  108. .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  109. .zq_config = MT41K256M16HA125E_ZQ_CFG,
  110. .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY |
  111. PHY_EN_DYN_PWRDN,
  112. };
  113. void sdram_init(void)
  114. {
  115. config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data,
  116. &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
  117. }
  118. #endif
  119. void set_uart_mux_conf(void)
  120. {
  121. enable_uart0_pin_mux();
  122. }
  123. void set_mux_conf_regs(void)
  124. {
  125. /* Initalize the board header */
  126. enable_i2c0_pin_mux();
  127. i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
  128. enable_board_pin_mux();
  129. }
  130. #endif
  131. /*
  132. * Basic board specific setup. Pinmux has been handled already.
  133. */
  134. int board_init(void)
  135. {
  136. i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
  137. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  138. return 0;
  139. }
  140. #ifdef CONFIG_DRIVER_TI_CPSW
  141. static void cpsw_control(int enabled)
  142. {
  143. /* VTP can be added here */
  144. return;
  145. }
  146. static struct cpsw_slave_data cpsw_slaves[] = {
  147. {
  148. .slave_reg_ofs = 0x208,
  149. .sliver_reg_ofs = 0xd80,
  150. .phy_addr = 0,
  151. .phy_if = PHY_INTERFACE_MODE_RGMII,
  152. },
  153. {
  154. .slave_reg_ofs = 0x308,
  155. .sliver_reg_ofs = 0xdc0,
  156. .phy_addr = 1,
  157. .phy_if = PHY_INTERFACE_MODE_RGMII,
  158. },
  159. };
  160. static struct cpsw_platform_data cpsw_data = {
  161. .mdio_base = CPSW_MDIO_BASE,
  162. .cpsw_base = CPSW_BASE,
  163. .mdio_div = 0xff,
  164. .channels = 8,
  165. .cpdma_reg_ofs = 0x800,
  166. .slaves = 1,
  167. .slave_data = cpsw_slaves,
  168. .ale_reg_ofs = 0xd00,
  169. .ale_entries = 1024,
  170. .host_port_reg_ofs = 0x108,
  171. .hw_stats_reg_ofs = 0x900,
  172. .bd_ram_ofs = 0x2000,
  173. .mac_control = (1 << 5),
  174. .control = cpsw_control,
  175. .host_port_num = 0,
  176. .version = CPSW_CTRL_VERSION_2,
  177. };
  178. #endif
  179. #if defined(CONFIG_DRIVER_TI_CPSW) || \
  180. (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
  181. int board_eth_init(bd_t *bis)
  182. {
  183. int rv, n = 0;
  184. #ifdef CONFIG_DRIVER_TI_CPSW
  185. uint8_t mac_addr[6];
  186. uint32_t mac_hi, mac_lo;
  187. if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
  188. printf("<ethaddr> not set. Reading from E-fuse\n");
  189. /* try reading mac address from efuse */
  190. mac_lo = readl(&cdev->macid0l);
  191. mac_hi = readl(&cdev->macid0h);
  192. mac_addr[0] = mac_hi & 0xFF;
  193. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  194. mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  195. mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  196. mac_addr[4] = mac_lo & 0xFF;
  197. mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  198. if (is_valid_ethaddr(mac_addr))
  199. eth_env_set_enetaddr("ethaddr", mac_addr);
  200. else
  201. goto try_usbether;
  202. }
  203. writel(RMII_RGMII2_MODE_ENABLE, &cdev->miisel);
  204. rv = cpsw_register(&cpsw_data);
  205. if (rv < 0)
  206. printf("Error %d registering CPSW switch\n", rv);
  207. else
  208. n += rv;
  209. try_usbether:
  210. #endif
  211. #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_SPL_BUILD)
  212. rv = usb_eth_initialize(bis);
  213. if (rv < 0)
  214. printf("Error %d registering USB_ETHER\n", rv);
  215. else
  216. n += rv;
  217. #endif
  218. return n;
  219. }
  220. #endif