kp_imx6q_tpc.c 6.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * K+P iMX6Q KP_IMX6Q_TPC board configuration
  4. *
  5. * Copyright (C) 2018 Lukasz Majewski <lukma@denx.de>
  6. */
  7. #include <common.h>
  8. #include <asm/arch/clock.h>
  9. #include <asm/arch/crm_regs.h>
  10. #include <asm/arch/imx-regs.h>
  11. #include <asm/arch/iomux.h>
  12. #include <asm/arch/mx6-pins.h>
  13. #include <asm/arch/sys_proto.h>
  14. #include <asm/gpio.h>
  15. #include <asm/io.h>
  16. #include <asm/mach-imx/boot_mode.h>
  17. #include <asm/mach-imx/iomux-v3.h>
  18. #include <asm/mach-imx/mxc_i2c.h>
  19. #include <env.h>
  20. #include <errno.h>
  21. #include <fsl_esdhc_imx.h>
  22. #include <fuse.h>
  23. #include <i2c.h>
  24. #include <miiphy.h>
  25. #include <mmc.h>
  26. #include <net.h>
  27. #include <netdev.h>
  28. #include <usb.h>
  29. #include <usb/ehci-ci.h>
  30. DECLARE_GLOBAL_DATA_PTR;
  31. #define ENET_PAD_CTRL \
  32. (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  33. PAD_CTL_HYS)
  34. #define I2C_PAD_CTRL \
  35. (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  36. PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  37. #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  38. static struct i2c_pads_info kp_imx6q_tpc_i2c_pad_info0 = {
  39. .scl = {
  40. .i2c_mode = MX6Q_PAD_CSI0_DAT9__I2C1_SCL | PC,
  41. .gpio_mode = MX6Q_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
  42. .gp = IMX_GPIO_NR(5, 27)
  43. },
  44. .sda = {
  45. .i2c_mode = MX6Q_PAD_CSI0_DAT8__I2C1_SDA | PC,
  46. .gpio_mode = MX6Q_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
  47. .gp = IMX_GPIO_NR(5, 26)
  48. }
  49. };
  50. static struct i2c_pads_info kp_imx6q_tpc_i2c_pad_info1 = {
  51. .scl = {
  52. .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
  53. .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
  54. .gp = IMX_GPIO_NR(4, 12)
  55. },
  56. .sda = {
  57. .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
  58. .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
  59. .gp = IMX_GPIO_NR(4, 13)
  60. }
  61. };
  62. int dram_init(void)
  63. {
  64. gd->ram_size = imx_ddr_size();
  65. return 0;
  66. }
  67. /*
  68. * Do not overwrite the console
  69. * Use always serial for U-Boot console
  70. */
  71. int overwrite_console(void)
  72. {
  73. return 1;
  74. }
  75. #ifdef CONFIG_FEC_MXC
  76. static iomux_v3_cfg_t const enet_pads[] = {
  77. IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  78. IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  79. IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  80. IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  81. IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  82. IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  83. IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  84. IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
  85. MUX_PAD_CTRL(ENET_PAD_CTRL)),
  86. IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  87. IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  88. IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  89. IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  90. IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  91. IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  92. IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
  93. MUX_PAD_CTRL(ENET_PAD_CTRL)),
  94. /* AR8031 PHY Reset */
  95. IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  96. };
  97. static void eth_phy_reset(void)
  98. {
  99. /* Reset AR8031 PHY */
  100. gpio_direction_output(IMX_GPIO_NR(1, 25), 0);
  101. mdelay(10);
  102. gpio_set_value(IMX_GPIO_NR(1, 25), 1);
  103. udelay(100);
  104. }
  105. static int setup_fec_clock(void)
  106. {
  107. struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  108. /* set gpr1[21] to select anatop clock */
  109. clrsetbits_le32(&iomuxc_regs->gpr[1], 0x1 << 21, 0x1 << 21);
  110. return enable_fec_anatop_clock(0, ENET_50MHZ);
  111. }
  112. int board_eth_init(bd_t *bis)
  113. {
  114. SETUP_IOMUX_PADS(enet_pads);
  115. setup_fec_clock();
  116. eth_phy_reset();
  117. return cpu_eth_init(bis);
  118. }
  119. static int ar8031_phy_fixup(struct phy_device *phydev)
  120. {
  121. unsigned short val;
  122. /* To enable AR8031 output a 125MHz clk from CLK_25M */
  123. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
  124. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
  125. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
  126. val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
  127. val &= 0xffe3;
  128. val |= 0x18;
  129. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
  130. /* introduce tx clock delay */
  131. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
  132. val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
  133. val |= 0x0100;
  134. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
  135. return 0;
  136. }
  137. int board_phy_config(struct phy_device *phydev)
  138. {
  139. ar8031_phy_fixup(phydev);
  140. if (phydev->drv->config)
  141. phydev->drv->config(phydev);
  142. return 0;
  143. }
  144. #endif
  145. #ifdef CONFIG_FSL_ESDHC_IMX
  146. #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
  147. static struct fsl_esdhc_cfg usdhc_cfg[] = {
  148. { USDHC2_BASE_ADDR },
  149. { USDHC4_BASE_ADDR },
  150. };
  151. int board_mmc_getcd(struct mmc *mmc)
  152. {
  153. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  154. switch (cfg->esdhc_base) {
  155. case USDHC2_BASE_ADDR:
  156. return !gpio_get_value(USDHC2_CD_GPIO);
  157. case USDHC4_BASE_ADDR:
  158. return 1; /* eMMC/uSDHC4 is always present */
  159. }
  160. return 0;
  161. }
  162. int board_mmc_init(bd_t *bis)
  163. {
  164. int i, ret;
  165. /*
  166. * According to the board_mmc_init() the following map is done:
  167. * (U-Boot device node) (Physical Port)
  168. * mmc0 micro SD
  169. * mmc2 eMMC
  170. */
  171. gpio_direction_input(USDHC2_CD_GPIO);
  172. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  173. usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
  174. for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  175. ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  176. if (ret)
  177. return ret;
  178. }
  179. return 0;
  180. }
  181. #endif
  182. #ifdef CONFIG_USB_EHCI_MX6
  183. static void setup_usb(void)
  184. {
  185. /*
  186. * Set daisy chain for otg_pin_id on MX6Q.
  187. * For MX6DL, this bit is reserved.
  188. */
  189. imx_iomux_set_gpr_register(1, 13, 1, 0);
  190. }
  191. int board_usb_phy_mode(int port)
  192. {
  193. if (port == 1)
  194. return USB_INIT_HOST;
  195. else
  196. return USB_INIT_DEVICE;
  197. }
  198. int board_ehci_power(int port, int on)
  199. {
  200. switch (port) {
  201. case 0:
  202. break;
  203. case 1:
  204. gpio_direction_output(IMX_GPIO_NR(3, 31), !!on);
  205. break;
  206. default:
  207. printf("MXC USB port %d not yet supported\n", port);
  208. return -EINVAL;
  209. }
  210. return 0;
  211. }
  212. #endif
  213. int board_early_init_f(void)
  214. {
  215. #ifdef CONFIG_USB_EHCI_MX6
  216. setup_usb();
  217. #endif
  218. return 0;
  219. }
  220. int board_init(void)
  221. {
  222. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  223. /* address of boot parameters */
  224. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  225. /* Enable eim_slow clocks */
  226. setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET);
  227. setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &kp_imx6q_tpc_i2c_pad_info0);
  228. setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &kp_imx6q_tpc_i2c_pad_info1);
  229. return 0;
  230. }
  231. #ifdef CONFIG_CMD_BMODE
  232. static const struct boot_mode board_boot_modes[] = {
  233. /* 4 bit bus width */
  234. {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  235. /* 8 bit bus width */
  236. {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
  237. {NULL, 0},
  238. };
  239. #endif
  240. int board_late_init(void)
  241. {
  242. #ifdef CONFIG_CMD_BMODE
  243. add_board_boot_modes(board_boot_modes);
  244. #endif
  245. env_set("boardname", "kp-tpc");
  246. env_set("boardsoc", "imx6q");
  247. return 0;
  248. }
  249. int checkboard(void)
  250. {
  251. puts("Board: K+P KP_IMX6Q_TPC i.MX6Q\n");
  252. return 0;
  253. }