imx8mq_evk.c 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2018 NXP
  4. */
  5. #include <common.h>
  6. #include <env.h>
  7. #include <malloc.h>
  8. #include <errno.h>
  9. #include <asm/io.h>
  10. #include <miiphy.h>
  11. #include <netdev.h>
  12. #include <asm/mach-imx/iomux-v3.h>
  13. #include <asm-generic/gpio.h>
  14. #include <fsl_esdhc_imx.h>
  15. #include <mmc.h>
  16. #include <asm/arch/imx8mq_pins.h>
  17. #include <asm/arch/sys_proto.h>
  18. #include <asm/mach-imx/gpio.h>
  19. #include <asm/mach-imx/mxc_i2c.h>
  20. #include <asm/arch/clock.h>
  21. #include <spl.h>
  22. #include <power/pmic.h>
  23. #include <power/pfuze100_pmic.h>
  24. #include "../common/pfuze.h"
  25. DECLARE_GLOBAL_DATA_PTR;
  26. #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
  27. #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
  28. static iomux_v3_cfg_t const wdog_pads[] = {
  29. IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  30. };
  31. static iomux_v3_cfg_t const uart_pads[] = {
  32. IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  33. IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  34. };
  35. int board_early_init_f(void)
  36. {
  37. struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  38. imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  39. set_wdog_reset(wdog);
  40. imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  41. return 0;
  42. }
  43. int dram_init(void)
  44. {
  45. /* rom_pointer[1] contains the size of TEE occupies */
  46. if (rom_pointer[1])
  47. gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
  48. else
  49. gd->ram_size = PHYS_SDRAM_SIZE;
  50. return 0;
  51. }
  52. #ifdef CONFIG_FEC_MXC
  53. #define FEC_RST_PAD IMX_GPIO_NR(1, 9)
  54. static iomux_v3_cfg_t const fec1_rst_pads[] = {
  55. IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
  56. };
  57. static void setup_iomux_fec(void)
  58. {
  59. imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
  60. ARRAY_SIZE(fec1_rst_pads));
  61. gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst");
  62. gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
  63. udelay(500);
  64. gpio_direction_output(IMX_GPIO_NR(1, 9), 1);
  65. }
  66. static int setup_fec(void)
  67. {
  68. struct iomuxc_gpr_base_regs *gpr =
  69. (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  70. setup_iomux_fec();
  71. /* Use 125M anatop REF_CLK1 for ENET1, not from external */
  72. clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
  73. return set_clk_enet(ENET_125MHZ);
  74. }
  75. int board_phy_config(struct phy_device *phydev)
  76. {
  77. /* enable rgmii rxc skew and phy mode select to RGMII copper */
  78. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
  79. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
  80. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
  81. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
  82. if (phydev->drv->config)
  83. phydev->drv->config(phydev);
  84. return 0;
  85. }
  86. #endif
  87. int board_init(void)
  88. {
  89. #ifdef CONFIG_FEC_MXC
  90. setup_fec();
  91. #endif
  92. return 0;
  93. }
  94. int board_mmc_get_env_dev(int devno)
  95. {
  96. return devno;
  97. }
  98. int board_late_init(void)
  99. {
  100. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  101. env_set("board_name", "EVK");
  102. env_set("board_rev", "iMX8MQ");
  103. #endif
  104. return 0;
  105. }