cgtqmx6eval.c 29 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
  4. * Based on mx6qsabrelite.c file
  5. * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
  6. * Leo Sartre, <lsartre@adeneo-embedded.com>
  7. */
  8. #include <common.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch/imx-regs.h>
  12. #include <asm/arch/iomux.h>
  13. #include <asm/arch/mx6-pins.h>
  14. #include <asm/gpio.h>
  15. #include <asm/mach-imx/iomux-v3.h>
  16. #include <asm/mach-imx/sata.h>
  17. #include <asm/mach-imx/boot_mode.h>
  18. #include <asm/mach-imx/mxc_i2c.h>
  19. #include <asm/arch/sys_proto.h>
  20. #include <asm/arch/mxc_hdmi.h>
  21. #include <asm/arch/crm_regs.h>
  22. #include <env.h>
  23. #include <mmc.h>
  24. #include <fsl_esdhc_imx.h>
  25. #include <i2c.h>
  26. #include <input.h>
  27. #include <power/pmic.h>
  28. #include <power/pfuze100_pmic.h>
  29. #include <linux/fb.h>
  30. #include <ipu_pixfmt.h>
  31. #include <malloc.h>
  32. #include <miiphy.h>
  33. #include <netdev.h>
  34. #include <micrel.h>
  35. #include <spi_flash.h>
  36. #include <spi.h>
  37. DECLARE_GLOBAL_DATA_PTR;
  38. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |\
  39. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  40. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\
  41. PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  42. #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  43. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  44. PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  45. PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  46. #define SPI_PAD_CTRL (PAD_CTL_HYS | \
  47. PAD_CTL_SPEED_MED | \
  48. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  49. #define MX6Q_QMX6_PFUZE_MUX IMX_GPIO_NR(6, 9)
  50. #define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  51. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  52. PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  53. int dram_init(void)
  54. {
  55. gd->ram_size = imx_ddr_size();
  56. return 0;
  57. }
  58. static iomux_v3_cfg_t const uart2_pads[] = {
  59. IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  60. IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  61. };
  62. #ifndef CONFIG_SPL_BUILD
  63. static iomux_v3_cfg_t const usdhc2_pads[] = {
  64. IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  65. IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  66. IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  67. IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  68. IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  69. IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  70. IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  71. };
  72. static iomux_v3_cfg_t const usdhc3_pads[] = {
  73. IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  74. IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  75. IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  76. IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  77. IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  78. IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  79. IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  80. IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  81. IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  82. IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  83. IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  84. };
  85. #endif
  86. static iomux_v3_cfg_t const usdhc4_pads[] = {
  87. IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  88. IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  89. IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  90. IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  91. IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  92. IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  93. IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  94. IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  95. IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  96. IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  97. IOMUX_PADS(PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  98. };
  99. static iomux_v3_cfg_t const usb_otg_pads[] = {
  100. IOMUX_PADS(PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)),
  101. IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
  102. };
  103. static iomux_v3_cfg_t enet_pads_ksz9031[] = {
  104. IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  105. IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  106. IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  107. IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  108. IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  109. IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  110. IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  111. IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  112. IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  113. IOMUX_PADS(PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  114. IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  115. IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  116. IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  117. IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  118. IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  119. };
  120. static iomux_v3_cfg_t enet_pads_final_ksz9031[] = {
  121. IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  122. IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  123. IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  124. IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  125. IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  126. IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  127. };
  128. static iomux_v3_cfg_t enet_pads_ar8035[] = {
  129. IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  130. IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  131. IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  132. IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  133. IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  134. IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  135. IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  136. IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  137. IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  138. IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  139. IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  140. IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  141. IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  142. IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  143. IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  144. };
  145. static iomux_v3_cfg_t const ecspi1_pads[] = {
  146. IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  147. IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  148. IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  149. IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  150. };
  151. #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  152. struct i2c_pads_info mx6q_i2c_pad_info1 = {
  153. .scl = {
  154. .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
  155. .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
  156. .gp = IMX_GPIO_NR(4, 12)
  157. },
  158. .sda = {
  159. .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
  160. .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
  161. .gp = IMX_GPIO_NR(4, 13)
  162. }
  163. };
  164. struct i2c_pads_info mx6dl_i2c_pad_info1 = {
  165. .scl = {
  166. .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
  167. .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
  168. .gp = IMX_GPIO_NR(4, 12)
  169. },
  170. .sda = {
  171. .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
  172. .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
  173. .gp = IMX_GPIO_NR(4, 13)
  174. }
  175. };
  176. #define I2C_PMIC 1 /* I2C2 port is used to connect to the PMIC */
  177. struct interface_level {
  178. char *name;
  179. uchar value;
  180. };
  181. static struct interface_level mipi_levels[] = {
  182. {"0V0", 0x00},
  183. {"2V5", 0x17},
  184. };
  185. /* setup board specific PMIC */
  186. int power_init_board(void)
  187. {
  188. struct pmic *p;
  189. u32 id1, id2, i;
  190. int ret;
  191. char const *lv_mipi;
  192. /* configure I2C multiplexer */
  193. gpio_direction_output(MX6Q_QMX6_PFUZE_MUX, 1);
  194. power_pfuze100_init(I2C_PMIC);
  195. p = pmic_get("PFUZE100");
  196. if (!p)
  197. return -EINVAL;
  198. ret = pmic_probe(p);
  199. if (ret)
  200. return ret;
  201. pmic_reg_read(p, PFUZE100_DEVICEID, &id1);
  202. pmic_reg_read(p, PFUZE100_REVID, &id2);
  203. printf("PFUZE100 Rev. [%02x/%02x] detected\n", id1, id2);
  204. if (id2 >= 0x20)
  205. return 0;
  206. /* set level of MIPI if specified */
  207. lv_mipi = env_get("lv_mipi");
  208. if (lv_mipi)
  209. return 0;
  210. for (i = 0; i < ARRAY_SIZE(mipi_levels); i++) {
  211. if (!strcmp(mipi_levels[i].name, lv_mipi)) {
  212. printf("set MIPI level %s\n", mipi_levels[i].name);
  213. ret = pmic_reg_write(p, PFUZE100_VGEN4VOL,
  214. mipi_levels[i].value);
  215. if (ret)
  216. return ret;
  217. }
  218. }
  219. return 0;
  220. }
  221. int board_eth_init(bd_t *bis)
  222. {
  223. struct phy_device *phydev;
  224. struct mii_dev *bus;
  225. unsigned short id1, id2;
  226. int ret;
  227. /* check whether KSZ9031 or AR8035 has to be configured */
  228. SETUP_IOMUX_PADS(enet_pads_ar8035);
  229. /* phy reset */
  230. gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
  231. udelay(2000);
  232. gpio_set_value(IMX_GPIO_NR(3, 23), 1);
  233. udelay(500);
  234. bus = fec_get_miibus(IMX_FEC_BASE, -1);
  235. if (!bus)
  236. return -EINVAL;
  237. phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
  238. if (!phydev) {
  239. printf("Error: phy device not found.\n");
  240. ret = -ENODEV;
  241. goto free_bus;
  242. }
  243. /* get the PHY id */
  244. id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2);
  245. id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3);
  246. if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) {
  247. /* re-configure for Micrel KSZ9031 */
  248. printf("configure Micrel KSZ9031 Ethernet Phy at address %d\n",
  249. phydev->addr);
  250. /* phy reset: gpio3-23 */
  251. gpio_set_value(IMX_GPIO_NR(3, 23), 0);
  252. gpio_set_value(IMX_GPIO_NR(6, 30), (phydev->addr >> 2));
  253. gpio_set_value(IMX_GPIO_NR(6, 25), 1);
  254. gpio_set_value(IMX_GPIO_NR(6, 27), 1);
  255. gpio_set_value(IMX_GPIO_NR(6, 28), 1);
  256. gpio_set_value(IMX_GPIO_NR(6, 29), 1);
  257. SETUP_IOMUX_PADS(enet_pads_ksz9031);
  258. gpio_set_value(IMX_GPIO_NR(6, 24), 1);
  259. udelay(500);
  260. gpio_set_value(IMX_GPIO_NR(3, 23), 1);
  261. SETUP_IOMUX_PADS(enet_pads_final_ksz9031);
  262. } else if ((id1 == 0x004d) && (id2 == 0xd072)) {
  263. /* configure Atheros AR8035 - actually nothing to do */
  264. printf("configure Atheros AR8035 Ethernet Phy at address %d\n",
  265. phydev->addr);
  266. } else {
  267. printf("Unknown Ethernet-Phy: 0x%04x 0x%04x\n", id1, id2);
  268. ret = -EINVAL;
  269. goto free_phydev;
  270. }
  271. ret = fec_probe(bis, -1, IMX_FEC_BASE, bus, phydev);
  272. if (ret)
  273. goto free_phydev;
  274. return 0;
  275. free_phydev:
  276. free(phydev);
  277. free_bus:
  278. free(bus);
  279. return ret;
  280. }
  281. int mx6_rgmii_rework(struct phy_device *phydev)
  282. {
  283. unsigned short id1, id2;
  284. unsigned short val;
  285. /* check whether KSZ9031 or AR8035 has to be configured */
  286. id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2);
  287. id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3);
  288. if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) {
  289. /* finalize phy configuration for Micrel KSZ9031 */
  290. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
  291. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 4);
  292. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
  293. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x0000);
  294. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
  295. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 5);
  296. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
  297. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, MII_KSZ9031_MOD_REG);
  298. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
  299. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 6);
  300. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
  301. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0xFFFF);
  302. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);
  303. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 8);
  304. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);
  305. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x3FFF);
  306. /* fix KSZ9031 link up issue */
  307. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 0x0);
  308. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x4);
  309. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_NO_POST_INC);
  310. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x6);
  311. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_REG);
  312. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x3);
  313. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_NO_POST_INC);
  314. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x1A80);
  315. }
  316. if ((id1 == 0x004d) && (id2 == 0xd072)) {
  317. /* enable AR8035 ouput a 125MHz clk from CLK_25M */
  318. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 0x7);
  319. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, MII_KSZ9031_MOD_DATA_POST_INC_RW | 0x16);
  320. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_NO_POST_INC | 0x7);
  321. val = phy_read(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA);
  322. val &= 0xfe63;
  323. val |= 0x18;
  324. phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, val);
  325. /* introduce tx clock delay */
  326. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
  327. val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
  328. val |= 0x0100;
  329. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
  330. /* disable hibernation */
  331. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0xb);
  332. val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
  333. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3c40);
  334. }
  335. return 0;
  336. }
  337. int board_phy_config(struct phy_device *phydev)
  338. {
  339. mx6_rgmii_rework(phydev);
  340. if (phydev->drv->config)
  341. phydev->drv->config(phydev);
  342. return 0;
  343. }
  344. static void setup_iomux_uart(void)
  345. {
  346. SETUP_IOMUX_PADS(uart2_pads);
  347. }
  348. #ifdef CONFIG_MXC_SPI
  349. static void setup_spi(void)
  350. {
  351. SETUP_IOMUX_PADS(ecspi1_pads);
  352. gpio_direction_output(IMX_GPIO_NR(3, 19), 0);
  353. }
  354. #endif
  355. #ifdef CONFIG_FSL_ESDHC_IMX
  356. static struct fsl_esdhc_cfg usdhc_cfg[] = {
  357. {USDHC2_BASE_ADDR},
  358. {USDHC3_BASE_ADDR},
  359. {USDHC4_BASE_ADDR},
  360. };
  361. int board_mmc_getcd(struct mmc *mmc)
  362. {
  363. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  364. int ret = 0;
  365. switch (cfg->esdhc_base) {
  366. case USDHC2_BASE_ADDR:
  367. gpio_direction_input(IMX_GPIO_NR(1, 4));
  368. ret = !gpio_get_value(IMX_GPIO_NR(1, 4));
  369. break;
  370. case USDHC3_BASE_ADDR:
  371. ret = 1; /* eMMC is always present */
  372. break;
  373. case USDHC4_BASE_ADDR:
  374. gpio_direction_input(IMX_GPIO_NR(2, 6));
  375. ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
  376. break;
  377. default:
  378. printf("Bad USDHC interface\n");
  379. }
  380. return ret;
  381. }
  382. int board_mmc_init(bd_t *bis)
  383. {
  384. #ifndef CONFIG_SPL_BUILD
  385. s32 status = 0;
  386. int i;
  387. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  388. usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  389. usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
  390. SETUP_IOMUX_PADS(usdhc2_pads);
  391. SETUP_IOMUX_PADS(usdhc3_pads);
  392. SETUP_IOMUX_PADS(usdhc4_pads);
  393. for (i = 0; i < ARRAY_SIZE(usdhc_cfg); i++) {
  394. status = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  395. if (status)
  396. return status;
  397. }
  398. return 0;
  399. #else
  400. SETUP_IOMUX_PADS(usdhc4_pads);
  401. usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
  402. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
  403. gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
  404. return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  405. #endif
  406. }
  407. #endif
  408. int board_ehci_hcd_init(int port)
  409. {
  410. switch (port) {
  411. case 0:
  412. SETUP_IOMUX_PADS(usb_otg_pads);
  413. /*
  414. * set daisy chain for otg_pin_id on 6q.
  415. * for 6dl, this bit is reserved
  416. */
  417. imx_iomux_set_gpr_register(1, 13, 1, 1);
  418. break;
  419. case 1:
  420. /* nothing to do */
  421. break;
  422. default:
  423. printf("Invalid USB port: %d\n", port);
  424. return -EINVAL;
  425. }
  426. return 0;
  427. }
  428. int board_ehci_power(int port, int on)
  429. {
  430. switch (port) {
  431. case 0:
  432. break;
  433. case 1:
  434. gpio_direction_output(IMX_GPIO_NR(5, 5), on);
  435. break;
  436. default:
  437. printf("Invalid USB port: %d\n", port);
  438. return -EINVAL;
  439. }
  440. return 0;
  441. }
  442. struct display_info_t {
  443. int bus;
  444. int addr;
  445. int pixfmt;
  446. int (*detect)(struct display_info_t const *dev);
  447. void (*enable)(struct display_info_t const *dev);
  448. struct fb_videomode mode;
  449. };
  450. static void disable_lvds(struct display_info_t const *dev)
  451. {
  452. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  453. clrbits_le32(&iomux->gpr[2], IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
  454. IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
  455. }
  456. static void do_enable_hdmi(struct display_info_t const *dev)
  457. {
  458. disable_lvds(dev);
  459. imx_enable_hdmi_phy();
  460. }
  461. static struct display_info_t const displays[] = {
  462. {
  463. .bus = -1,
  464. .addr = 0,
  465. .pixfmt = IPU_PIX_FMT_RGB666,
  466. .detect = NULL,
  467. .enable = NULL,
  468. .mode = {
  469. .name =
  470. "Hannstar-XGA",
  471. .refresh = 60,
  472. .xres = 1024,
  473. .yres = 768,
  474. .pixclock = 15385,
  475. .left_margin = 220,
  476. .right_margin = 40,
  477. .upper_margin = 21,
  478. .lower_margin = 7,
  479. .hsync_len = 60,
  480. .vsync_len = 10,
  481. .sync = FB_SYNC_EXT,
  482. .vmode = FB_VMODE_NONINTERLACED } },
  483. {
  484. .bus = -1,
  485. .addr = 0,
  486. .pixfmt = IPU_PIX_FMT_RGB24,
  487. .detect = NULL,
  488. .enable = do_enable_hdmi,
  489. .mode = {
  490. .name = "HDMI",
  491. .refresh = 60,
  492. .xres = 1024,
  493. .yres = 768,
  494. .pixclock = 15385,
  495. .left_margin = 220,
  496. .right_margin = 40,
  497. .upper_margin = 21,
  498. .lower_margin = 7,
  499. .hsync_len = 60,
  500. .vsync_len = 10,
  501. .sync = FB_SYNC_EXT,
  502. .vmode = FB_VMODE_NONINTERLACED } }
  503. };
  504. int board_video_skip(void)
  505. {
  506. int i;
  507. int ret;
  508. char const *panel = env_get("panel");
  509. if (!panel) {
  510. for (i = 0; i < ARRAY_SIZE(displays); i++) {
  511. struct display_info_t const *dev = displays + i;
  512. if (dev->detect && dev->detect(dev)) {
  513. panel = dev->mode.name;
  514. printf("auto-detected panel %s\n", panel);
  515. break;
  516. }
  517. }
  518. if (!panel) {
  519. panel = displays[0].mode.name;
  520. printf("No panel detected: default to %s\n", panel);
  521. i = 0;
  522. }
  523. } else {
  524. for (i = 0; i < ARRAY_SIZE(displays); i++) {
  525. if (!strcmp(panel, displays[i].mode.name))
  526. break;
  527. }
  528. }
  529. if (i < ARRAY_SIZE(displays)) {
  530. ret = ipuv3_fb_init(&displays[i].mode, 0, displays[i].pixfmt);
  531. if (!ret) {
  532. if (displays[i].enable)
  533. displays[i].enable(displays + i);
  534. printf("Display: %s (%ux%u)\n",
  535. displays[i].mode.name, displays[i].mode.xres,
  536. displays[i].mode.yres);
  537. } else
  538. printf("LCD %s cannot be configured: %d\n",
  539. displays[i].mode.name, ret);
  540. } else {
  541. printf("unsupported panel %s\n", panel);
  542. return -EINVAL;
  543. }
  544. return 0;
  545. }
  546. static void setup_display(void)
  547. {
  548. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  549. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  550. int reg;
  551. enable_ipu_clock();
  552. imx_setup_hdmi();
  553. /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
  554. setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK |
  555. MXC_CCM_CCGR3_LDB_DI1_MASK);
  556. /* set LDB0, LDB1 clk select to 011/011 */
  557. reg = readl(&mxc_ccm->cs2cdr);
  558. reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
  559. MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
  560. reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
  561. (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
  562. writel(reg, &mxc_ccm->cs2cdr);
  563. setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV |
  564. MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV);
  565. setbits_le32(&mxc_ccm->chsccdr, CHSCCDR_CLK_SEL_LDB_DI0 <<
  566. MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET |
  567. CHSCCDR_CLK_SEL_LDB_DI0 <<
  568. MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
  569. reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
  570. | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
  571. | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
  572. | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
  573. | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
  574. | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
  575. | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
  576. | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
  577. | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
  578. writel(reg, &iomux->gpr[2]);
  579. reg = readl(&iomux->gpr[3]);
  580. reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
  581. IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) |
  582. (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
  583. IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
  584. writel(reg, &iomux->gpr[3]);
  585. }
  586. /*
  587. * Do not overwrite the console
  588. * Use always serial for U-Boot console
  589. */
  590. int overwrite_console(void)
  591. {
  592. return 1;
  593. }
  594. int board_early_init_f(void)
  595. {
  596. setup_iomux_uart();
  597. #ifdef CONFIG_MXC_SPI
  598. setup_spi();
  599. #endif
  600. return 0;
  601. }
  602. int board_init(void)
  603. {
  604. /* address of boot parameters */
  605. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  606. if (is_mx6dq())
  607. setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
  608. else
  609. setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
  610. setup_display();
  611. #ifdef CONFIG_SATA
  612. setup_sata();
  613. #endif
  614. return 0;
  615. }
  616. int checkboard(void)
  617. {
  618. char *type = "unknown";
  619. if (is_cpu_type(MXC_CPU_MX6Q))
  620. type = "Quad";
  621. else if (is_cpu_type(MXC_CPU_MX6D))
  622. type = "Dual";
  623. else if (is_cpu_type(MXC_CPU_MX6DL))
  624. type = "Dual-Lite";
  625. else if (is_cpu_type(MXC_CPU_MX6SOLO))
  626. type = "Solo";
  627. printf("Board: conga-QMX6 %s\n", type);
  628. return 0;
  629. }
  630. #ifdef CONFIG_MXC_SPI
  631. int board_spi_cs_gpio(unsigned bus, unsigned cs)
  632. {
  633. return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -EINVAL;
  634. }
  635. #endif
  636. #ifdef CONFIG_CMD_BMODE
  637. static const struct boot_mode board_boot_modes[] = {
  638. /* 4 bit bus width */
  639. {"mmc0", MAKE_CFGVAL(0x50, 0x20, 0x00, 0x00)},
  640. {"mmc1", MAKE_CFGVAL(0x50, 0x38, 0x00, 0x00)},
  641. {NULL, 0},
  642. };
  643. #endif
  644. int misc_init_r(void)
  645. {
  646. #ifdef CONFIG_CMD_BMODE
  647. add_board_boot_modes(board_boot_modes);
  648. #endif
  649. return 0;
  650. }
  651. int board_late_init(void)
  652. {
  653. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  654. if (is_mx6dq())
  655. env_set("board_rev", "MX6Q");
  656. else
  657. env_set("board_rev", "MX6DL");
  658. #endif
  659. return 0;
  660. }
  661. #ifdef CONFIG_SPL_BUILD
  662. #include <asm/arch/mx6-ddr.h>
  663. #include <spl.h>
  664. #include <linux/libfdt.h>
  665. #include <spi_flash.h>
  666. #include <spi.h>
  667. const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = {
  668. .dram_sdclk_0 = 0x00000030,
  669. .dram_sdclk_1 = 0x00000030,
  670. .dram_cas = 0x00000030,
  671. .dram_ras = 0x00000030,
  672. .dram_reset = 0x00000030,
  673. .dram_sdcke0 = 0x00003000,
  674. .dram_sdcke1 = 0x00003000,
  675. .dram_sdba2 = 0x00000000,
  676. .dram_sdodt0 = 0x00000030,
  677. .dram_sdodt1 = 0x00000030,
  678. .dram_sdqs0 = 0x00000030,
  679. .dram_sdqs1 = 0x00000030,
  680. .dram_sdqs2 = 0x00000030,
  681. .dram_sdqs3 = 0x00000030,
  682. .dram_sdqs4 = 0x00000030,
  683. .dram_sdqs5 = 0x00000030,
  684. .dram_sdqs6 = 0x00000030,
  685. .dram_sdqs7 = 0x00000030,
  686. .dram_dqm0 = 0x00000030,
  687. .dram_dqm1 = 0x00000030,
  688. .dram_dqm2 = 0x00000030,
  689. .dram_dqm3 = 0x00000030,
  690. .dram_dqm4 = 0x00000030,
  691. .dram_dqm5 = 0x00000030,
  692. .dram_dqm6 = 0x00000030,
  693. .dram_dqm7 = 0x00000030,
  694. };
  695. static const struct mx6sdl_iomux_ddr_regs mx6dl_ddr_ioregs = {
  696. .dram_sdclk_0 = 0x00000030,
  697. .dram_sdclk_1 = 0x00000030,
  698. .dram_cas = 0x00000030,
  699. .dram_ras = 0x00000030,
  700. .dram_reset = 0x00000030,
  701. .dram_sdcke0 = 0x00003000,
  702. .dram_sdcke1 = 0x00003000,
  703. .dram_sdba2 = 0x00000000,
  704. .dram_sdodt0 = 0x00000030,
  705. .dram_sdodt1 = 0x00000030,
  706. .dram_sdqs0 = 0x00000030,
  707. .dram_sdqs1 = 0x00000030,
  708. .dram_sdqs2 = 0x00000030,
  709. .dram_sdqs3 = 0x00000030,
  710. .dram_sdqs4 = 0x00000030,
  711. .dram_sdqs5 = 0x00000030,
  712. .dram_sdqs6 = 0x00000030,
  713. .dram_sdqs7 = 0x00000030,
  714. .dram_dqm0 = 0x00000030,
  715. .dram_dqm1 = 0x00000030,
  716. .dram_dqm2 = 0x00000030,
  717. .dram_dqm3 = 0x00000030,
  718. .dram_dqm4 = 0x00000030,
  719. .dram_dqm5 = 0x00000030,
  720. .dram_dqm6 = 0x00000030,
  721. .dram_dqm7 = 0x00000030,
  722. };
  723. const struct mx6dq_iomux_grp_regs mx6q_grp_ioregs = {
  724. .grp_ddr_type = 0x000C0000,
  725. .grp_ddrmode_ctl = 0x00020000,
  726. .grp_ddrpke = 0x00000000,
  727. .grp_addds = 0x00000030,
  728. .grp_ctlds = 0x00000030,
  729. .grp_ddrmode = 0x00020000,
  730. .grp_b0ds = 0x00000030,
  731. .grp_b1ds = 0x00000030,
  732. .grp_b2ds = 0x00000030,
  733. .grp_b3ds = 0x00000030,
  734. .grp_b4ds = 0x00000030,
  735. .grp_b5ds = 0x00000030,
  736. .grp_b6ds = 0x00000030,
  737. .grp_b7ds = 0x00000030,
  738. };
  739. static const struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
  740. .grp_ddr_type = 0x000c0000,
  741. .grp_ddrmode_ctl = 0x00020000,
  742. .grp_ddrpke = 0x00000000,
  743. .grp_addds = 0x00000030,
  744. .grp_ctlds = 0x00000030,
  745. .grp_ddrmode = 0x00020000,
  746. .grp_b0ds = 0x00000030,
  747. .grp_b1ds = 0x00000030,
  748. .grp_b2ds = 0x00000030,
  749. .grp_b3ds = 0x00000030,
  750. .grp_b4ds = 0x00000030,
  751. .grp_b5ds = 0x00000030,
  752. .grp_b6ds = 0x00000030,
  753. .grp_b7ds = 0x00000030,
  754. };
  755. const struct mx6_mmdc_calibration mx6q_mmcd_calib = {
  756. .p0_mpwldectrl0 = 0x0016001A,
  757. .p0_mpwldectrl1 = 0x0023001C,
  758. .p1_mpwldectrl0 = 0x0028003A,
  759. .p1_mpwldectrl1 = 0x001F002C,
  760. .p0_mpdgctrl0 = 0x43440354,
  761. .p0_mpdgctrl1 = 0x033C033C,
  762. .p1_mpdgctrl0 = 0x43300368,
  763. .p1_mpdgctrl1 = 0x03500330,
  764. .p0_mprddlctl = 0x3228242E,
  765. .p1_mprddlctl = 0x2C2C2636,
  766. .p0_mpwrdlctl = 0x36323A38,
  767. .p1_mpwrdlctl = 0x42324440,
  768. };
  769. const struct mx6_mmdc_calibration mx6q_2g_mmcd_calib = {
  770. .p0_mpwldectrl0 = 0x00080016,
  771. .p0_mpwldectrl1 = 0x001D0016,
  772. .p1_mpwldectrl0 = 0x0018002C,
  773. .p1_mpwldectrl1 = 0x000D001D,
  774. .p0_mpdgctrl0 = 0x43200334,
  775. .p0_mpdgctrl1 = 0x0320031C,
  776. .p1_mpdgctrl0 = 0x0344034C,
  777. .p1_mpdgctrl1 = 0x03380314,
  778. .p0_mprddlctl = 0x3E36383A,
  779. .p1_mprddlctl = 0x38363240,
  780. .p0_mpwrdlctl = 0x36364238,
  781. .p1_mpwrdlctl = 0x4230423E,
  782. };
  783. static const struct mx6_mmdc_calibration mx6s_mmcd_calib = {
  784. .p0_mpwldectrl0 = 0x00480049,
  785. .p0_mpwldectrl1 = 0x00410044,
  786. .p0_mpdgctrl0 = 0x42480248,
  787. .p0_mpdgctrl1 = 0x023C023C,
  788. .p0_mprddlctl = 0x40424644,
  789. .p0_mpwrdlctl = 0x34323034,
  790. };
  791. const struct mx6_mmdc_calibration mx6dl_mmcd_calib = {
  792. .p0_mpwldectrl0 = 0x0043004B,
  793. .p0_mpwldectrl1 = 0x003A003E,
  794. .p1_mpwldectrl0 = 0x0047004F,
  795. .p1_mpwldectrl1 = 0x004E0061,
  796. .p0_mpdgctrl0 = 0x42500250,
  797. .p0_mpdgctrl1 = 0x0238023C,
  798. .p1_mpdgctrl0 = 0x42640264,
  799. .p1_mpdgctrl1 = 0x02500258,
  800. .p0_mprddlctl = 0x40424846,
  801. .p1_mprddlctl = 0x46484842,
  802. .p0_mpwrdlctl = 0x38382C30,
  803. .p1_mpwrdlctl = 0x34343430,
  804. };
  805. static struct mx6_ddr3_cfg mem_ddr_2g = {
  806. .mem_speed = 1600,
  807. .density = 2,
  808. .width = 16,
  809. .banks = 8,
  810. .rowaddr = 14,
  811. .coladdr = 10,
  812. .pagesz = 2,
  813. .trcd = 1310,
  814. .trcmin = 4875,
  815. .trasmin = 3500,
  816. };
  817. static struct mx6_ddr3_cfg mem_ddr_4g = {
  818. .mem_speed = 1600,
  819. .density = 4,
  820. .width = 16,
  821. .banks = 8,
  822. .rowaddr = 15,
  823. .coladdr = 10,
  824. .pagesz = 2,
  825. .trcd = 1310,
  826. .trcmin = 4875,
  827. .trasmin = 3500,
  828. };
  829. static void ccgr_init(void)
  830. {
  831. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  832. writel(0x00C03F3F, &ccm->CCGR0);
  833. writel(0x0030FC03, &ccm->CCGR1);
  834. writel(0x0FFFC000, &ccm->CCGR2);
  835. writel(0x3FF00000, &ccm->CCGR3);
  836. writel(0x00FFF300, &ccm->CCGR4);
  837. writel(0x0F0000C3, &ccm->CCGR5);
  838. writel(0x000003FF, &ccm->CCGR6);
  839. }
  840. /* Define a minimal structure so that the part number can be read via SPL */
  841. struct mfgdata {
  842. unsigned char tsize;
  843. /* size of checksummed part in bytes */
  844. unsigned char ckcnt;
  845. /* checksum corrected byte */
  846. unsigned char cksum;
  847. /* decimal serial number, packed BCD */
  848. unsigned char serial[6];
  849. /* part number, right justified, ASCII */
  850. unsigned char pn[16];
  851. };
  852. static void conv_ascii(unsigned char *dst, unsigned char *src, int len)
  853. {
  854. int remain = len;
  855. unsigned char *sptr = src;
  856. unsigned char *dptr = dst;
  857. while (remain) {
  858. if (*sptr) {
  859. *dptr = *sptr;
  860. dptr++;
  861. }
  862. sptr++;
  863. remain--;
  864. }
  865. *dptr = 0x0;
  866. }
  867. #define CFG_MFG_ADDR_OFFSET (spi->size - SZ_16K)
  868. static bool is_2gb(void)
  869. {
  870. struct spi_flash *spi;
  871. int ret;
  872. char buf[sizeof(struct mfgdata)];
  873. struct mfgdata *data = (struct mfgdata *)buf;
  874. unsigned char outbuf[32];
  875. spi = spi_flash_probe(CONFIG_ENV_SPI_BUS,
  876. CONFIG_ENV_SPI_CS,
  877. CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
  878. ret = spi_flash_read(spi, CFG_MFG_ADDR_OFFSET, sizeof(struct mfgdata),
  879. buf);
  880. if (ret)
  881. return false;
  882. /* Congatec Part Numbers 104 and 105 have 2GiB of RAM */
  883. conv_ascii(outbuf, data->pn, sizeof(data->pn));
  884. if (!memcmp(outbuf, "016104", 6) || !memcmp(outbuf, "016105", 6))
  885. return true;
  886. else
  887. return false;
  888. }
  889. static void spl_dram_init(int width)
  890. {
  891. struct mx6_ddr_sysinfo sysinfo = {
  892. /* width of data bus:0=16,1=32,2=64 */
  893. .dsize = width / 32,
  894. /* config for full 4GB range so that get_mem_size() works */
  895. .cs_density = 32, /* 32Gb per CS */
  896. /* single chip select */
  897. .ncs = 1,
  898. .cs1_mirror = 0,
  899. .rtt_wr = 2,
  900. .rtt_nom = 2,
  901. .walat = 0,
  902. .ralat = 5,
  903. .mif3_mode = 3,
  904. .bi_on = 1,
  905. .sde_to_rst = 0x0d,
  906. .rst_to_cke = 0x20,
  907. .refsel = 1, /* Refresh cycles at 32KHz */
  908. .refr = 7, /* 8 refresh commands per refresh cycle */
  909. };
  910. if (is_cpu_type(MXC_CPU_MX6Q) && is_2gb()) {
  911. mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
  912. mx6_dram_cfg(&sysinfo, &mx6q_2g_mmcd_calib, &mem_ddr_4g);
  913. return;
  914. }
  915. if (is_mx6dq()) {
  916. mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs);
  917. mx6_dram_cfg(&sysinfo, &mx6q_mmcd_calib, &mem_ddr_2g);
  918. } else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
  919. sysinfo.walat = 1;
  920. mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);
  921. mx6_dram_cfg(&sysinfo, &mx6s_mmcd_calib, &mem_ddr_4g);
  922. } else if (is_cpu_type(MXC_CPU_MX6DL)) {
  923. sysinfo.walat = 1;
  924. mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs);
  925. mx6_dram_cfg(&sysinfo, &mx6dl_mmcd_calib, &mem_ddr_2g);
  926. }
  927. }
  928. void board_init_f(ulong dummy)
  929. {
  930. /* setup AIPS and disable watchdog */
  931. arch_cpu_init();
  932. ccgr_init();
  933. gpr_init();
  934. /* iomux and setup of i2c */
  935. board_early_init_f();
  936. /* setup GP timer */
  937. timer_init();
  938. /* UART clocks enabled and gd valid - init serial console */
  939. preloader_console_init();
  940. /* Needed for malloc() to work in SPL prior to board_init_r() */
  941. spl_init();
  942. /* DDR initialization */
  943. if (is_cpu_type(MXC_CPU_MX6SOLO))
  944. spl_dram_init(32);
  945. else
  946. spl_dram_init(64);
  947. /* Clear the BSS. */
  948. memset(__bss_start, 0, __bss_end - __bss_start);
  949. /* load/boot image from boot device */
  950. board_init_r(NULL, 0);
  951. }
  952. #endif