ot1200.c 9.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
  4. * Copyright (C) 2014, Bachmann electronic GmbH
  5. */
  6. #include <common.h>
  7. #include <asm/io.h>
  8. #include <asm/arch/clock.h>
  9. #include <asm/arch/imx-regs.h>
  10. #include <asm/arch/iomux.h>
  11. #include <env.h>
  12. #include <malloc.h>
  13. #include <asm/arch/mx6-pins.h>
  14. #include <asm/mach-imx/iomux-v3.h>
  15. #include <asm/mach-imx/sata.h>
  16. #include <asm/mach-imx/mxc_i2c.h>
  17. #include <asm/mach-imx/boot_mode.h>
  18. #include <asm/arch/crm_regs.h>
  19. #include <asm/arch/sys_proto.h>
  20. #include <mmc.h>
  21. #include <fsl_esdhc_imx.h>
  22. #include <netdev.h>
  23. #include <i2c.h>
  24. #include <pca953x.h>
  25. #include <asm/gpio.h>
  26. #include <phy.h>
  27. DECLARE_GLOBAL_DATA_PTR;
  28. #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
  29. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  30. OUTPUT_40OHM | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  31. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  32. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  33. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  34. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM | \
  35. PAD_CTL_HYS)
  36. #define SPI_PAD_CTRL (PAD_CTL_HYS | OUTPUT_40OHM | \
  37. PAD_CTL_SRE_FAST)
  38. #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM | \
  39. PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  40. int dram_init(void)
  41. {
  42. gd->ram_size = imx_ddr_size();
  43. return 0;
  44. }
  45. static iomux_v3_cfg_t const uart1_pads[] = {
  46. MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  47. MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  48. };
  49. static void setup_iomux_uart(void)
  50. {
  51. imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  52. }
  53. static iomux_v3_cfg_t const enet_pads[] = {
  54. MX6_PAD_KEY_ROW1__ENET_COL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  55. MX6_PAD_KEY_COL3__ENET_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL),
  56. MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  57. MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  58. MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
  59. MX6_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
  60. MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  61. MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  62. MX6_PAD_KEY_COL2__ENET_RX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  63. MX6_PAD_KEY_COL0__ENET_RX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  64. MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  65. MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
  66. MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  67. MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  68. MX6_PAD_KEY_ROW2__ENET_TX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  69. MX6_PAD_KEY_ROW0__ENET_TX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  70. MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  71. };
  72. static void setup_iomux_enet(void)
  73. {
  74. imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
  75. }
  76. static iomux_v3_cfg_t const ecspi1_pads[] = {
  77. MX6_PAD_DISP0_DAT3__ECSPI3_SS0 | MUX_PAD_CTRL(SPI_PAD_CTRL),
  78. MX6_PAD_DISP0_DAT4__ECSPI3_SS1 | MUX_PAD_CTRL(SPI_PAD_CTRL),
  79. MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
  80. MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
  81. MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
  82. };
  83. static void setup_iomux_spi(void)
  84. {
  85. imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
  86. }
  87. int board_spi_cs_gpio(unsigned bus, unsigned cs)
  88. {
  89. return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(1, 3)) : -1;
  90. }
  91. static iomux_v3_cfg_t const feature_pads[] = {
  92. /* SD card detect */
  93. MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_DOWN),
  94. /* eMMC soldered? */
  95. MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP),
  96. };
  97. static void setup_iomux_features(void)
  98. {
  99. imx_iomux_v3_setup_multiple_pads(feature_pads,
  100. ARRAY_SIZE(feature_pads));
  101. }
  102. #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  103. /* I2C2 - EEPROM */
  104. static struct i2c_pads_info i2c_pad_info1 = {
  105. .scl = {
  106. .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
  107. .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
  108. .gp = IMX_GPIO_NR(2, 30)
  109. },
  110. .sda = {
  111. .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC,
  112. .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
  113. .gp = IMX_GPIO_NR(3, 16)
  114. }
  115. };
  116. /* I2C3 - IO expander */
  117. static struct i2c_pads_info i2c_pad_info2 = {
  118. .scl = {
  119. .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
  120. .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
  121. .gp = IMX_GPIO_NR(3, 17)
  122. },
  123. .sda = {
  124. .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
  125. .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
  126. .gp = IMX_GPIO_NR(3, 18)
  127. }
  128. };
  129. static void setup_iomux_i2c(void)
  130. {
  131. setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  132. setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
  133. }
  134. static void ccgr_init(void)
  135. {
  136. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  137. writel(0x00C03F3F, &ccm->CCGR0);
  138. writel(0x0030FC33, &ccm->CCGR1);
  139. writel(0x0FFFC000, &ccm->CCGR2);
  140. writel(0x3FF00000, &ccm->CCGR3);
  141. writel(0x00FFF300, &ccm->CCGR4);
  142. writel(0x0F0000C3, &ccm->CCGR5);
  143. writel(0x000003FF, &ccm->CCGR6);
  144. }
  145. int board_early_init_f(void)
  146. {
  147. ccgr_init();
  148. gpr_init();
  149. setup_iomux_uart();
  150. setup_iomux_spi();
  151. setup_iomux_i2c();
  152. setup_iomux_features();
  153. return 0;
  154. }
  155. static iomux_v3_cfg_t const usdhc3_pads[] = {
  156. MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  157. MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  158. MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  159. MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  160. MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  161. MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  162. MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  163. MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  164. MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  165. MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  166. MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  167. };
  168. iomux_v3_cfg_t const usdhc4_pads[] = {
  169. MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  170. MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  171. MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  172. MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  173. MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  174. MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  175. };
  176. int board_mmc_getcd(struct mmc *mmc)
  177. {
  178. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  179. int ret;
  180. if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
  181. gpio_direction_input(IMX_GPIO_NR(4, 5));
  182. ret = gpio_get_value(IMX_GPIO_NR(4, 5));
  183. } else {
  184. gpio_direction_input(IMX_GPIO_NR(1, 5));
  185. ret = !gpio_get_value(IMX_GPIO_NR(1, 5));
  186. }
  187. return ret;
  188. }
  189. struct fsl_esdhc_cfg usdhc_cfg[2] = {
  190. {USDHC3_BASE_ADDR},
  191. {USDHC4_BASE_ADDR},
  192. };
  193. int board_mmc_init(bd_t *bis)
  194. {
  195. int ret;
  196. u32 index = 0;
  197. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  198. usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
  199. usdhc_cfg[0].max_bus_width = 8;
  200. usdhc_cfg[1].max_bus_width = 4;
  201. for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
  202. switch (index) {
  203. case 0:
  204. imx_iomux_v3_setup_multiple_pads(
  205. usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  206. break;
  207. case 1:
  208. imx_iomux_v3_setup_multiple_pads(
  209. usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
  210. break;
  211. default:
  212. printf("Warning: you configured more USDHC controllers"
  213. "(%d) then supported by the board (%d)\n",
  214. index + 1, CONFIG_SYS_FSL_USDHC_NUM);
  215. return -EINVAL;
  216. }
  217. ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
  218. if (ret)
  219. return ret;
  220. }
  221. return 0;
  222. }
  223. static void leds_on(void)
  224. {
  225. /* turn on all possible leds connected via GPIO expander */
  226. i2c_set_bus_num(2);
  227. pca953x_set_dir(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, PCA953X_DIR_OUT);
  228. pca953x_set_val(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, 0x0);
  229. }
  230. static void backlight_lcd_off(void)
  231. {
  232. unsigned gpio = IMX_GPIO_NR(2, 0);
  233. gpio_direction_output(gpio, 0);
  234. gpio = IMX_GPIO_NR(2, 3);
  235. gpio_direction_output(gpio, 0);
  236. }
  237. int board_eth_init(bd_t *bis)
  238. {
  239. uint32_t base = IMX_FEC_BASE;
  240. struct mii_dev *bus = NULL;
  241. struct phy_device *phydev = NULL;
  242. int ret;
  243. setup_iomux_enet();
  244. bus = fec_get_miibus(base, -1);
  245. if (!bus)
  246. return -EINVAL;
  247. /* scan phy 0 and 5 */
  248. phydev = phy_find_by_mask(bus, 0x21, PHY_INTERFACE_MODE_RGMII);
  249. if (!phydev) {
  250. ret = -EINVAL;
  251. goto free_bus;
  252. }
  253. /* depending on the phy address we can detect our board version */
  254. if (phydev->addr == 0)
  255. env_set("boardver", "");
  256. else
  257. env_set("boardver", "mr");
  258. printf("using phy at %d\n", phydev->addr);
  259. ret = fec_probe(bis, -1, base, bus, phydev);
  260. if (ret)
  261. goto free_phydev;
  262. return 0;
  263. free_phydev:
  264. free(phydev);
  265. free_bus:
  266. free(bus);
  267. return ret;
  268. }
  269. int board_init(void)
  270. {
  271. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  272. backlight_lcd_off();
  273. leds_on();
  274. #ifdef CONFIG_SATA
  275. setup_sata();
  276. #endif
  277. return 0;
  278. }
  279. int checkboard(void)
  280. {
  281. puts("Board: "CONFIG_SYS_BOARD"\n");
  282. return 0;
  283. }
  284. #ifdef CONFIG_CMD_BMODE
  285. static const struct boot_mode board_boot_modes[] = {
  286. /* 4 bit bus width */
  287. {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  288. {NULL, 0},
  289. };
  290. #endif
  291. int misc_init_r(void)
  292. {
  293. #ifdef CONFIG_CMD_BMODE
  294. add_board_boot_modes(board_boot_modes);
  295. #endif
  296. return 0;
  297. }