cpu.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
  4. */
  5. #include <common.h>
  6. #include <clk.h>
  7. #include <debug_uart.h>
  8. #include <env.h>
  9. #include <environment.h>
  10. #include <misc.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/stm32.h>
  13. #include <asm/arch/sys_proto.h>
  14. #include <dm/device.h>
  15. #include <dm/uclass.h>
  16. /* RCC register */
  17. #define RCC_TZCR (STM32_RCC_BASE + 0x00)
  18. #define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C)
  19. #define RCC_BDCR (STM32_RCC_BASE + 0x0140)
  20. #define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208)
  21. #define RCC_MP_AHB5ENSETR (STM32_RCC_BASE + 0x0210)
  22. #define RCC_BDCR_VSWRST BIT(31)
  23. #define RCC_BDCR_RTCSRC GENMASK(17, 16)
  24. #define RCC_DBGCFGR_DBGCKEN BIT(8)
  25. /* Security register */
  26. #define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04)
  27. #define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10)
  28. #define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008)
  29. #define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110)
  30. #define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114)
  31. #define TAMP_CR1 (STM32_TAMP_BASE + 0x00)
  32. #define PWR_CR1 (STM32_PWR_BASE + 0x00)
  33. #define PWR_CR1_DBP BIT(8)
  34. /* DBGMCU register */
  35. #define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00)
  36. #define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C)
  37. #define DBGMCU_APB4FZ1_IWDG2 BIT(2)
  38. #define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0)
  39. #define DBGMCU_IDC_DEV_ID_SHIFT 0
  40. #define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16)
  41. #define DBGMCU_IDC_REV_ID_SHIFT 16
  42. /* GPIOZ registers */
  43. #define GPIOZ_SECCFGR 0x54004030
  44. /* boot interface from Bootrom
  45. * - boot instance = bit 31:16
  46. * - boot device = bit 15:0
  47. */
  48. #define BOOTROM_PARAM_ADDR 0x2FFC0078
  49. #define BOOTROM_MODE_MASK GENMASK(15, 0)
  50. #define BOOTROM_MODE_SHIFT 0
  51. #define BOOTROM_INSTANCE_MASK GENMASK(31, 16)
  52. #define BOOTROM_INSTANCE_SHIFT 16
  53. /* BSEC OTP index */
  54. #define BSEC_OTP_RPN 1
  55. #define BSEC_OTP_SERIAL 13
  56. #define BSEC_OTP_PKG 16
  57. #define BSEC_OTP_MAC 57
  58. /* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */
  59. #define RPN_SHIFT 0
  60. #define RPN_MASK GENMASK(7, 0)
  61. /* Package = bit 27:29 of OTP16
  62. * - 100: LBGA448 (FFI) => AA = LFBGA 18x18mm 448 balls p. 0.8mm
  63. * - 011: LBGA354 (LCI) => AB = LFBGA 16x16mm 359 balls p. 0.8mm
  64. * - 010: TFBGA361 (FFC) => AC = TFBGA 12x12mm 361 balls p. 0.5mm
  65. * - 001: TFBGA257 (LCC) => AD = TFBGA 10x10mm 257 balls p. 0.5mm
  66. * - others: Reserved
  67. */
  68. #define PKG_SHIFT 27
  69. #define PKG_MASK GENMASK(2, 0)
  70. #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  71. #ifndef CONFIG_STM32MP1_TRUSTED
  72. static void security_init(void)
  73. {
  74. /* Disable the backup domain write protection */
  75. /* the protection is enable at each reset by hardware */
  76. /* And must be disable by software */
  77. setbits_le32(PWR_CR1, PWR_CR1_DBP);
  78. while (!(readl(PWR_CR1) & PWR_CR1_DBP))
  79. ;
  80. /* If RTC clock isn't enable so this is a cold boot then we need
  81. * to reset the backup domain
  82. */
  83. if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) {
  84. setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
  85. while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST))
  86. ;
  87. clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
  88. }
  89. /* allow non secure access in Write/Read for all peripheral */
  90. writel(GENMASK(25, 0), ETZPC_DECPROT0);
  91. /* Open SYSRAM for no secure access */
  92. writel(0x0, ETZPC_TZMA1_SIZE);
  93. /* enable TZC1 TZC2 clock */
  94. writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR);
  95. /* Region 0 set to no access by default */
  96. /* bit 0 / 16 => nsaid0 read/write Enable
  97. * bit 1 / 17 => nsaid1 read/write Enable
  98. * ...
  99. * bit 15 / 31 => nsaid15 read/write Enable
  100. */
  101. writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0);
  102. /* bit 30 / 31 => Secure Global Enable : write/read */
  103. /* bit 0 / 1 => Region Enable for filter 0/1 */
  104. writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0);
  105. /* Enable Filter 0 and 1 */
  106. setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1));
  107. /* RCC trust zone deactivated */
  108. writel(0x0, RCC_TZCR);
  109. /* TAMP: deactivate the internal tamper
  110. * Bit 23 ITAMP8E: monotonic counter overflow
  111. * Bit 20 ITAMP5E: RTC calendar overflow
  112. * Bit 19 ITAMP4E: HSE monitoring
  113. * Bit 18 ITAMP3E: LSE monitoring
  114. * Bit 16 ITAMP1E: RTC power domain supply monitoring
  115. */
  116. writel(0x0, TAMP_CR1);
  117. /* GPIOZ: deactivate the security */
  118. writel(BIT(0), RCC_MP_AHB5ENSETR);
  119. writel(0x0, GPIOZ_SECCFGR);
  120. }
  121. #endif /* CONFIG_STM32MP1_TRUSTED */
  122. /*
  123. * Debug init
  124. */
  125. static void dbgmcu_init(void)
  126. {
  127. setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
  128. /* Freeze IWDG2 if Cortex-A7 is in debug mode */
  129. setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
  130. }
  131. #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
  132. #if !defined(CONFIG_STM32MP1_TRUSTED) && \
  133. (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
  134. /* get bootmode from ROM code boot context: saved in TAMP register */
  135. static void update_bootmode(void)
  136. {
  137. u32 boot_mode;
  138. u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR);
  139. u32 bootrom_device, bootrom_instance;
  140. /* enable TAMP clock = RTCAPBEN */
  141. writel(BIT(8), RCC_MP_APB5ENSETR);
  142. /* read bootrom context */
  143. bootrom_device =
  144. (bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT;
  145. bootrom_instance =
  146. (bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT;
  147. boot_mode =
  148. ((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) |
  149. ((bootrom_instance << BOOT_INSTANCE_SHIFT) &
  150. BOOT_INSTANCE_MASK);
  151. /* save the boot mode in TAMP backup register */
  152. clrsetbits_le32(TAMP_BOOT_CONTEXT,
  153. TAMP_BOOT_MODE_MASK,
  154. boot_mode << TAMP_BOOT_MODE_SHIFT);
  155. }
  156. #endif
  157. u32 get_bootmode(void)
  158. {
  159. /* read bootmode from TAMP backup register */
  160. return (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >>
  161. TAMP_BOOT_MODE_SHIFT;
  162. }
  163. /*
  164. * Early system init
  165. */
  166. int arch_cpu_init(void)
  167. {
  168. u32 boot_mode;
  169. /* early armv7 timer init: needed for polling */
  170. timer_init();
  171. #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  172. dbgmcu_init();
  173. #ifndef CONFIG_STM32MP1_TRUSTED
  174. security_init();
  175. update_bootmode();
  176. #endif
  177. #endif
  178. boot_mode = get_bootmode();
  179. if ((boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
  180. gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
  181. #if defined(CONFIG_DEBUG_UART) && \
  182. !defined(CONFIG_STM32MP1_TRUSTED) && \
  183. (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
  184. else
  185. debug_uart_init();
  186. #endif
  187. return 0;
  188. }
  189. void enable_caches(void)
  190. {
  191. /* Enable D-cache. I-cache is already enabled in start.S */
  192. dcache_enable();
  193. }
  194. static u32 read_idc(void)
  195. {
  196. setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
  197. return readl(DBGMCU_IDC);
  198. }
  199. u32 get_cpu_rev(void)
  200. {
  201. return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT;
  202. }
  203. static u32 get_otp(int index, int shift, int mask)
  204. {
  205. int ret;
  206. struct udevice *dev;
  207. u32 otp = 0;
  208. ret = uclass_get_device_by_driver(UCLASS_MISC,
  209. DM_GET_DRIVER(stm32mp_bsec),
  210. &dev);
  211. if (!ret)
  212. ret = misc_read(dev, STM32_BSEC_SHADOW(index),
  213. &otp, sizeof(otp));
  214. return (otp >> shift) & mask;
  215. }
  216. /* Get Device Part Number (RPN) from OTP */
  217. static u32 get_cpu_rpn(void)
  218. {
  219. return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK);
  220. }
  221. u32 get_cpu_type(void)
  222. {
  223. u32 id;
  224. id = (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT;
  225. return (id << 16) | get_cpu_rpn();
  226. }
  227. /* Get Package options from OTP */
  228. u32 get_cpu_package(void)
  229. {
  230. return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK);
  231. }
  232. #if defined(CONFIG_DISPLAY_CPUINFO)
  233. int print_cpuinfo(void)
  234. {
  235. char *cpu_s, *cpu_r, *pkg;
  236. /* MPUs Part Numbers */
  237. switch (get_cpu_type()) {
  238. case CPU_STM32MP157Cxx:
  239. cpu_s = "157C";
  240. break;
  241. case CPU_STM32MP157Axx:
  242. cpu_s = "157A";
  243. break;
  244. case CPU_STM32MP153Cxx:
  245. cpu_s = "153C";
  246. break;
  247. case CPU_STM32MP153Axx:
  248. cpu_s = "153A";
  249. break;
  250. case CPU_STM32MP151Cxx:
  251. cpu_s = "151C";
  252. break;
  253. case CPU_STM32MP151Axx:
  254. cpu_s = "151A";
  255. break;
  256. default:
  257. cpu_s = "????";
  258. break;
  259. }
  260. /* Package */
  261. switch (get_cpu_package()) {
  262. case PKG_AA_LBGA448:
  263. pkg = "AA";
  264. break;
  265. case PKG_AB_LBGA354:
  266. pkg = "AB";
  267. break;
  268. case PKG_AC_TFBGA361:
  269. pkg = "AC";
  270. break;
  271. case PKG_AD_TFBGA257:
  272. pkg = "AD";
  273. break;
  274. default:
  275. pkg = "??";
  276. break;
  277. }
  278. /* REVISION */
  279. switch (get_cpu_rev()) {
  280. case CPU_REVA:
  281. cpu_r = "A";
  282. break;
  283. case CPU_REVB:
  284. cpu_r = "B";
  285. break;
  286. default:
  287. cpu_r = "?";
  288. break;
  289. }
  290. printf("CPU: STM32MP%s%s Rev.%s\n", cpu_s, pkg, cpu_r);
  291. return 0;
  292. }
  293. #endif /* CONFIG_DISPLAY_CPUINFO */
  294. static void setup_boot_mode(void)
  295. {
  296. const u32 serial_addr[] = {
  297. STM32_USART1_BASE,
  298. STM32_USART2_BASE,
  299. STM32_USART3_BASE,
  300. STM32_UART4_BASE,
  301. STM32_UART5_BASE,
  302. STM32_USART6_BASE,
  303. STM32_UART7_BASE,
  304. STM32_UART8_BASE
  305. };
  306. char cmd[60];
  307. u32 boot_ctx = readl(TAMP_BOOT_CONTEXT);
  308. u32 boot_mode =
  309. (boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT;
  310. unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
  311. u32 forced_mode = (boot_ctx & TAMP_BOOT_FORCED_MASK);
  312. struct udevice *dev;
  313. int alias;
  314. pr_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n",
  315. __func__, boot_ctx, boot_mode, instance, forced_mode);
  316. switch (boot_mode & TAMP_BOOT_DEVICE_MASK) {
  317. case BOOT_SERIAL_UART:
  318. if (instance > ARRAY_SIZE(serial_addr))
  319. break;
  320. /* serial : search associated alias in devicetree */
  321. sprintf(cmd, "serial@%x", serial_addr[instance]);
  322. if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev))
  323. break;
  324. if (fdtdec_get_alias_seq(gd->fdt_blob, "serial",
  325. dev_of_offset(dev), &alias))
  326. break;
  327. sprintf(cmd, "%d", alias);
  328. env_set("boot_device", "serial");
  329. env_set("boot_instance", cmd);
  330. /* restore console on uart when not used */
  331. if (gd->cur_serial_dev != dev) {
  332. gd->flags &= ~(GD_FLG_SILENT |
  333. GD_FLG_DISABLE_CONSOLE);
  334. printf("serial boot with console enabled!\n");
  335. }
  336. break;
  337. case BOOT_SERIAL_USB:
  338. env_set("boot_device", "usb");
  339. env_set("boot_instance", "0");
  340. break;
  341. case BOOT_FLASH_SD:
  342. case BOOT_FLASH_EMMC:
  343. sprintf(cmd, "%d", instance);
  344. env_set("boot_device", "mmc");
  345. env_set("boot_instance", cmd);
  346. break;
  347. case BOOT_FLASH_NAND:
  348. env_set("boot_device", "nand");
  349. env_set("boot_instance", "0");
  350. break;
  351. case BOOT_FLASH_NOR:
  352. env_set("boot_device", "nor");
  353. env_set("boot_instance", "0");
  354. break;
  355. default:
  356. pr_debug("unexpected boot mode = %x\n", boot_mode);
  357. break;
  358. }
  359. switch (forced_mode) {
  360. case BOOT_FASTBOOT:
  361. printf("Enter fastboot!\n");
  362. env_set("preboot", "env set preboot; fastboot 0");
  363. break;
  364. case BOOT_STM32PROG:
  365. env_set("boot_device", "usb");
  366. env_set("boot_instance", "0");
  367. break;
  368. case BOOT_UMS_MMC0:
  369. case BOOT_UMS_MMC1:
  370. case BOOT_UMS_MMC2:
  371. printf("Enter UMS!\n");
  372. instance = forced_mode - BOOT_UMS_MMC0;
  373. sprintf(cmd, "env set preboot; ums 0 mmc %d", instance);
  374. env_set("preboot", cmd);
  375. break;
  376. case BOOT_RECOVERY:
  377. env_set("preboot", "env set preboot; run altbootcmd");
  378. break;
  379. case BOOT_NORMAL:
  380. break;
  381. default:
  382. pr_debug("unexpected forced boot mode = %x\n", forced_mode);
  383. break;
  384. }
  385. /* clear TAMP for next reboot */
  386. clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, BOOT_NORMAL);
  387. }
  388. /*
  389. * If there is no MAC address in the environment, then it will be initialized
  390. * (silently) from the value in the OTP.
  391. */
  392. static int setup_mac_address(void)
  393. {
  394. #if defined(CONFIG_NET)
  395. int ret;
  396. int i;
  397. u32 otp[2];
  398. uchar enetaddr[6];
  399. struct udevice *dev;
  400. /* MAC already in environment */
  401. if (eth_env_get_enetaddr("ethaddr", enetaddr))
  402. return 0;
  403. ret = uclass_get_device_by_driver(UCLASS_MISC,
  404. DM_GET_DRIVER(stm32mp_bsec),
  405. &dev);
  406. if (ret)
  407. return ret;
  408. ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_MAC),
  409. otp, sizeof(otp));
  410. if (ret < 0)
  411. return ret;
  412. for (i = 0; i < 6; i++)
  413. enetaddr[i] = ((uint8_t *)&otp)[i];
  414. if (!is_valid_ethaddr(enetaddr)) {
  415. pr_err("invalid MAC address in OTP %pM\n", enetaddr);
  416. return -EINVAL;
  417. }
  418. pr_debug("OTP MAC address = %pM\n", enetaddr);
  419. ret = !eth_env_set_enetaddr("ethaddr", enetaddr);
  420. if (!ret)
  421. pr_err("Failed to set mac address %pM from OTP: %d\n",
  422. enetaddr, ret);
  423. #endif
  424. return 0;
  425. }
  426. static int setup_serial_number(void)
  427. {
  428. char serial_string[25];
  429. u32 otp[3] = {0, 0, 0 };
  430. struct udevice *dev;
  431. int ret;
  432. if (env_get("serial#"))
  433. return 0;
  434. ret = uclass_get_device_by_driver(UCLASS_MISC,
  435. DM_GET_DRIVER(stm32mp_bsec),
  436. &dev);
  437. if (ret)
  438. return ret;
  439. ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_SERIAL),
  440. otp, sizeof(otp));
  441. if (ret < 0)
  442. return ret;
  443. sprintf(serial_string, "%08X%08X%08X", otp[0], otp[1], otp[2]);
  444. env_set("serial#", serial_string);
  445. return 0;
  446. }
  447. int arch_misc_init(void)
  448. {
  449. setup_boot_mode();
  450. setup_mac_address();
  451. setup_serial_number();
  452. return 0;
  453. }