cpu.c 1.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018 Marvell International Ltd.
  4. *
  5. * https://spdx.org/licenses
  6. */
  7. #include <common.h>
  8. #include <asm/armv8/mmu.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/board.h>
  11. DECLARE_GLOBAL_DATA_PTR;
  12. #define OTX2_MEM_MAP_USED 4
  13. /* +1 is end of list which needs to be empty */
  14. #define OTX2_MEM_MAP_MAX (OTX2_MEM_MAP_USED + CONFIG_NR_DRAM_BANKS + 1)
  15. static struct mm_region otx2_mem_map[OTX2_MEM_MAP_MAX] = {
  16. {
  17. .virt = 0x800000000000UL,
  18. .phys = 0x800000000000UL,
  19. .size = 0x40000000000UL,
  20. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  21. PTE_BLOCK_NON_SHARE
  22. }, {
  23. .virt = 0x840000000000UL,
  24. .phys = 0x840000000000UL,
  25. .size = 0x40000000000UL,
  26. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  27. PTE_BLOCK_NON_SHARE
  28. }, {
  29. .virt = 0x880000000000UL,
  30. .phys = 0x880000000000UL,
  31. .size = 0x40000000000UL,
  32. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  33. PTE_BLOCK_NON_SHARE
  34. }, {
  35. .virt = 0x8c0000000000UL,
  36. .phys = 0x8c0000000000UL,
  37. .size = 0x40000000000UL,
  38. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  39. PTE_BLOCK_NON_SHARE
  40. }
  41. };
  42. struct mm_region *mem_map = otx2_mem_map;
  43. void mem_map_fill(void)
  44. {
  45. int banks = OTX2_MEM_MAP_USED;
  46. u32 dram_start = CONFIG_SYS_TEXT_BASE;
  47. for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  48. otx2_mem_map[banks].virt = dram_start;
  49. otx2_mem_map[banks].phys = dram_start;
  50. otx2_mem_map[banks].size = gd->ram_size;
  51. otx2_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  52. PTE_BLOCK_NON_SHARE;
  53. banks = banks + 1;
  54. }
  55. }
  56. u64 get_page_table_size(void)
  57. {
  58. return 0x80000;
  59. }
  60. void reset_cpu(ulong addr)
  61. {
  62. }