csrs-rvu.h 56 KB

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  1. /* SPDX-License-Identifier: GPL-2.0
  2. *
  3. * Copyright (C) 2020 Marvell International Ltd.
  4. *
  5. * https://spdx.org/licenses
  6. */
  7. #ifndef __CSRS_RVU_H__
  8. #define __CSRS_RVU_H__
  9. /**
  10. * @file
  11. *
  12. * Configuration and status register (CSR) address and type definitions for
  13. * RVU.
  14. *
  15. * This file is auto generated. Do not edit.
  16. *
  17. */
  18. /**
  19. * Enumeration rvu_af_int_vec_e
  20. *
  21. * RVU Admin Function Interrupt Vector Enumeration Enumerates the MSI-X
  22. * interrupt vectors. Internal: RVU maintains the state of these vectors
  23. * internally, and generates GIB messages for it without accessing the
  24. * MSI-X table region in LLC/DRAM.
  25. */
  26. #define RVU_AF_INT_VEC_E_GEN (3)
  27. #define RVU_AF_INT_VEC_E_MBOX (4)
  28. #define RVU_AF_INT_VEC_E_PFFLR (1)
  29. #define RVU_AF_INT_VEC_E_PFME (2)
  30. #define RVU_AF_INT_VEC_E_POISON (0)
  31. /**
  32. * Enumeration rvu_bar_e
  33. *
  34. * RVU Base Address Register Enumeration Enumerates the base address
  35. * registers. Internal: For documentation only.
  36. */
  37. #define RVU_BAR_E_RVU_PFX_BAR0(a) (0x840000000000ll + 0x1000000000ll * (a))
  38. #define RVU_BAR_E_RVU_PFX_BAR0_SIZE 0x10000000ull
  39. #define RVU_BAR_E_RVU_PFX_FUNCX_BAR2(a, b) \
  40. (0x840200000000ll + 0x1000000000ll * (a) + 0x2000000ll * (b))
  41. #define RVU_BAR_E_RVU_PFX_FUNCX_BAR2_SIZE 0x100000ull
  42. #define RVU_BAR_E_RVU_PFX_FUNCX_BAR4(a, b) \
  43. (0x840400000000ll + 0x1000000000ll * (a) + 0x2000000ll * (b))
  44. #define RVU_BAR_E_RVU_PFX_FUNCX_BAR4_SIZE 0x10000ull
  45. /**
  46. * Enumeration rvu_block_addr_e
  47. *
  48. * RVU Block Address Enumeration Enumerates addressing of RVU resource
  49. * blocks within each RVU BAR, i.e. values of RVU_FUNC_ADDR_S[BLOCK] and
  50. * RVU_AF_ADDR_S[BLOCK]. CNXXXX may not implement all enumerated blocks.
  51. * Software can read RVU_PF/RVU_VF_BLOCK_ADDR()_DISC[IMP] to discover
  52. * which blocks are implemented and enabled.
  53. */
  54. #define RVU_BLOCK_ADDR_E_CPTX(a) (0xa + (a))
  55. #define RVU_BLOCK_ADDR_E_LMT (1)
  56. #define RVU_BLOCK_ADDR_E_NDCX(a) (0xc + (a))
  57. #define RVU_BLOCK_ADDR_E_NIXX(a) (4 + (a))
  58. #define RVU_BLOCK_ADDR_E_NPA (3)
  59. #define RVU_BLOCK_ADDR_E_NPC (6)
  60. #define RVU_BLOCK_ADDR_E_RX(a) (0 + (a))
  61. #define RVU_BLOCK_ADDR_E_REEX(a) (0x14 + (a))
  62. #define RVU_BLOCK_ADDR_E_RVUM (0)
  63. #define RVU_BLOCK_ADDR_E_SSO (7)
  64. #define RVU_BLOCK_ADDR_E_SSOW (8)
  65. #define RVU_BLOCK_ADDR_E_TIM (9)
  66. /**
  67. * Enumeration rvu_block_type_e
  68. *
  69. * RVU Block Type Enumeration Enumerates values of
  70. * RVU_PF/RVU_VF_BLOCK_ADDR()_DISC[BTYPE].
  71. */
  72. #define RVU_BLOCK_TYPE_E_CPT (9)
  73. #define RVU_BLOCK_TYPE_E_DDF (0xb)
  74. #define RVU_BLOCK_TYPE_E_LMT (2)
  75. #define RVU_BLOCK_TYPE_E_NDC (0xa)
  76. #define RVU_BLOCK_TYPE_E_NIX (3)
  77. #define RVU_BLOCK_TYPE_E_NPA (4)
  78. #define RVU_BLOCK_TYPE_E_NPC (5)
  79. #define RVU_BLOCK_TYPE_E_RAD (0xd)
  80. #define RVU_BLOCK_TYPE_E_REE (0xe)
  81. #define RVU_BLOCK_TYPE_E_RVUM (0)
  82. #define RVU_BLOCK_TYPE_E_SSO (6)
  83. #define RVU_BLOCK_TYPE_E_SSOW (7)
  84. #define RVU_BLOCK_TYPE_E_TIM (8)
  85. #define RVU_BLOCK_TYPE_E_ZIP (0xc)
  86. /**
  87. * Enumeration rvu_bus_lf_e
  88. *
  89. * INTERNAL: RVU Bus LF Range Enumeration Enumerates the LF range for
  90. * the RVU bus. Internal: This is an enum used in csr3 virtual equations.
  91. */
  92. #define RVU_BUS_LF_E_RVU_BUS_LFX(a) (0 + 0x2000000 * (a))
  93. /**
  94. * Enumeration rvu_bus_lf_slot_e
  95. *
  96. * INTERNAL: RVU Bus LF Slot Range Enumeration Enumerates the LF and
  97. * Slot range for the RVU bus. Internal: This is an enum used in csr3
  98. * virtual equations.
  99. */
  100. #define RVU_BUS_LF_SLOT_E_RVU_BUS_LFX_SLOTX(a, b) \
  101. (0 + 0x2000000 * (a) + 0x1000 * (b))
  102. /**
  103. * Enumeration rvu_bus_pf_e
  104. *
  105. * INTERNAL: RVU Bus PF Range Enumeration Enumerates the PF range for
  106. * the RVU bus. Internal: This is an enum used in csr3 virtual equations.
  107. */
  108. #define RVU_BUS_PF_E_RVU_BUS_PFX(a) (0ll + 0x1000000000ll * (a))
  109. /**
  110. * Enumeration rvu_bus_pfvf_e
  111. *
  112. * INTERNAL: RVU Bus PFVF Range Enumeration Enumerates the PF and VF
  113. * ranges for the RVU bus. Internal: This is an enum used in csr3 virtual
  114. * equations.
  115. */
  116. #define RVU_BUS_PFVF_E_RVU_BUS_PFX(a) (0 + 0x2000000 * (a))
  117. #define RVU_BUS_PFVF_E_RVU_BUS_VFX(a) (0 + 0x2000000 * (a))
  118. /**
  119. * Enumeration rvu_busbar_e
  120. *
  121. * INTERNAL: RVU Bus Base Address Region Enumeration Enumerates the base
  122. * address region for the RVU bus. Internal: This is an enum used in csr3
  123. * virtual equations.
  124. */
  125. #define RVU_BUSBAR_E_RVU_BUSBAR0 (0)
  126. #define RVU_BUSBAR_E_RVU_BUSBAR2 (0x200000000ll)
  127. /**
  128. * Enumeration rvu_busdid_e
  129. *
  130. * INTERNAL: RVU Bus DID Enumeration Enumerates the DID offset for the
  131. * RVU bus. Internal: This is an enum used in csr3 virtual equations.
  132. */
  133. #define RVU_BUSDID_E_RVU_BUSDID (0x840000000000ll)
  134. /**
  135. * Enumeration rvu_pf_int_vec_e
  136. *
  137. * RVU PF Interrupt Vector Enumeration Enumerates the MSI-X interrupt
  138. * vectors.
  139. */
  140. #define RVU_PF_INT_VEC_E_AFPF_MBOX (6)
  141. #define RVU_PF_INT_VEC_E_VFFLRX(a) (0 + (a))
  142. #define RVU_PF_INT_VEC_E_VFMEX(a) (2 + (a))
  143. #define RVU_PF_INT_VEC_E_VFPF_MBOXX(a) (4 + (a))
  144. /**
  145. * Enumeration rvu_vf_int_vec_e
  146. *
  147. * RVU VF Interrupt Vector Enumeration Enumerates the MSI-X interrupt
  148. * vectors.
  149. */
  150. #define RVU_VF_INT_VEC_E_MBOX (0)
  151. /**
  152. * Structure rvu_af_addr_s
  153. *
  154. * RVU Admin Function Register Address Structure Address format for
  155. * accessing shared Admin Function (AF) registers in RVU PF BAR0. These
  156. * registers may be accessed by all RVU PFs whose
  157. * RVU_PRIV_PF()_CFG[AF_ENA] bit is set.
  158. */
  159. union rvu_af_addr_s {
  160. u64 u;
  161. struct rvu_af_addr_s_s {
  162. u64 addr : 28;
  163. u64 block : 5;
  164. u64 reserved_33_63 : 31;
  165. } s;
  166. /* struct rvu_af_addr_s_s cn; */
  167. };
  168. /**
  169. * Structure rvu_func_addr_s
  170. *
  171. * RVU Function-unique Address Structure Address format for accessing
  172. * function-unique registers in RVU PF/FUNC BAR2.
  173. */
  174. union rvu_func_addr_s {
  175. u32 u;
  176. struct rvu_func_addr_s_s {
  177. u32 addr : 12;
  178. u32 lf_slot : 8;
  179. u32 block : 5;
  180. u32 reserved_25_31 : 7;
  181. } s;
  182. /* struct rvu_func_addr_s_s cn; */
  183. };
  184. /**
  185. * Structure rvu_msix_vec_s
  186. *
  187. * RVU MSI-X Vector Structure Format of entries in the RVU MSI-X table
  188. * region in LLC/DRAM. See RVU_PRIV_PF()_MSIX_CFG.
  189. */
  190. union rvu_msix_vec_s {
  191. u64 u[2];
  192. struct rvu_msix_vec_s_s {
  193. u64 addr : 64;
  194. u64 data : 32;
  195. u64 mask : 1;
  196. u64 pend : 1;
  197. u64 reserved_98_127 : 30;
  198. } s;
  199. /* struct rvu_msix_vec_s_s cn; */
  200. };
  201. /**
  202. * Structure rvu_pf_func_s
  203. *
  204. * RVU PF Function Identification Structure Identifies an RVU PF/VF, and
  205. * format of *_PRIV_LF()_CFG[PF_FUNC] in RVU resource blocks, e.g.
  206. * NPA_PRIV_LF()_CFG[PF_FUNC]. Internal: Also used for PF/VF
  207. * identification on inter-coprocessor hardware interfaces (NPA, SSO,
  208. * CPT, ...).
  209. */
  210. union rvu_pf_func_s {
  211. u32 u;
  212. struct rvu_pf_func_s_s {
  213. u32 func : 10;
  214. u32 pf : 6;
  215. u32 reserved_16_31 : 16;
  216. } s;
  217. /* struct rvu_pf_func_s_s cn; */
  218. };
  219. /**
  220. * Register (RVU_PF_BAR0) rvu_af_afpf#_mbox#
  221. *
  222. * RVU Admin Function AF/PF Mailbox Registers
  223. */
  224. union rvu_af_afpfx_mboxx {
  225. u64 u;
  226. struct rvu_af_afpfx_mboxx_s {
  227. u64 data : 64;
  228. } s;
  229. /* struct rvu_af_afpfx_mboxx_s cn; */
  230. };
  231. static inline u64 RVU_AF_AFPFX_MBOXX(u64 a, u64 b)
  232. __attribute__ ((pure, always_inline));
  233. static inline u64 RVU_AF_AFPFX_MBOXX(u64 a, u64 b)
  234. {
  235. return 0x2000 + 0x10 * a + 8 * b;
  236. }
  237. /**
  238. * Register (RVU_PF_BAR0) rvu_af_bar2_alias#
  239. *
  240. * INTERNAL: RVU Admin Function BAR2 Alias Registers These registers
  241. * alias to the RVU BAR2 registers for the PF and function selected by
  242. * RVU_AF_BAR2_SEL[PF_FUNC]. Internal: Not implemented. Placeholder for
  243. * bug33464.
  244. */
  245. union rvu_af_bar2_aliasx {
  246. u64 u;
  247. struct rvu_af_bar2_aliasx_s {
  248. u64 data : 64;
  249. } s;
  250. /* struct rvu_af_bar2_aliasx_s cn; */
  251. };
  252. static inline u64 RVU_AF_BAR2_ALIASX(u64 a)
  253. __attribute__ ((pure, always_inline));
  254. static inline u64 RVU_AF_BAR2_ALIASX(u64 a)
  255. {
  256. return 0x9100000 + 8 * a;
  257. }
  258. /**
  259. * Register (RVU_PF_BAR0) rvu_af_bar2_sel
  260. *
  261. * INTERNAL: RVU Admin Function BAR2 Select Register This register
  262. * configures BAR2 accesses from the RVU_AF_BAR2_ALIAS() registers in
  263. * BAR0. Internal: Not implemented. Placeholder for bug33464.
  264. */
  265. union rvu_af_bar2_sel {
  266. u64 u;
  267. struct rvu_af_bar2_sel_s {
  268. u64 alias_pf_func : 16;
  269. u64 alias_ena : 1;
  270. u64 reserved_17_63 : 47;
  271. } s;
  272. /* struct rvu_af_bar2_sel_s cn; */
  273. };
  274. static inline u64 RVU_AF_BAR2_SEL(void)
  275. __attribute__ ((pure, always_inline));
  276. static inline u64 RVU_AF_BAR2_SEL(void)
  277. {
  278. return 0x9000000;
  279. }
  280. /**
  281. * Register (RVU_PF_BAR0) rvu_af_blk_rst
  282. *
  283. * RVU Master Admin Function Block Reset Register
  284. */
  285. union rvu_af_blk_rst {
  286. u64 u;
  287. struct rvu_af_blk_rst_s {
  288. u64 rst : 1;
  289. u64 reserved_1_62 : 62;
  290. u64 busy : 1;
  291. } s;
  292. /* struct rvu_af_blk_rst_s cn; */
  293. };
  294. static inline u64 RVU_AF_BLK_RST(void)
  295. __attribute__ ((pure, always_inline));
  296. static inline u64 RVU_AF_BLK_RST(void)
  297. {
  298. return 0x30;
  299. }
  300. /**
  301. * Register (RVU_PF_BAR0) rvu_af_bp_test
  302. *
  303. * INTERNAL: RVUM Backpressure Test Registers
  304. */
  305. union rvu_af_bp_test {
  306. u64 u;
  307. struct rvu_af_bp_test_s {
  308. u64 lfsr_freq : 12;
  309. u64 reserved_12_15 : 4;
  310. u64 bp_cfg : 16;
  311. u64 enable : 8;
  312. u64 reserved_40_63 : 24;
  313. } s;
  314. /* struct rvu_af_bp_test_s cn; */
  315. };
  316. static inline u64 RVU_AF_BP_TEST(void)
  317. __attribute__ ((pure, always_inline));
  318. static inline u64 RVU_AF_BP_TEST(void)
  319. {
  320. return 0x4000;
  321. }
  322. /**
  323. * Register (RVU_PF_BAR0) rvu_af_eco
  324. *
  325. * INTERNAL: RVU Admin Function ECO Register
  326. */
  327. union rvu_af_eco {
  328. u64 u;
  329. struct rvu_af_eco_s {
  330. u64 eco_rw : 32;
  331. u64 reserved_32_63 : 32;
  332. } s;
  333. /* struct rvu_af_eco_s cn; */
  334. };
  335. static inline u64 RVU_AF_ECO(void)
  336. __attribute__ ((pure, always_inline));
  337. static inline u64 RVU_AF_ECO(void)
  338. {
  339. return 0x20;
  340. }
  341. /**
  342. * Register (RVU_PF_BAR0) rvu_af_gen_int
  343. *
  344. * RVU Admin Function General Interrupt Register This register contains
  345. * General interrupt summary bits.
  346. */
  347. union rvu_af_gen_int {
  348. u64 u;
  349. struct rvu_af_gen_int_s {
  350. u64 unmapped : 1;
  351. u64 msix_fault : 1;
  352. u64 reserved_2_63 : 62;
  353. } s;
  354. /* struct rvu_af_gen_int_s cn; */
  355. };
  356. static inline u64 RVU_AF_GEN_INT(void)
  357. __attribute__ ((pure, always_inline));
  358. static inline u64 RVU_AF_GEN_INT(void)
  359. {
  360. return 0x120;
  361. }
  362. /**
  363. * Register (RVU_PF_BAR0) rvu_af_gen_int_ena_w1c
  364. *
  365. * RVU Admin Function General Interrupt Enable Clear Register This
  366. * register clears interrupt enable bits.
  367. */
  368. union rvu_af_gen_int_ena_w1c {
  369. u64 u;
  370. struct rvu_af_gen_int_ena_w1c_s {
  371. u64 unmapped : 1;
  372. u64 msix_fault : 1;
  373. u64 reserved_2_63 : 62;
  374. } s;
  375. /* struct rvu_af_gen_int_ena_w1c_s cn; */
  376. };
  377. static inline u64 RVU_AF_GEN_INT_ENA_W1C(void)
  378. __attribute__ ((pure, always_inline));
  379. static inline u64 RVU_AF_GEN_INT_ENA_W1C(void)
  380. {
  381. return 0x138;
  382. }
  383. /**
  384. * Register (RVU_PF_BAR0) rvu_af_gen_int_ena_w1s
  385. *
  386. * RVU Admin Function General Interrupt Enable Set Register This register
  387. * sets interrupt enable bits.
  388. */
  389. union rvu_af_gen_int_ena_w1s {
  390. u64 u;
  391. struct rvu_af_gen_int_ena_w1s_s {
  392. u64 unmapped : 1;
  393. u64 msix_fault : 1;
  394. u64 reserved_2_63 : 62;
  395. } s;
  396. /* struct rvu_af_gen_int_ena_w1s_s cn; */
  397. };
  398. static inline u64 RVU_AF_GEN_INT_ENA_W1S(void)
  399. __attribute__ ((pure, always_inline));
  400. static inline u64 RVU_AF_GEN_INT_ENA_W1S(void)
  401. {
  402. return 0x130;
  403. }
  404. /**
  405. * Register (RVU_PF_BAR0) rvu_af_gen_int_w1s
  406. *
  407. * RVU Admin Function General Interrupt Set Register This register sets
  408. * interrupt bits.
  409. */
  410. union rvu_af_gen_int_w1s {
  411. u64 u;
  412. struct rvu_af_gen_int_w1s_s {
  413. u64 unmapped : 1;
  414. u64 msix_fault : 1;
  415. u64 reserved_2_63 : 62;
  416. } s;
  417. /* struct rvu_af_gen_int_w1s_s cn; */
  418. };
  419. static inline u64 RVU_AF_GEN_INT_W1S(void)
  420. __attribute__ ((pure, always_inline));
  421. static inline u64 RVU_AF_GEN_INT_W1S(void)
  422. {
  423. return 0x128;
  424. }
  425. /**
  426. * Register (RVU_PF_BAR0) rvu_af_hwvf_rst
  427. *
  428. * RVU Admin Function Hardware VF Reset Register
  429. */
  430. union rvu_af_hwvf_rst {
  431. u64 u;
  432. struct rvu_af_hwvf_rst_s {
  433. u64 hwvf : 8;
  434. u64 reserved_8_11 : 4;
  435. u64 exec : 1;
  436. u64 reserved_13_63 : 51;
  437. } s;
  438. /* struct rvu_af_hwvf_rst_s cn; */
  439. };
  440. static inline u64 RVU_AF_HWVF_RST(void)
  441. __attribute__ ((pure, always_inline));
  442. static inline u64 RVU_AF_HWVF_RST(void)
  443. {
  444. return 0x2850;
  445. }
  446. /**
  447. * Register (RVU_PF_BAR0) rvu_af_msixtr_base
  448. *
  449. * RVU Admin Function MSI-X Table Region Base-Address Register
  450. */
  451. union rvu_af_msixtr_base {
  452. u64 u;
  453. struct rvu_af_msixtr_base_s {
  454. u64 reserved_0_6 : 7;
  455. u64 addr : 46;
  456. u64 reserved_53_63 : 11;
  457. } s;
  458. /* struct rvu_af_msixtr_base_s cn; */
  459. };
  460. static inline u64 RVU_AF_MSIXTR_BASE(void)
  461. __attribute__ ((pure, always_inline));
  462. static inline u64 RVU_AF_MSIXTR_BASE(void)
  463. {
  464. return 0x10;
  465. }
  466. /**
  467. * Register (RVU_PF_BAR0) rvu_af_pf#_vf_bar4_addr
  468. *
  469. * RVU Admin Function PF/VF BAR4 Address Registers
  470. */
  471. union rvu_af_pfx_vf_bar4_addr {
  472. u64 u;
  473. struct rvu_af_pfx_vf_bar4_addr_s {
  474. u64 reserved_0_15 : 16;
  475. u64 addr : 48;
  476. } s;
  477. /* struct rvu_af_pfx_vf_bar4_addr_s cn; */
  478. };
  479. static inline u64 RVU_AF_PFX_VF_BAR4_ADDR(u64 a)
  480. __attribute__ ((pure, always_inline));
  481. static inline u64 RVU_AF_PFX_VF_BAR4_ADDR(u64 a)
  482. {
  483. return 0x1000 + 0x10 * a;
  484. }
  485. /**
  486. * Register (RVU_PF_BAR0) rvu_af_pf_bar4_addr
  487. *
  488. * RVU Admin Function PF BAR4 Address Registers
  489. */
  490. union rvu_af_pf_bar4_addr {
  491. u64 u;
  492. struct rvu_af_pf_bar4_addr_s {
  493. u64 reserved_0_15 : 16;
  494. u64 addr : 48;
  495. } s;
  496. /* struct rvu_af_pf_bar4_addr_s cn; */
  497. };
  498. static inline u64 RVU_AF_PF_BAR4_ADDR(void)
  499. __attribute__ ((pure, always_inline));
  500. static inline u64 RVU_AF_PF_BAR4_ADDR(void)
  501. {
  502. return 0x40;
  503. }
  504. /**
  505. * Register (RVU_PF_BAR0) rvu_af_pf_rst
  506. *
  507. * RVU Admin Function PF Reset Register
  508. */
  509. union rvu_af_pf_rst {
  510. u64 u;
  511. struct rvu_af_pf_rst_s {
  512. u64 pf : 4;
  513. u64 reserved_4_11 : 8;
  514. u64 exec : 1;
  515. u64 reserved_13_63 : 51;
  516. } s;
  517. /* struct rvu_af_pf_rst_s cn; */
  518. };
  519. static inline u64 RVU_AF_PF_RST(void)
  520. __attribute__ ((pure, always_inline));
  521. static inline u64 RVU_AF_PF_RST(void)
  522. {
  523. return 0x2840;
  524. }
  525. /**
  526. * Register (RVU_PF_BAR0) rvu_af_pfaf_mbox_int
  527. *
  528. * RVU Admin Function PF to AF Mailbox Interrupt Registers
  529. */
  530. union rvu_af_pfaf_mbox_int {
  531. u64 u;
  532. struct rvu_af_pfaf_mbox_int_s {
  533. u64 mbox : 16;
  534. u64 reserved_16_63 : 48;
  535. } s;
  536. /* struct rvu_af_pfaf_mbox_int_s cn; */
  537. };
  538. static inline u64 RVU_AF_PFAF_MBOX_INT(void)
  539. __attribute__ ((pure, always_inline));
  540. static inline u64 RVU_AF_PFAF_MBOX_INT(void)
  541. {
  542. return 0x2880;
  543. }
  544. /**
  545. * Register (RVU_PF_BAR0) rvu_af_pfaf_mbox_int_ena_w1c
  546. *
  547. * RVU Admin Function PF to AF Mailbox Interrupt Enable Clear Registers
  548. * This register clears interrupt enable bits.
  549. */
  550. union rvu_af_pfaf_mbox_int_ena_w1c {
  551. u64 u;
  552. struct rvu_af_pfaf_mbox_int_ena_w1c_s {
  553. u64 mbox : 16;
  554. u64 reserved_16_63 : 48;
  555. } s;
  556. /* struct rvu_af_pfaf_mbox_int_ena_w1c_s cn; */
  557. };
  558. static inline u64 RVU_AF_PFAF_MBOX_INT_ENA_W1C(void)
  559. __attribute__ ((pure, always_inline));
  560. static inline u64 RVU_AF_PFAF_MBOX_INT_ENA_W1C(void)
  561. {
  562. return 0x2898;
  563. }
  564. /**
  565. * Register (RVU_PF_BAR0) rvu_af_pfaf_mbox_int_ena_w1s
  566. *
  567. * RVU Admin Function PF to AF Mailbox Interrupt Enable Set Registers
  568. * This register sets interrupt enable bits.
  569. */
  570. union rvu_af_pfaf_mbox_int_ena_w1s {
  571. u64 u;
  572. struct rvu_af_pfaf_mbox_int_ena_w1s_s {
  573. u64 mbox : 16;
  574. u64 reserved_16_63 : 48;
  575. } s;
  576. /* struct rvu_af_pfaf_mbox_int_ena_w1s_s cn; */
  577. };
  578. static inline u64 RVU_AF_PFAF_MBOX_INT_ENA_W1S(void)
  579. __attribute__ ((pure, always_inline));
  580. static inline u64 RVU_AF_PFAF_MBOX_INT_ENA_W1S(void)
  581. {
  582. return 0x2890;
  583. }
  584. /**
  585. * Register (RVU_PF_BAR0) rvu_af_pfaf_mbox_int_w1s
  586. *
  587. * RVU Admin Function PF to AF Mailbox Interrupt Set Registers This
  588. * register sets interrupt bits.
  589. */
  590. union rvu_af_pfaf_mbox_int_w1s {
  591. u64 u;
  592. struct rvu_af_pfaf_mbox_int_w1s_s {
  593. u64 mbox : 16;
  594. u64 reserved_16_63 : 48;
  595. } s;
  596. /* struct rvu_af_pfaf_mbox_int_w1s_s cn; */
  597. };
  598. static inline u64 RVU_AF_PFAF_MBOX_INT_W1S(void)
  599. __attribute__ ((pure, always_inline));
  600. static inline u64 RVU_AF_PFAF_MBOX_INT_W1S(void)
  601. {
  602. return 0x2888;
  603. }
  604. /**
  605. * Register (RVU_PF_BAR0) rvu_af_pfflr_int
  606. *
  607. * RVU Admin Function PF Function Level Reset Interrupt Registers
  608. */
  609. union rvu_af_pfflr_int {
  610. u64 u;
  611. struct rvu_af_pfflr_int_s {
  612. u64 flr : 16;
  613. u64 reserved_16_63 : 48;
  614. } s;
  615. /* struct rvu_af_pfflr_int_s cn; */
  616. };
  617. static inline u64 RVU_AF_PFFLR_INT(void)
  618. __attribute__ ((pure, always_inline));
  619. static inline u64 RVU_AF_PFFLR_INT(void)
  620. {
  621. return 0x28a0;
  622. }
  623. /**
  624. * Register (RVU_PF_BAR0) rvu_af_pfflr_int_ena_w1c
  625. *
  626. * RVU Admin Function PF Function Level Reset Interrupt Enable Clear
  627. * Registers This register clears interrupt enable bits.
  628. */
  629. union rvu_af_pfflr_int_ena_w1c {
  630. u64 u;
  631. struct rvu_af_pfflr_int_ena_w1c_s {
  632. u64 flr : 16;
  633. u64 reserved_16_63 : 48;
  634. } s;
  635. /* struct rvu_af_pfflr_int_ena_w1c_s cn; */
  636. };
  637. static inline u64 RVU_AF_PFFLR_INT_ENA_W1C(void)
  638. __attribute__ ((pure, always_inline));
  639. static inline u64 RVU_AF_PFFLR_INT_ENA_W1C(void)
  640. {
  641. return 0x28b8;
  642. }
  643. /**
  644. * Register (RVU_PF_BAR0) rvu_af_pfflr_int_ena_w1s
  645. *
  646. * RVU Admin Function PF Function Level Reset Interrupt Enable Set
  647. * Registers This register sets interrupt enable bits.
  648. */
  649. union rvu_af_pfflr_int_ena_w1s {
  650. u64 u;
  651. struct rvu_af_pfflr_int_ena_w1s_s {
  652. u64 flr : 16;
  653. u64 reserved_16_63 : 48;
  654. } s;
  655. /* struct rvu_af_pfflr_int_ena_w1s_s cn; */
  656. };
  657. static inline u64 RVU_AF_PFFLR_INT_ENA_W1S(void)
  658. __attribute__ ((pure, always_inline));
  659. static inline u64 RVU_AF_PFFLR_INT_ENA_W1S(void)
  660. {
  661. return 0x28b0;
  662. }
  663. /**
  664. * Register (RVU_PF_BAR0) rvu_af_pfflr_int_w1s
  665. *
  666. * RVU Admin Function PF Function Level Reset Interrupt Set Registers
  667. * This register sets interrupt bits.
  668. */
  669. union rvu_af_pfflr_int_w1s {
  670. u64 u;
  671. struct rvu_af_pfflr_int_w1s_s {
  672. u64 flr : 16;
  673. u64 reserved_16_63 : 48;
  674. } s;
  675. /* struct rvu_af_pfflr_int_w1s_s cn; */
  676. };
  677. static inline u64 RVU_AF_PFFLR_INT_W1S(void)
  678. __attribute__ ((pure, always_inline));
  679. static inline u64 RVU_AF_PFFLR_INT_W1S(void)
  680. {
  681. return 0x28a8;
  682. }
  683. /**
  684. * Register (RVU_PF_BAR0) rvu_af_pfme_int
  685. *
  686. * RVU Admin Function PF Bus Master Enable Interrupt Registers
  687. */
  688. union rvu_af_pfme_int {
  689. u64 u;
  690. struct rvu_af_pfme_int_s {
  691. u64 me : 16;
  692. u64 reserved_16_63 : 48;
  693. } s;
  694. /* struct rvu_af_pfme_int_s cn; */
  695. };
  696. static inline u64 RVU_AF_PFME_INT(void)
  697. __attribute__ ((pure, always_inline));
  698. static inline u64 RVU_AF_PFME_INT(void)
  699. {
  700. return 0x28c0;
  701. }
  702. /**
  703. * Register (RVU_PF_BAR0) rvu_af_pfme_int_ena_w1c
  704. *
  705. * RVU Admin Function PF Bus Master Enable Interrupt Enable Clear
  706. * Registers This register clears interrupt enable bits.
  707. */
  708. union rvu_af_pfme_int_ena_w1c {
  709. u64 u;
  710. struct rvu_af_pfme_int_ena_w1c_s {
  711. u64 me : 16;
  712. u64 reserved_16_63 : 48;
  713. } s;
  714. /* struct rvu_af_pfme_int_ena_w1c_s cn; */
  715. };
  716. static inline u64 RVU_AF_PFME_INT_ENA_W1C(void)
  717. __attribute__ ((pure, always_inline));
  718. static inline u64 RVU_AF_PFME_INT_ENA_W1C(void)
  719. {
  720. return 0x28d8;
  721. }
  722. /**
  723. * Register (RVU_PF_BAR0) rvu_af_pfme_int_ena_w1s
  724. *
  725. * RVU Admin Function PF Bus Master Enable Interrupt Enable Set Registers
  726. * This register sets interrupt enable bits.
  727. */
  728. union rvu_af_pfme_int_ena_w1s {
  729. u64 u;
  730. struct rvu_af_pfme_int_ena_w1s_s {
  731. u64 me : 16;
  732. u64 reserved_16_63 : 48;
  733. } s;
  734. /* struct rvu_af_pfme_int_ena_w1s_s cn; */
  735. };
  736. static inline u64 RVU_AF_PFME_INT_ENA_W1S(void)
  737. __attribute__ ((pure, always_inline));
  738. static inline u64 RVU_AF_PFME_INT_ENA_W1S(void)
  739. {
  740. return 0x28d0;
  741. }
  742. /**
  743. * Register (RVU_PF_BAR0) rvu_af_pfme_int_w1s
  744. *
  745. * RVU Admin Function PF Bus Master Enable Interrupt Set Registers This
  746. * register sets interrupt bits.
  747. */
  748. union rvu_af_pfme_int_w1s {
  749. u64 u;
  750. struct rvu_af_pfme_int_w1s_s {
  751. u64 me : 16;
  752. u64 reserved_16_63 : 48;
  753. } s;
  754. /* struct rvu_af_pfme_int_w1s_s cn; */
  755. };
  756. static inline u64 RVU_AF_PFME_INT_W1S(void)
  757. __attribute__ ((pure, always_inline));
  758. static inline u64 RVU_AF_PFME_INT_W1S(void)
  759. {
  760. return 0x28c8;
  761. }
  762. /**
  763. * Register (RVU_PF_BAR0) rvu_af_pfme_status
  764. *
  765. * RVU Admin Function PF Bus Master Enable Status Registers
  766. */
  767. union rvu_af_pfme_status {
  768. u64 u;
  769. struct rvu_af_pfme_status_s {
  770. u64 me : 16;
  771. u64 reserved_16_63 : 48;
  772. } s;
  773. /* struct rvu_af_pfme_status_s cn; */
  774. };
  775. static inline u64 RVU_AF_PFME_STATUS(void)
  776. __attribute__ ((pure, always_inline));
  777. static inline u64 RVU_AF_PFME_STATUS(void)
  778. {
  779. return 0x2800;
  780. }
  781. /**
  782. * Register (RVU_PF_BAR0) rvu_af_pftrpend
  783. *
  784. * RVU Admin Function PF Transaction Pending Registers
  785. */
  786. union rvu_af_pftrpend {
  787. u64 u;
  788. struct rvu_af_pftrpend_s {
  789. u64 trpend : 16;
  790. u64 reserved_16_63 : 48;
  791. } s;
  792. /* struct rvu_af_pftrpend_s cn; */
  793. };
  794. static inline u64 RVU_AF_PFTRPEND(void)
  795. __attribute__ ((pure, always_inline));
  796. static inline u64 RVU_AF_PFTRPEND(void)
  797. {
  798. return 0x2810;
  799. }
  800. /**
  801. * Register (RVU_PF_BAR0) rvu_af_pftrpend_w1s
  802. *
  803. * RVU Admin Function PF Transaction Pending Set Registers This register
  804. * reads or sets bits.
  805. */
  806. union rvu_af_pftrpend_w1s {
  807. u64 u;
  808. struct rvu_af_pftrpend_w1s_s {
  809. u64 trpend : 16;
  810. u64 reserved_16_63 : 48;
  811. } s;
  812. /* struct rvu_af_pftrpend_w1s_s cn; */
  813. };
  814. static inline u64 RVU_AF_PFTRPEND_W1S(void)
  815. __attribute__ ((pure, always_inline));
  816. static inline u64 RVU_AF_PFTRPEND_W1S(void)
  817. {
  818. return 0x2820;
  819. }
  820. /**
  821. * Register (RVU_PF_BAR0) rvu_af_ras
  822. *
  823. * RVU Admin Function RAS Interrupt Register This register is intended
  824. * for delivery of RAS events to the SCP, so should be ignored by OS
  825. * drivers.
  826. */
  827. union rvu_af_ras {
  828. u64 u;
  829. struct rvu_af_ras_s {
  830. u64 msix_poison : 1;
  831. u64 reserved_1_63 : 63;
  832. } s;
  833. /* struct rvu_af_ras_s cn; */
  834. };
  835. static inline u64 RVU_AF_RAS(void)
  836. __attribute__ ((pure, always_inline));
  837. static inline u64 RVU_AF_RAS(void)
  838. {
  839. return 0x100;
  840. }
  841. /**
  842. * Register (RVU_PF_BAR0) rvu_af_ras_ena_w1c
  843. *
  844. * RVU Admin Function RAS Interrupt Enable Clear Register This register
  845. * clears interrupt enable bits.
  846. */
  847. union rvu_af_ras_ena_w1c {
  848. u64 u;
  849. struct rvu_af_ras_ena_w1c_s {
  850. u64 msix_poison : 1;
  851. u64 reserved_1_63 : 63;
  852. } s;
  853. /* struct rvu_af_ras_ena_w1c_s cn; */
  854. };
  855. static inline u64 RVU_AF_RAS_ENA_W1C(void)
  856. __attribute__ ((pure, always_inline));
  857. static inline u64 RVU_AF_RAS_ENA_W1C(void)
  858. {
  859. return 0x118;
  860. }
  861. /**
  862. * Register (RVU_PF_BAR0) rvu_af_ras_ena_w1s
  863. *
  864. * RVU Admin Function RAS Interrupt Enable Set Register This register
  865. * sets interrupt enable bits.
  866. */
  867. union rvu_af_ras_ena_w1s {
  868. u64 u;
  869. struct rvu_af_ras_ena_w1s_s {
  870. u64 msix_poison : 1;
  871. u64 reserved_1_63 : 63;
  872. } s;
  873. /* struct rvu_af_ras_ena_w1s_s cn; */
  874. };
  875. static inline u64 RVU_AF_RAS_ENA_W1S(void)
  876. __attribute__ ((pure, always_inline));
  877. static inline u64 RVU_AF_RAS_ENA_W1S(void)
  878. {
  879. return 0x110;
  880. }
  881. /**
  882. * Register (RVU_PF_BAR0) rvu_af_ras_w1s
  883. *
  884. * RVU Admin Function RAS Interrupt Set Register This register sets
  885. * interrupt bits.
  886. */
  887. union rvu_af_ras_w1s {
  888. u64 u;
  889. struct rvu_af_ras_w1s_s {
  890. u64 msix_poison : 1;
  891. u64 reserved_1_63 : 63;
  892. } s;
  893. /* struct rvu_af_ras_w1s_s cn; */
  894. };
  895. static inline u64 RVU_AF_RAS_W1S(void)
  896. __attribute__ ((pure, always_inline));
  897. static inline u64 RVU_AF_RAS_W1S(void)
  898. {
  899. return 0x108;
  900. }
  901. /**
  902. * Register (RVU_PF_BAR2) rvu_pf_block_addr#_disc
  903. *
  904. * RVU PF Block Address Discovery Registers These registers allow each PF
  905. * driver to discover block resources that are provisioned to its PF. The
  906. * register's BLOCK_ADDR index is enumerated by RVU_BLOCK_ADDR_E.
  907. */
  908. union rvu_pf_block_addrx_disc {
  909. u64 u;
  910. struct rvu_pf_block_addrx_disc_s {
  911. u64 num_lfs : 9;
  912. u64 reserved_9_10 : 2;
  913. u64 imp : 1;
  914. u64 rid : 8;
  915. u64 btype : 8;
  916. u64 reserved_28_63 : 36;
  917. } s;
  918. /* struct rvu_pf_block_addrx_disc_s cn; */
  919. };
  920. static inline u64 RVU_PF_BLOCK_ADDRX_DISC(u64 a)
  921. __attribute__ ((pure, always_inline));
  922. static inline u64 RVU_PF_BLOCK_ADDRX_DISC(u64 a)
  923. {
  924. return 0x200 + 8 * a;
  925. }
  926. /**
  927. * Register (RVU_PF_BAR2) rvu_pf_int
  928. *
  929. * RVU PF Interrupt Registers
  930. */
  931. union rvu_pf_int {
  932. u64 u;
  933. struct rvu_pf_int_s {
  934. u64 mbox : 1;
  935. u64 reserved_1_63 : 63;
  936. } s;
  937. /* struct rvu_pf_int_s cn; */
  938. };
  939. static inline u64 RVU_PF_INT(void)
  940. __attribute__ ((pure, always_inline));
  941. static inline u64 RVU_PF_INT(void)
  942. {
  943. return 0xc20;
  944. }
  945. /**
  946. * Register (RVU_PF_BAR2) rvu_pf_int_ena_w1c
  947. *
  948. * RVU PF Interrupt Enable Clear Register This register clears interrupt
  949. * enable bits.
  950. */
  951. union rvu_pf_int_ena_w1c {
  952. u64 u;
  953. struct rvu_pf_int_ena_w1c_s {
  954. u64 mbox : 1;
  955. u64 reserved_1_63 : 63;
  956. } s;
  957. /* struct rvu_pf_int_ena_w1c_s cn; */
  958. };
  959. static inline u64 RVU_PF_INT_ENA_W1C(void)
  960. __attribute__ ((pure, always_inline));
  961. static inline u64 RVU_PF_INT_ENA_W1C(void)
  962. {
  963. return 0xc38;
  964. }
  965. /**
  966. * Register (RVU_PF_BAR2) rvu_pf_int_ena_w1s
  967. *
  968. * RVU PF Interrupt Enable Set Register This register sets interrupt
  969. * enable bits.
  970. */
  971. union rvu_pf_int_ena_w1s {
  972. u64 u;
  973. struct rvu_pf_int_ena_w1s_s {
  974. u64 mbox : 1;
  975. u64 reserved_1_63 : 63;
  976. } s;
  977. /* struct rvu_pf_int_ena_w1s_s cn; */
  978. };
  979. static inline u64 RVU_PF_INT_ENA_W1S(void)
  980. __attribute__ ((pure, always_inline));
  981. static inline u64 RVU_PF_INT_ENA_W1S(void)
  982. {
  983. return 0xc30;
  984. }
  985. /**
  986. * Register (RVU_PF_BAR2) rvu_pf_int_w1s
  987. *
  988. * RVU PF Interrupt Set Register This register sets interrupt bits.
  989. */
  990. union rvu_pf_int_w1s {
  991. u64 u;
  992. struct rvu_pf_int_w1s_s {
  993. u64 mbox : 1;
  994. u64 reserved_1_63 : 63;
  995. } s;
  996. /* struct rvu_pf_int_w1s_s cn; */
  997. };
  998. static inline u64 RVU_PF_INT_W1S(void)
  999. __attribute__ ((pure, always_inline));
  1000. static inline u64 RVU_PF_INT_W1S(void)
  1001. {
  1002. return 0xc28;
  1003. }
  1004. /**
  1005. * Register (RVU_PF_BAR2) rvu_pf_msix_pba#
  1006. *
  1007. * RVU PF MSI-X Pending-Bit-Array Registers This register is the MSI-X PF
  1008. * PBA table.
  1009. */
  1010. union rvu_pf_msix_pbax {
  1011. u64 u;
  1012. struct rvu_pf_msix_pbax_s {
  1013. u64 pend : 64;
  1014. } s;
  1015. /* struct rvu_pf_msix_pbax_s cn; */
  1016. };
  1017. static inline u64 RVU_PF_MSIX_PBAX(u64 a)
  1018. __attribute__ ((pure, always_inline));
  1019. static inline u64 RVU_PF_MSIX_PBAX(u64 a)
  1020. {
  1021. return 0xf0000 + 8 * a;
  1022. }
  1023. /**
  1024. * Register (RVU_PF_BAR2) rvu_pf_msix_vec#_addr
  1025. *
  1026. * RVU PF MSI-X Vector-Table Address Registers These registers and
  1027. * RVU_PF_MSIX_VEC()_CTL form the PF MSI-X vector table. The number of
  1028. * MSI-X vectors for a given PF is specified by
  1029. * RVU_PRIV_PF()_MSIX_CFG[PF_MSIXT_SIZEM1] (plus 1). Software must do a
  1030. * read after any writes to the MSI-X vector table to ensure that the
  1031. * writes have completed before interrupts are generated to the modified
  1032. * vectors.
  1033. */
  1034. union rvu_pf_msix_vecx_addr {
  1035. u64 u;
  1036. struct rvu_pf_msix_vecx_addr_s {
  1037. u64 secvec : 1;
  1038. u64 reserved_1 : 1;
  1039. u64 addr : 51;
  1040. u64 reserved_53_63 : 11;
  1041. } s;
  1042. /* struct rvu_pf_msix_vecx_addr_s cn; */
  1043. };
  1044. static inline u64 RVU_PF_MSIX_VECX_ADDR(u64 a)
  1045. __attribute__ ((pure, always_inline));
  1046. static inline u64 RVU_PF_MSIX_VECX_ADDR(u64 a)
  1047. {
  1048. return 0x80000 + 0x10 * a;
  1049. }
  1050. /**
  1051. * Register (RVU_PF_BAR2) rvu_pf_msix_vec#_ctl
  1052. *
  1053. * RVU PF MSI-X Vector-Table Control and Data Registers These registers
  1054. * and RVU_PF_MSIX_VEC()_ADDR form the PF MSI-X vector table.
  1055. */
  1056. union rvu_pf_msix_vecx_ctl {
  1057. u64 u;
  1058. struct rvu_pf_msix_vecx_ctl_s {
  1059. u64 data : 32;
  1060. u64 mask : 1;
  1061. u64 reserved_33_63 : 31;
  1062. } s;
  1063. /* struct rvu_pf_msix_vecx_ctl_s cn; */
  1064. };
  1065. static inline u64 RVU_PF_MSIX_VECX_CTL(u64 a)
  1066. __attribute__ ((pure, always_inline));
  1067. static inline u64 RVU_PF_MSIX_VECX_CTL(u64 a)
  1068. {
  1069. return 0x80008 + 0x10 * a;
  1070. }
  1071. /**
  1072. * Register (RVU_PF_BAR2) rvu_pf_pfaf_mbox#
  1073. *
  1074. * RVU PF/AF Mailbox Registers
  1075. */
  1076. union rvu_pf_pfaf_mboxx {
  1077. u64 u;
  1078. struct rvu_pf_pfaf_mboxx_s {
  1079. u64 data : 64;
  1080. } s;
  1081. /* struct rvu_pf_pfaf_mboxx_s cn; */
  1082. };
  1083. static inline u64 RVU_PF_PFAF_MBOXX(u64 a)
  1084. __attribute__ ((pure, always_inline));
  1085. static inline u64 RVU_PF_PFAF_MBOXX(u64 a)
  1086. {
  1087. return 0xc00 + 8 * a;
  1088. }
  1089. /**
  1090. * Register (RVU_PF_BAR2) rvu_pf_vf#_pfvf_mbox#
  1091. *
  1092. * RVU PF/VF Mailbox Registers
  1093. */
  1094. union rvu_pf_vfx_pfvf_mboxx {
  1095. u64 u;
  1096. struct rvu_pf_vfx_pfvf_mboxx_s {
  1097. u64 data : 64;
  1098. } s;
  1099. /* struct rvu_pf_vfx_pfvf_mboxx_s cn; */
  1100. };
  1101. static inline u64 RVU_PF_VFX_PFVF_MBOXX(u64 a, u64 b)
  1102. __attribute__ ((pure, always_inline));
  1103. static inline u64 RVU_PF_VFX_PFVF_MBOXX(u64 a, u64 b)
  1104. {
  1105. return 0 + 0x1000 * a + 8 * b;
  1106. }
  1107. /**
  1108. * Register (RVU_PF_BAR2) rvu_pf_vf_bar4_addr
  1109. *
  1110. * RVU PF VF BAR4 Address Registers
  1111. */
  1112. union rvu_pf_vf_bar4_addr {
  1113. u64 u;
  1114. struct rvu_pf_vf_bar4_addr_s {
  1115. u64 reserved_0_15 : 16;
  1116. u64 addr : 48;
  1117. } s;
  1118. /* struct rvu_pf_vf_bar4_addr_s cn; */
  1119. };
  1120. static inline u64 RVU_PF_VF_BAR4_ADDR(void)
  1121. __attribute__ ((pure, always_inline));
  1122. static inline u64 RVU_PF_VF_BAR4_ADDR(void)
  1123. {
  1124. return 0x10;
  1125. }
  1126. /**
  1127. * Register (RVU_PF_BAR2) rvu_pf_vfflr_int#
  1128. *
  1129. * RVU PF VF Function Level Reset Interrupt Registers
  1130. */
  1131. union rvu_pf_vfflr_intx {
  1132. u64 u;
  1133. struct rvu_pf_vfflr_intx_s {
  1134. u64 flr : 64;
  1135. } s;
  1136. /* struct rvu_pf_vfflr_intx_s cn; */
  1137. };
  1138. static inline u64 RVU_PF_VFFLR_INTX(u64 a)
  1139. __attribute__ ((pure, always_inline));
  1140. static inline u64 RVU_PF_VFFLR_INTX(u64 a)
  1141. {
  1142. return 0x900 + 8 * a;
  1143. }
  1144. /**
  1145. * Register (RVU_PF_BAR2) rvu_pf_vfflr_int_ena_w1c#
  1146. *
  1147. * RVU PF VF Function Level Reset Interrupt Enable Clear Registers This
  1148. * register clears interrupt enable bits.
  1149. */
  1150. union rvu_pf_vfflr_int_ena_w1cx {
  1151. u64 u;
  1152. struct rvu_pf_vfflr_int_ena_w1cx_s {
  1153. u64 flr : 64;
  1154. } s;
  1155. /* struct rvu_pf_vfflr_int_ena_w1cx_s cn; */
  1156. };
  1157. static inline u64 RVU_PF_VFFLR_INT_ENA_W1CX(u64 a)
  1158. __attribute__ ((pure, always_inline));
  1159. static inline u64 RVU_PF_VFFLR_INT_ENA_W1CX(u64 a)
  1160. {
  1161. return 0x960 + 8 * a;
  1162. }
  1163. /**
  1164. * Register (RVU_PF_BAR2) rvu_pf_vfflr_int_ena_w1s#
  1165. *
  1166. * RVU PF VF Function Level Reset Interrupt Enable Set Registers This
  1167. * register sets interrupt enable bits.
  1168. */
  1169. union rvu_pf_vfflr_int_ena_w1sx {
  1170. u64 u;
  1171. struct rvu_pf_vfflr_int_ena_w1sx_s {
  1172. u64 flr : 64;
  1173. } s;
  1174. /* struct rvu_pf_vfflr_int_ena_w1sx_s cn; */
  1175. };
  1176. static inline u64 RVU_PF_VFFLR_INT_ENA_W1SX(u64 a)
  1177. __attribute__ ((pure, always_inline));
  1178. static inline u64 RVU_PF_VFFLR_INT_ENA_W1SX(u64 a)
  1179. {
  1180. return 0x940 + 8 * a;
  1181. }
  1182. /**
  1183. * Register (RVU_PF_BAR2) rvu_pf_vfflr_int_w1s#
  1184. *
  1185. * RVU PF VF Function Level Reset Interrupt Set Registers This register
  1186. * sets interrupt bits.
  1187. */
  1188. union rvu_pf_vfflr_int_w1sx {
  1189. u64 u;
  1190. struct rvu_pf_vfflr_int_w1sx_s {
  1191. u64 flr : 64;
  1192. } s;
  1193. /* struct rvu_pf_vfflr_int_w1sx_s cn; */
  1194. };
  1195. static inline u64 RVU_PF_VFFLR_INT_W1SX(u64 a)
  1196. __attribute__ ((pure, always_inline));
  1197. static inline u64 RVU_PF_VFFLR_INT_W1SX(u64 a)
  1198. {
  1199. return 0x920 + 8 * a;
  1200. }
  1201. /**
  1202. * Register (RVU_PF_BAR2) rvu_pf_vfme_int#
  1203. *
  1204. * RVU PF VF Bus Master Enable Interrupt Registers
  1205. */
  1206. union rvu_pf_vfme_intx {
  1207. u64 u;
  1208. struct rvu_pf_vfme_intx_s {
  1209. u64 me : 64;
  1210. } s;
  1211. /* struct rvu_pf_vfme_intx_s cn; */
  1212. };
  1213. static inline u64 RVU_PF_VFME_INTX(u64 a)
  1214. __attribute__ ((pure, always_inline));
  1215. static inline u64 RVU_PF_VFME_INTX(u64 a)
  1216. {
  1217. return 0x980 + 8 * a;
  1218. }
  1219. /**
  1220. * Register (RVU_PF_BAR2) rvu_pf_vfme_int_ena_w1c#
  1221. *
  1222. * RVU PF VF Bus Master Enable Interrupt Enable Clear Registers This
  1223. * register clears interrupt enable bits.
  1224. */
  1225. union rvu_pf_vfme_int_ena_w1cx {
  1226. u64 u;
  1227. struct rvu_pf_vfme_int_ena_w1cx_s {
  1228. u64 me : 64;
  1229. } s;
  1230. /* struct rvu_pf_vfme_int_ena_w1cx_s cn; */
  1231. };
  1232. static inline u64 RVU_PF_VFME_INT_ENA_W1CX(u64 a)
  1233. __attribute__ ((pure, always_inline));
  1234. static inline u64 RVU_PF_VFME_INT_ENA_W1CX(u64 a)
  1235. {
  1236. return 0x9e0 + 8 * a;
  1237. }
  1238. /**
  1239. * Register (RVU_PF_BAR2) rvu_pf_vfme_int_ena_w1s#
  1240. *
  1241. * RVU PF VF Bus Master Enable Interrupt Enable Set Registers This
  1242. * register sets interrupt enable bits.
  1243. */
  1244. union rvu_pf_vfme_int_ena_w1sx {
  1245. u64 u;
  1246. struct rvu_pf_vfme_int_ena_w1sx_s {
  1247. u64 me : 64;
  1248. } s;
  1249. /* struct rvu_pf_vfme_int_ena_w1sx_s cn; */
  1250. };
  1251. static inline u64 RVU_PF_VFME_INT_ENA_W1SX(u64 a)
  1252. __attribute__ ((pure, always_inline));
  1253. static inline u64 RVU_PF_VFME_INT_ENA_W1SX(u64 a)
  1254. {
  1255. return 0x9c0 + 8 * a;
  1256. }
  1257. /**
  1258. * Register (RVU_PF_BAR2) rvu_pf_vfme_int_w1s#
  1259. *
  1260. * RVU PF VF Bus Master Enable Interrupt Set Registers This register sets
  1261. * interrupt bits.
  1262. */
  1263. union rvu_pf_vfme_int_w1sx {
  1264. u64 u;
  1265. struct rvu_pf_vfme_int_w1sx_s {
  1266. u64 me : 64;
  1267. } s;
  1268. /* struct rvu_pf_vfme_int_w1sx_s cn; */
  1269. };
  1270. static inline u64 RVU_PF_VFME_INT_W1SX(u64 a)
  1271. __attribute__ ((pure, always_inline));
  1272. static inline u64 RVU_PF_VFME_INT_W1SX(u64 a)
  1273. {
  1274. return 0x9a0 + 8 * a;
  1275. }
  1276. /**
  1277. * Register (RVU_PF_BAR2) rvu_pf_vfme_status#
  1278. *
  1279. * RVU PF VF Bus Master Enable Status Registers
  1280. */
  1281. union rvu_pf_vfme_statusx {
  1282. u64 u;
  1283. struct rvu_pf_vfme_statusx_s {
  1284. u64 me : 64;
  1285. } s;
  1286. /* struct rvu_pf_vfme_statusx_s cn; */
  1287. };
  1288. static inline u64 RVU_PF_VFME_STATUSX(u64 a)
  1289. __attribute__ ((pure, always_inline));
  1290. static inline u64 RVU_PF_VFME_STATUSX(u64 a)
  1291. {
  1292. return 0x800 + 8 * a;
  1293. }
  1294. /**
  1295. * Register (RVU_PF_BAR2) rvu_pf_vfpf_mbox_int#
  1296. *
  1297. * RVU VF to PF Mailbox Interrupt Registers
  1298. */
  1299. union rvu_pf_vfpf_mbox_intx {
  1300. u64 u;
  1301. struct rvu_pf_vfpf_mbox_intx_s {
  1302. u64 mbox : 64;
  1303. } s;
  1304. /* struct rvu_pf_vfpf_mbox_intx_s cn; */
  1305. };
  1306. static inline u64 RVU_PF_VFPF_MBOX_INTX(u64 a)
  1307. __attribute__ ((pure, always_inline));
  1308. static inline u64 RVU_PF_VFPF_MBOX_INTX(u64 a)
  1309. {
  1310. return 0x880 + 8 * a;
  1311. }
  1312. /**
  1313. * Register (RVU_PF_BAR2) rvu_pf_vfpf_mbox_int_ena_w1c#
  1314. *
  1315. * RVU VF to PF Mailbox Interrupt Enable Clear Registers This register
  1316. * clears interrupt enable bits.
  1317. */
  1318. union rvu_pf_vfpf_mbox_int_ena_w1cx {
  1319. u64 u;
  1320. struct rvu_pf_vfpf_mbox_int_ena_w1cx_s {
  1321. u64 mbox : 64;
  1322. } s;
  1323. /* struct rvu_pf_vfpf_mbox_int_ena_w1cx_s cn; */
  1324. };
  1325. static inline u64 RVU_PF_VFPF_MBOX_INT_ENA_W1CX(u64 a)
  1326. __attribute__ ((pure, always_inline));
  1327. static inline u64 RVU_PF_VFPF_MBOX_INT_ENA_W1CX(u64 a)
  1328. {
  1329. return 0x8e0 + 8 * a;
  1330. }
  1331. /**
  1332. * Register (RVU_PF_BAR2) rvu_pf_vfpf_mbox_int_ena_w1s#
  1333. *
  1334. * RVU VF to PF Mailbox Interrupt Enable Set Registers This register sets
  1335. * interrupt enable bits.
  1336. */
  1337. union rvu_pf_vfpf_mbox_int_ena_w1sx {
  1338. u64 u;
  1339. struct rvu_pf_vfpf_mbox_int_ena_w1sx_s {
  1340. u64 mbox : 64;
  1341. } s;
  1342. /* struct rvu_pf_vfpf_mbox_int_ena_w1sx_s cn; */
  1343. };
  1344. static inline u64 RVU_PF_VFPF_MBOX_INT_ENA_W1SX(u64 a)
  1345. __attribute__ ((pure, always_inline));
  1346. static inline u64 RVU_PF_VFPF_MBOX_INT_ENA_W1SX(u64 a)
  1347. {
  1348. return 0x8c0 + 8 * a;
  1349. }
  1350. /**
  1351. * Register (RVU_PF_BAR2) rvu_pf_vfpf_mbox_int_w1s#
  1352. *
  1353. * RVU VF to PF Mailbox Interrupt Set Registers This register sets
  1354. * interrupt bits.
  1355. */
  1356. union rvu_pf_vfpf_mbox_int_w1sx {
  1357. u64 u;
  1358. struct rvu_pf_vfpf_mbox_int_w1sx_s {
  1359. u64 mbox : 64;
  1360. } s;
  1361. /* struct rvu_pf_vfpf_mbox_int_w1sx_s cn; */
  1362. };
  1363. static inline u64 RVU_PF_VFPF_MBOX_INT_W1SX(u64 a)
  1364. __attribute__ ((pure, always_inline));
  1365. static inline u64 RVU_PF_VFPF_MBOX_INT_W1SX(u64 a)
  1366. {
  1367. return 0x8a0 + 8 * a;
  1368. }
  1369. /**
  1370. * Register (RVU_PF_BAR2) rvu_pf_vftrpend#
  1371. *
  1372. * RVU PF VF Transaction Pending Registers
  1373. */
  1374. union rvu_pf_vftrpendx {
  1375. u64 u;
  1376. struct rvu_pf_vftrpendx_s {
  1377. u64 trpend : 64;
  1378. } s;
  1379. /* struct rvu_pf_vftrpendx_s cn; */
  1380. };
  1381. static inline u64 RVU_PF_VFTRPENDX(u64 a)
  1382. __attribute__ ((pure, always_inline));
  1383. static inline u64 RVU_PF_VFTRPENDX(u64 a)
  1384. {
  1385. return 0x820 + 8 * a;
  1386. }
  1387. /**
  1388. * Register (RVU_PF_BAR2) rvu_pf_vftrpend_w1s#
  1389. *
  1390. * RVU PF VF Transaction Pending Set Registers This register reads or
  1391. * sets bits.
  1392. */
  1393. union rvu_pf_vftrpend_w1sx {
  1394. u64 u;
  1395. struct rvu_pf_vftrpend_w1sx_s {
  1396. u64 trpend : 64;
  1397. } s;
  1398. /* struct rvu_pf_vftrpend_w1sx_s cn; */
  1399. };
  1400. static inline u64 RVU_PF_VFTRPEND_W1SX(u64 a)
  1401. __attribute__ ((pure, always_inline));
  1402. static inline u64 RVU_PF_VFTRPEND_W1SX(u64 a)
  1403. {
  1404. return 0x840 + 8 * a;
  1405. }
  1406. /**
  1407. * Register (RVU_PF_BAR0) rvu_priv_active_pc
  1408. *
  1409. * RVU Active Program Counter Register
  1410. */
  1411. union rvu_priv_active_pc {
  1412. u64 u;
  1413. struct rvu_priv_active_pc_s {
  1414. u64 active_pc : 64;
  1415. } s;
  1416. /* struct rvu_priv_active_pc_s cn; */
  1417. };
  1418. static inline u64 RVU_PRIV_ACTIVE_PC(void)
  1419. __attribute__ ((pure, always_inline));
  1420. static inline u64 RVU_PRIV_ACTIVE_PC(void)
  1421. {
  1422. return 0x8000030;
  1423. }
  1424. /**
  1425. * Register (RVU_PF_BAR0) rvu_priv_block_type#_rev
  1426. *
  1427. * RVU Privileged Block Type Revision Registers These registers are used
  1428. * by configuration software to specify the revision ID of each block
  1429. * type enumerated by RVU_BLOCK_TYPE_E, to assist VF/PF software
  1430. * discovery.
  1431. */
  1432. union rvu_priv_block_typex_rev {
  1433. u64 u;
  1434. struct rvu_priv_block_typex_rev_s {
  1435. u64 rid : 8;
  1436. u64 reserved_8_63 : 56;
  1437. } s;
  1438. /* struct rvu_priv_block_typex_rev_s cn; */
  1439. };
  1440. static inline u64 RVU_PRIV_BLOCK_TYPEX_REV(u64 a)
  1441. __attribute__ ((pure, always_inline));
  1442. static inline u64 RVU_PRIV_BLOCK_TYPEX_REV(u64 a)
  1443. {
  1444. return 0x8000400 + 8 * a;
  1445. }
  1446. /**
  1447. * Register (RVU_PF_BAR0) rvu_priv_clk_cfg
  1448. *
  1449. * RVU Privileged General Configuration Register
  1450. */
  1451. union rvu_priv_clk_cfg {
  1452. u64 u;
  1453. struct rvu_priv_clk_cfg_s {
  1454. u64 blk_clken : 1;
  1455. u64 ncbi_clken : 1;
  1456. u64 reserved_2_63 : 62;
  1457. } s;
  1458. /* struct rvu_priv_clk_cfg_s cn; */
  1459. };
  1460. static inline u64 RVU_PRIV_CLK_CFG(void)
  1461. __attribute__ ((pure, always_inline));
  1462. static inline u64 RVU_PRIV_CLK_CFG(void)
  1463. {
  1464. return 0x8000020;
  1465. }
  1466. /**
  1467. * Register (RVU_PF_BAR0) rvu_priv_const
  1468. *
  1469. * RVU Privileged Constants Register This register contains constants for
  1470. * software discovery.
  1471. */
  1472. union rvu_priv_const {
  1473. u64 u;
  1474. struct rvu_priv_const_s {
  1475. u64 max_msix : 20;
  1476. u64 hwvfs : 12;
  1477. u64 pfs : 8;
  1478. u64 max_vfs_per_pf : 8;
  1479. u64 reserved_48_63 : 16;
  1480. } s;
  1481. /* struct rvu_priv_const_s cn; */
  1482. };
  1483. static inline u64 RVU_PRIV_CONST(void)
  1484. __attribute__ ((pure, always_inline));
  1485. static inline u64 RVU_PRIV_CONST(void)
  1486. {
  1487. return 0x8000000;
  1488. }
  1489. /**
  1490. * Register (RVU_PF_BAR0) rvu_priv_gen_cfg
  1491. *
  1492. * RVU Privileged General Configuration Register
  1493. */
  1494. union rvu_priv_gen_cfg {
  1495. u64 u;
  1496. struct rvu_priv_gen_cfg_s {
  1497. u64 lock : 1;
  1498. u64 reserved_1_63 : 63;
  1499. } s;
  1500. /* struct rvu_priv_gen_cfg_s cn; */
  1501. };
  1502. static inline u64 RVU_PRIV_GEN_CFG(void)
  1503. __attribute__ ((pure, always_inline));
  1504. static inline u64 RVU_PRIV_GEN_CFG(void)
  1505. {
  1506. return 0x8000010;
  1507. }
  1508. /**
  1509. * Register (RVU_PF_BAR0) rvu_priv_hwvf#_cpt#_cfg
  1510. *
  1511. * RVU Privileged Hardware VF CPT Configuration Registers Similar to
  1512. * RVU_PRIV_HWVF()_NIX()_CFG, but for CPT({a}) block.
  1513. */
  1514. union rvu_priv_hwvfx_cptx_cfg {
  1515. u64 u;
  1516. struct rvu_priv_hwvfx_cptx_cfg_s {
  1517. u64 num_lfs : 9;
  1518. u64 reserved_9_63 : 55;
  1519. } s;
  1520. /* struct rvu_priv_hwvfx_cptx_cfg_s cn; */
  1521. };
  1522. static inline u64 RVU_PRIV_HWVFX_CPTX_CFG(u64 a, u64 b)
  1523. __attribute__ ((pure, always_inline));
  1524. static inline u64 RVU_PRIV_HWVFX_CPTX_CFG(u64 a, u64 b)
  1525. {
  1526. return 0x8001350 + 0x10000 * a + 8 * b;
  1527. }
  1528. /**
  1529. * Register (RVU_PF_BAR0) rvu_priv_hwvf#_int_cfg
  1530. *
  1531. * RVU Privileged Hardware VF Interrupt Configuration Registers
  1532. */
  1533. union rvu_priv_hwvfx_int_cfg {
  1534. u64 u;
  1535. struct rvu_priv_hwvfx_int_cfg_s {
  1536. u64 msix_offset : 11;
  1537. u64 reserved_11 : 1;
  1538. u64 msix_size : 8;
  1539. u64 reserved_20_63 : 44;
  1540. } s;
  1541. /* struct rvu_priv_hwvfx_int_cfg_s cn; */
  1542. };
  1543. static inline u64 RVU_PRIV_HWVFX_INT_CFG(u64 a)
  1544. __attribute__ ((pure, always_inline));
  1545. static inline u64 RVU_PRIV_HWVFX_INT_CFG(u64 a)
  1546. {
  1547. return 0x8001280 + 0x10000 * a;
  1548. }
  1549. /**
  1550. * Register (RVU_PF_BAR0) rvu_priv_hwvf#_nix#_cfg
  1551. *
  1552. * RVU Privileged Hardware VF NIX Configuration Registers These registers
  1553. * are used to assist VF software discovery. For each HWVF, if the HWVF
  1554. * is mapped to a VF by RVU_PRIV_PF()_CFG[FIRST_HWVF,NVF], software
  1555. * writes NIX block's resource configuration for the VF in this register.
  1556. * The VF driver can read RVU_VF_BLOCK_ADDR()_DISC to discover the
  1557. * configuration.
  1558. */
  1559. union rvu_priv_hwvfx_nixx_cfg {
  1560. u64 u;
  1561. struct rvu_priv_hwvfx_nixx_cfg_s {
  1562. u64 has_lf : 1;
  1563. u64 reserved_1_63 : 63;
  1564. } s;
  1565. /* struct rvu_priv_hwvfx_nixx_cfg_s cn; */
  1566. };
  1567. static inline u64 RVU_PRIV_HWVFX_NIXX_CFG(u64 a, u64 b)
  1568. __attribute__ ((pure, always_inline));
  1569. static inline u64 RVU_PRIV_HWVFX_NIXX_CFG(u64 a, u64 b)
  1570. {
  1571. return 0x8001300 + 0x10000 * a + 8 * b;
  1572. }
  1573. /**
  1574. * Register (RVU_PF_BAR0) rvu_priv_hwvf#_npa_cfg
  1575. *
  1576. * RVU Privileged Hardware VF NPA Configuration Registers Similar to
  1577. * RVU_PRIV_HWVF()_NIX()_CFG, but for NPA block.
  1578. */
  1579. union rvu_priv_hwvfx_npa_cfg {
  1580. u64 u;
  1581. struct rvu_priv_hwvfx_npa_cfg_s {
  1582. u64 has_lf : 1;
  1583. u64 reserved_1_63 : 63;
  1584. } s;
  1585. /* struct rvu_priv_hwvfx_npa_cfg_s cn; */
  1586. };
  1587. static inline u64 RVU_PRIV_HWVFX_NPA_CFG(u64 a)
  1588. __attribute__ ((pure, always_inline));
  1589. static inline u64 RVU_PRIV_HWVFX_NPA_CFG(u64 a)
  1590. {
  1591. return 0x8001310 + 0x10000 * a;
  1592. }
  1593. /**
  1594. * Register (RVU_PF_BAR0) rvu_priv_hwvf#_sso_cfg
  1595. *
  1596. * RVU Privileged Hardware VF SSO Configuration Registers Similar to
  1597. * RVU_PRIV_HWVF()_NIX()_CFG, but for SSO block.
  1598. */
  1599. union rvu_priv_hwvfx_sso_cfg {
  1600. u64 u;
  1601. struct rvu_priv_hwvfx_sso_cfg_s {
  1602. u64 num_lfs : 9;
  1603. u64 reserved_9_63 : 55;
  1604. } s;
  1605. /* struct rvu_priv_hwvfx_sso_cfg_s cn; */
  1606. };
  1607. static inline u64 RVU_PRIV_HWVFX_SSO_CFG(u64 a)
  1608. __attribute__ ((pure, always_inline));
  1609. static inline u64 RVU_PRIV_HWVFX_SSO_CFG(u64 a)
  1610. {
  1611. return 0x8001320 + 0x10000 * a;
  1612. }
  1613. /**
  1614. * Register (RVU_PF_BAR0) rvu_priv_hwvf#_ssow_cfg
  1615. *
  1616. * RVU Privileged Hardware VF SSO Work Slot Configuration Registers
  1617. * Similar to RVU_PRIV_HWVF()_NIX()_CFG, but for SSOW block.
  1618. */
  1619. union rvu_priv_hwvfx_ssow_cfg {
  1620. u64 u;
  1621. struct rvu_priv_hwvfx_ssow_cfg_s {
  1622. u64 num_lfs : 9;
  1623. u64 reserved_9_63 : 55;
  1624. } s;
  1625. /* struct rvu_priv_hwvfx_ssow_cfg_s cn; */
  1626. };
  1627. static inline u64 RVU_PRIV_HWVFX_SSOW_CFG(u64 a)
  1628. __attribute__ ((pure, always_inline));
  1629. static inline u64 RVU_PRIV_HWVFX_SSOW_CFG(u64 a)
  1630. {
  1631. return 0x8001330 + 0x10000 * a;
  1632. }
  1633. /**
  1634. * Register (RVU_PF_BAR0) rvu_priv_hwvf#_tim_cfg
  1635. *
  1636. * RVU Privileged Hardware VF SSO Work Slot Configuration Registers
  1637. * Similar to RVU_PRIV_HWVF()_NIX()_CFG, but for TIM block.
  1638. */
  1639. union rvu_priv_hwvfx_tim_cfg {
  1640. u64 u;
  1641. struct rvu_priv_hwvfx_tim_cfg_s {
  1642. u64 num_lfs : 9;
  1643. u64 reserved_9_63 : 55;
  1644. } s;
  1645. /* struct rvu_priv_hwvfx_tim_cfg_s cn; */
  1646. };
  1647. static inline u64 RVU_PRIV_HWVFX_TIM_CFG(u64 a)
  1648. __attribute__ ((pure, always_inline));
  1649. static inline u64 RVU_PRIV_HWVFX_TIM_CFG(u64 a)
  1650. {
  1651. return 0x8001340 + 0x10000 * a;
  1652. }
  1653. /**
  1654. * Register (RVU_PF_BAR0) rvu_priv_pf#_cfg
  1655. *
  1656. * RVU Privileged PF Configuration Registers
  1657. */
  1658. union rvu_priv_pfx_cfg {
  1659. u64 u;
  1660. struct rvu_priv_pfx_cfg_s {
  1661. u64 first_hwvf : 12;
  1662. u64 nvf : 8;
  1663. u64 ena : 1;
  1664. u64 af_ena : 1;
  1665. u64 me_flr_ena : 1;
  1666. u64 pf_vf_io_bar4 : 1;
  1667. u64 reserved_24_63 : 40;
  1668. } s;
  1669. struct rvu_priv_pfx_cfg_cn96xxp1 {
  1670. u64 first_hwvf : 12;
  1671. u64 nvf : 8;
  1672. u64 ena : 1;
  1673. u64 af_ena : 1;
  1674. u64 me_flr_ena : 1;
  1675. u64 reserved_23_63 : 41;
  1676. } cn96xxp1;
  1677. /* struct rvu_priv_pfx_cfg_s cn96xxp3; */
  1678. /* struct rvu_priv_pfx_cfg_cn96xxp1 cnf95xx; */
  1679. };
  1680. static inline u64 RVU_PRIV_PFX_CFG(u64 a)
  1681. __attribute__ ((pure, always_inline));
  1682. static inline u64 RVU_PRIV_PFX_CFG(u64 a)
  1683. {
  1684. return 0x8000100 + 0x10000 * a;
  1685. }
  1686. /**
  1687. * Register (RVU_PF_BAR0) rvu_priv_pf#_cpt#_cfg
  1688. *
  1689. * RVU Privileged PF CPT Configuration Registers Similar to
  1690. * RVU_PRIV_PF()_NIX()_CFG, but for CPT({a}) block.
  1691. */
  1692. union rvu_priv_pfx_cptx_cfg {
  1693. u64 u;
  1694. struct rvu_priv_pfx_cptx_cfg_s {
  1695. u64 num_lfs : 9;
  1696. u64 reserved_9_63 : 55;
  1697. } s;
  1698. /* struct rvu_priv_pfx_cptx_cfg_s cn; */
  1699. };
  1700. static inline u64 RVU_PRIV_PFX_CPTX_CFG(u64 a, u64 b)
  1701. __attribute__ ((pure, always_inline));
  1702. static inline u64 RVU_PRIV_PFX_CPTX_CFG(u64 a, u64 b)
  1703. {
  1704. return 0x8000350 + 0x10000 * a + 8 * b;
  1705. }
  1706. /**
  1707. * Register (RVU_PF_BAR0) rvu_priv_pf#_id_cfg
  1708. *
  1709. * RVU Privileged PF ID Configuration Registers
  1710. */
  1711. union rvu_priv_pfx_id_cfg {
  1712. u64 u;
  1713. struct rvu_priv_pfx_id_cfg_s {
  1714. u64 pf_devid : 8;
  1715. u64 vf_devid : 8;
  1716. u64 class_code : 24;
  1717. u64 reserved_40_63 : 24;
  1718. } s;
  1719. /* struct rvu_priv_pfx_id_cfg_s cn; */
  1720. };
  1721. static inline u64 RVU_PRIV_PFX_ID_CFG(u64 a)
  1722. __attribute__ ((pure, always_inline));
  1723. static inline u64 RVU_PRIV_PFX_ID_CFG(u64 a)
  1724. {
  1725. return 0x8000120 + 0x10000 * a;
  1726. }
  1727. /**
  1728. * Register (RVU_PF_BAR0) rvu_priv_pf#_int_cfg
  1729. *
  1730. * RVU Privileged PF Interrupt Configuration Registers
  1731. */
  1732. union rvu_priv_pfx_int_cfg {
  1733. u64 u;
  1734. struct rvu_priv_pfx_int_cfg_s {
  1735. u64 msix_offset : 11;
  1736. u64 reserved_11 : 1;
  1737. u64 msix_size : 8;
  1738. u64 reserved_20_63 : 44;
  1739. } s;
  1740. /* struct rvu_priv_pfx_int_cfg_s cn; */
  1741. };
  1742. static inline u64 RVU_PRIV_PFX_INT_CFG(u64 a)
  1743. __attribute__ ((pure, always_inline));
  1744. static inline u64 RVU_PRIV_PFX_INT_CFG(u64 a)
  1745. {
  1746. return 0x8000200 + 0x10000 * a;
  1747. }
  1748. /**
  1749. * Register (RVU_PF_BAR0) rvu_priv_pf#_msix_cfg
  1750. *
  1751. * RVU Privileged PF MSI-X Configuration Registers These registers
  1752. * specify MSI-X table sizes and locations for RVU PFs and associated
  1753. * VFs. Hardware maintains all RVU MSI-X tables in a contiguous memory
  1754. * region in LLC/DRAM called the MSI-X table region. The table region's
  1755. * base AF IOVA is specified by RVU_AF_MSIXTR_BASE, and its size as a
  1756. * multiple of 16-byte RVU_MSIX_VEC_S structures must be less than or
  1757. * equal to RVU_PRIV_CONST[MAX_MSIX]. A PF's MSI-X table consists of the
  1758. * following range of RVU_MSIX_VEC_S structures in the table region: *
  1759. * First index: [PF_MSIXT_OFFSET]. * Last index: [PF_MSIXT_OFFSET] +
  1760. * [PF_MSIXT_SIZEM1]. If a PF has enabled VFs (associated
  1761. * RVU_PRIV_PF()_CFG[NVF] is nonzero), then each VF's MSI-X table
  1762. * consumes the following range of RVU_MSIX_VEC_S structures: * First
  1763. * index: [VF_MSIXT_OFFSET] + N*([VF_MSIXT_SIZEM1] + 1). * Last index:
  1764. * [VF_MSIXT_OFFSET] + N*([VF_MSIXT_SIZEM1] + 1) + [VF_MSIXT_SIZEM1].
  1765. * N=0 for the first VF, N=1 for the second VF, etc. Different PFs and
  1766. * VFs must have non-overlapping vector ranges, and the last index of any
  1767. * range must be less than RVU_PRIV_CONST[MAX_MSIX].
  1768. */
  1769. union rvu_priv_pfx_msix_cfg {
  1770. u64 u;
  1771. struct rvu_priv_pfx_msix_cfg_s {
  1772. u64 vf_msixt_sizem1 : 12;
  1773. u64 vf_msixt_offset : 20;
  1774. u64 pf_msixt_sizem1 : 12;
  1775. u64 pf_msixt_offset : 20;
  1776. } s;
  1777. /* struct rvu_priv_pfx_msix_cfg_s cn; */
  1778. };
  1779. static inline u64 RVU_PRIV_PFX_MSIX_CFG(u64 a)
  1780. __attribute__ ((pure, always_inline));
  1781. static inline u64 RVU_PRIV_PFX_MSIX_CFG(u64 a)
  1782. {
  1783. return 0x8000110 + 0x10000 * a;
  1784. }
  1785. /**
  1786. * Register (RVU_PF_BAR0) rvu_priv_pf#_nix#_cfg
  1787. *
  1788. * RVU Privileged PF NIX Configuration Registers These registers are used
  1789. * to assist PF software discovery. For each enabled RVU PF, software
  1790. * writes the block's resource configuration for the PF in this register.
  1791. * The PF driver can read RVU_PF_BLOCK_ADDR()_DISC to discover the
  1792. * configuration.
  1793. */
  1794. union rvu_priv_pfx_nixx_cfg {
  1795. u64 u;
  1796. struct rvu_priv_pfx_nixx_cfg_s {
  1797. u64 has_lf : 1;
  1798. u64 reserved_1_63 : 63;
  1799. } s;
  1800. /* struct rvu_priv_pfx_nixx_cfg_s cn; */
  1801. };
  1802. static inline u64 RVU_PRIV_PFX_NIXX_CFG(u64 a, u64 b)
  1803. __attribute__ ((pure, always_inline));
  1804. static inline u64 RVU_PRIV_PFX_NIXX_CFG(u64 a, u64 b)
  1805. {
  1806. return 0x8000300 + 0x10000 * a + 8 * b;
  1807. }
  1808. /**
  1809. * Register (RVU_PF_BAR0) rvu_priv_pf#_npa_cfg
  1810. *
  1811. * RVU Privileged PF NPA Configuration Registers Similar to
  1812. * RVU_PRIV_PF()_NIX()_CFG, but for NPA block.
  1813. */
  1814. union rvu_priv_pfx_npa_cfg {
  1815. u64 u;
  1816. struct rvu_priv_pfx_npa_cfg_s {
  1817. u64 has_lf : 1;
  1818. u64 reserved_1_63 : 63;
  1819. } s;
  1820. /* struct rvu_priv_pfx_npa_cfg_s cn; */
  1821. };
  1822. static inline u64 RVU_PRIV_PFX_NPA_CFG(u64 a)
  1823. __attribute__ ((pure, always_inline));
  1824. static inline u64 RVU_PRIV_PFX_NPA_CFG(u64 a)
  1825. {
  1826. return 0x8000310 + 0x10000 * a;
  1827. }
  1828. /**
  1829. * Register (RVU_PF_BAR0) rvu_priv_pf#_sso_cfg
  1830. *
  1831. * RVU Privileged PF SSO Configuration Registers Similar to
  1832. * RVU_PRIV_PF()_NIX()_CFG, but for SSO block.
  1833. */
  1834. union rvu_priv_pfx_sso_cfg {
  1835. u64 u;
  1836. struct rvu_priv_pfx_sso_cfg_s {
  1837. u64 num_lfs : 9;
  1838. u64 reserved_9_63 : 55;
  1839. } s;
  1840. /* struct rvu_priv_pfx_sso_cfg_s cn; */
  1841. };
  1842. static inline u64 RVU_PRIV_PFX_SSO_CFG(u64 a)
  1843. __attribute__ ((pure, always_inline));
  1844. static inline u64 RVU_PRIV_PFX_SSO_CFG(u64 a)
  1845. {
  1846. return 0x8000320 + 0x10000 * a;
  1847. }
  1848. /**
  1849. * Register (RVU_PF_BAR0) rvu_priv_pf#_ssow_cfg
  1850. *
  1851. * RVU Privileged PF SSO Work Slot Configuration Registers Similar to
  1852. * RVU_PRIV_PF()_NIX()_CFG, but for SSOW block.
  1853. */
  1854. union rvu_priv_pfx_ssow_cfg {
  1855. u64 u;
  1856. struct rvu_priv_pfx_ssow_cfg_s {
  1857. u64 num_lfs : 9;
  1858. u64 reserved_9_63 : 55;
  1859. } s;
  1860. /* struct rvu_priv_pfx_ssow_cfg_s cn; */
  1861. };
  1862. static inline u64 RVU_PRIV_PFX_SSOW_CFG(u64 a)
  1863. __attribute__ ((pure, always_inline));
  1864. static inline u64 RVU_PRIV_PFX_SSOW_CFG(u64 a)
  1865. {
  1866. return 0x8000330 + 0x10000 * a;
  1867. }
  1868. /**
  1869. * Register (RVU_PF_BAR0) rvu_priv_pf#_tim_cfg
  1870. *
  1871. * RVU Privileged PF SSO Work Slot Configuration Registers Similar to
  1872. * RVU_PRIV_PF()_NIX()_CFG, but for TIM block.
  1873. */
  1874. union rvu_priv_pfx_tim_cfg {
  1875. u64 u;
  1876. struct rvu_priv_pfx_tim_cfg_s {
  1877. u64 num_lfs : 9;
  1878. u64 reserved_9_63 : 55;
  1879. } s;
  1880. /* struct rvu_priv_pfx_tim_cfg_s cn; */
  1881. };
  1882. static inline u64 RVU_PRIV_PFX_TIM_CFG(u64 a)
  1883. __attribute__ ((pure, always_inline));
  1884. static inline u64 RVU_PRIV_PFX_TIM_CFG(u64 a)
  1885. {
  1886. return 0x8000340 + 0x10000 * a;
  1887. }
  1888. /**
  1889. * Register (RVU_VF_BAR2) rvu_vf_block_addr#_disc
  1890. *
  1891. * RVU VF Block Address Discovery Registers These registers allow each VF
  1892. * driver to discover block resources that are provisioned to its VF. The
  1893. * register's BLOCK_ADDR index is enumerated by RVU_BLOCK_ADDR_E.
  1894. */
  1895. union rvu_vf_block_addrx_disc {
  1896. u64 u;
  1897. struct rvu_vf_block_addrx_disc_s {
  1898. u64 num_lfs : 9;
  1899. u64 reserved_9_10 : 2;
  1900. u64 imp : 1;
  1901. u64 rid : 8;
  1902. u64 btype : 8;
  1903. u64 reserved_28_63 : 36;
  1904. } s;
  1905. /* struct rvu_vf_block_addrx_disc_s cn; */
  1906. };
  1907. static inline u64 RVU_VF_BLOCK_ADDRX_DISC(u64 a)
  1908. __attribute__ ((pure, always_inline));
  1909. static inline u64 RVU_VF_BLOCK_ADDRX_DISC(u64 a)
  1910. {
  1911. return 0x200 + 8 * a;
  1912. }
  1913. /**
  1914. * Register (RVU_VF_BAR2) rvu_vf_int
  1915. *
  1916. * RVU VF Interrupt Registers
  1917. */
  1918. union rvu_vf_int {
  1919. u64 u;
  1920. struct rvu_vf_int_s {
  1921. u64 mbox : 1;
  1922. u64 reserved_1_63 : 63;
  1923. } s;
  1924. /* struct rvu_vf_int_s cn; */
  1925. };
  1926. static inline u64 RVU_VF_INT(void)
  1927. __attribute__ ((pure, always_inline));
  1928. static inline u64 RVU_VF_INT(void)
  1929. {
  1930. return 0x20;
  1931. }
  1932. /**
  1933. * Register (RVU_VF_BAR2) rvu_vf_int_ena_w1c
  1934. *
  1935. * RVU VF Interrupt Enable Clear Register This register clears interrupt
  1936. * enable bits.
  1937. */
  1938. union rvu_vf_int_ena_w1c {
  1939. u64 u;
  1940. struct rvu_vf_int_ena_w1c_s {
  1941. u64 mbox : 1;
  1942. u64 reserved_1_63 : 63;
  1943. } s;
  1944. /* struct rvu_vf_int_ena_w1c_s cn; */
  1945. };
  1946. static inline u64 RVU_VF_INT_ENA_W1C(void)
  1947. __attribute__ ((pure, always_inline));
  1948. static inline u64 RVU_VF_INT_ENA_W1C(void)
  1949. {
  1950. return 0x38;
  1951. }
  1952. /**
  1953. * Register (RVU_VF_BAR2) rvu_vf_int_ena_w1s
  1954. *
  1955. * RVU VF Interrupt Enable Set Register This register sets interrupt
  1956. * enable bits.
  1957. */
  1958. union rvu_vf_int_ena_w1s {
  1959. u64 u;
  1960. struct rvu_vf_int_ena_w1s_s {
  1961. u64 mbox : 1;
  1962. u64 reserved_1_63 : 63;
  1963. } s;
  1964. /* struct rvu_vf_int_ena_w1s_s cn; */
  1965. };
  1966. static inline u64 RVU_VF_INT_ENA_W1S(void)
  1967. __attribute__ ((pure, always_inline));
  1968. static inline u64 RVU_VF_INT_ENA_W1S(void)
  1969. {
  1970. return 0x30;
  1971. }
  1972. /**
  1973. * Register (RVU_VF_BAR2) rvu_vf_int_w1s
  1974. *
  1975. * RVU VF Interrupt Set Register This register sets interrupt bits.
  1976. */
  1977. union rvu_vf_int_w1s {
  1978. u64 u;
  1979. struct rvu_vf_int_w1s_s {
  1980. u64 mbox : 1;
  1981. u64 reserved_1_63 : 63;
  1982. } s;
  1983. /* struct rvu_vf_int_w1s_s cn; */
  1984. };
  1985. static inline u64 RVU_VF_INT_W1S(void)
  1986. __attribute__ ((pure, always_inline));
  1987. static inline u64 RVU_VF_INT_W1S(void)
  1988. {
  1989. return 0x28;
  1990. }
  1991. /**
  1992. * Register (RVU_VF_BAR2) rvu_vf_msix_pba#
  1993. *
  1994. * RVU VF MSI-X Pending-Bit-Array Registers This register is the MSI-X VF
  1995. * PBA table.
  1996. */
  1997. union rvu_vf_msix_pbax {
  1998. u64 u;
  1999. struct rvu_vf_msix_pbax_s {
  2000. u64 pend : 64;
  2001. } s;
  2002. /* struct rvu_vf_msix_pbax_s cn; */
  2003. };
  2004. static inline u64 RVU_VF_MSIX_PBAX(u64 a)
  2005. __attribute__ ((pure, always_inline));
  2006. static inline u64 RVU_VF_MSIX_PBAX(u64 a)
  2007. {
  2008. return 0xf0000 + 8 * a;
  2009. }
  2010. /**
  2011. * Register (RVU_VF_BAR2) rvu_vf_msix_vec#_addr
  2012. *
  2013. * RVU VF MSI-X Vector-Table Address Registers These registers and
  2014. * RVU_VF_MSIX_VEC()_CTL form the VF MSI-X vector table. The number of
  2015. * MSI-X vectors for a given VF is specified by
  2016. * RVU_PRIV_PF()_MSIX_CFG[VF_MSIXT_SIZEM1] (plus 1). Software must do a
  2017. * read after any writes to the MSI-X vector table to ensure that the
  2018. * writes have completed before interrupts are generated to the modified
  2019. * vectors.
  2020. */
  2021. union rvu_vf_msix_vecx_addr {
  2022. u64 u;
  2023. struct rvu_vf_msix_vecx_addr_s {
  2024. u64 secvec : 1;
  2025. u64 reserved_1 : 1;
  2026. u64 addr : 51;
  2027. u64 reserved_53_63 : 11;
  2028. } s;
  2029. /* struct rvu_vf_msix_vecx_addr_s cn; */
  2030. };
  2031. static inline u64 RVU_VF_MSIX_VECX_ADDR(u64 a)
  2032. __attribute__ ((pure, always_inline));
  2033. static inline u64 RVU_VF_MSIX_VECX_ADDR(u64 a)
  2034. {
  2035. return 0x80000 + 0x10 * a;
  2036. }
  2037. /**
  2038. * Register (RVU_VF_BAR2) rvu_vf_msix_vec#_ctl
  2039. *
  2040. * RVU VF MSI-X Vector-Table Control and Data Registers These registers
  2041. * and RVU_VF_MSIX_VEC()_ADDR form the VF MSI-X vector table.
  2042. */
  2043. union rvu_vf_msix_vecx_ctl {
  2044. u64 u;
  2045. struct rvu_vf_msix_vecx_ctl_s {
  2046. u64 data : 32;
  2047. u64 mask : 1;
  2048. u64 reserved_33_63 : 31;
  2049. } s;
  2050. /* struct rvu_vf_msix_vecx_ctl_s cn; */
  2051. };
  2052. static inline u64 RVU_VF_MSIX_VECX_CTL(u64 a)
  2053. __attribute__ ((pure, always_inline));
  2054. static inline u64 RVU_VF_MSIX_VECX_CTL(u64 a)
  2055. {
  2056. return 0x80008 + 0x10 * a;
  2057. }
  2058. /**
  2059. * Register (RVU_VF_BAR2) rvu_vf_vfpf_mbox#
  2060. *
  2061. * RVU VF/PF Mailbox Registers
  2062. */
  2063. union rvu_vf_vfpf_mboxx {
  2064. u64 u;
  2065. struct rvu_vf_vfpf_mboxx_s {
  2066. u64 data : 64;
  2067. } s;
  2068. /* struct rvu_vf_vfpf_mboxx_s cn; */
  2069. };
  2070. static inline u64 RVU_VF_VFPF_MBOXX(u64 a)
  2071. __attribute__ ((pure, always_inline));
  2072. static inline u64 RVU_VF_VFPF_MBOXX(u64 a)
  2073. {
  2074. return 0 + 8 * a;
  2075. }
  2076. #endif /* __CSRS_RVU_H__ */