csrs-nix.h 303 KB

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  1. /* SPDX-License-Identifier: GPL-2.0
  2. *
  3. * Copyright (C) 2020 Marvell International Ltd.
  4. *
  5. * https://spdx.org/licenses
  6. */
  7. #ifndef __CSRS_NIX_H__
  8. #define __CSRS_NIX_H__
  9. /**
  10. * @file
  11. *
  12. * Configuration and status register (CSR) address and type definitions for
  13. * NIX.
  14. *
  15. * This file is auto generated. Do not edit.
  16. *
  17. */
  18. /**
  19. * Enumeration nix_af_int_vec_e
  20. *
  21. * NIX Admin Function Interrupt Vector Enumeration Enumerates the NIX AF
  22. * MSI-X interrupt vectors.
  23. */
  24. #define NIX_AF_INT_VEC_E_AF_ERR (3)
  25. #define NIX_AF_INT_VEC_E_AQ_DONE (2)
  26. #define NIX_AF_INT_VEC_E_GEN (1)
  27. #define NIX_AF_INT_VEC_E_POISON (4)
  28. #define NIX_AF_INT_VEC_E_RVU (0)
  29. /**
  30. * Enumeration nix_aq_comp_e
  31. *
  32. * NIX Completion Enumeration Enumerates the values of
  33. * NIX_AQ_RES_S[COMPCODE].
  34. */
  35. #define NIX_AQ_COMP_E_CTX_FAULT (4)
  36. #define NIX_AQ_COMP_E_CTX_POISON (3)
  37. #define NIX_AQ_COMP_E_GOOD (1)
  38. #define NIX_AQ_COMP_E_LOCKERR (5)
  39. #define NIX_AQ_COMP_E_NOTDONE (0)
  40. #define NIX_AQ_COMP_E_SQB_ALLOC_FAIL (6)
  41. #define NIX_AQ_COMP_E_SWERR (2)
  42. /**
  43. * Enumeration nix_aq_ctype_e
  44. *
  45. * NIX Context Type Enumeration Enumerates NIX_AQ_INST_S[CTYPE] values.
  46. */
  47. #define NIX_AQ_CTYPE_E_CQ (2)
  48. #define NIX_AQ_CTYPE_E_DYNO (5)
  49. #define NIX_AQ_CTYPE_E_MCE (3)
  50. #define NIX_AQ_CTYPE_E_RQ (0)
  51. #define NIX_AQ_CTYPE_E_RSS (4)
  52. #define NIX_AQ_CTYPE_E_SQ (1)
  53. /**
  54. * Enumeration nix_aq_instop_e
  55. *
  56. * NIX Admin Queue Opcode Enumeration Enumerates NIX_AQ_INST_S[OP]
  57. * values.
  58. */
  59. #define NIX_AQ_INSTOP_E_INIT (1)
  60. #define NIX_AQ_INSTOP_E_LOCK (4)
  61. #define NIX_AQ_INSTOP_E_NOP (0)
  62. #define NIX_AQ_INSTOP_E_READ (3)
  63. #define NIX_AQ_INSTOP_E_UNLOCK (5)
  64. #define NIX_AQ_INSTOP_E_WRITE (2)
  65. /**
  66. * Enumeration nix_chan_e
  67. *
  68. * NIX Channel Number Enumeration Enumerates the receive and transmit
  69. * channels, and values of NIX_RX_PARSE_S[CHAN],
  70. * NIX_SQ_CTX_S[DEFAULT_CHAN]. CNXXXX implements a subset of these
  71. * channels. Specifically, only channels for links enumerated by
  72. * NIX_LINK_E are implemented. Internal: P2X/X2P channel enumeration for
  73. * t9x.
  74. */
  75. #define NIX_CHAN_E_CGXX_LMACX_CHX(a, b, c) \
  76. (0x800 + 0x100 * (a) + 0x10 * (b) + (c))
  77. #define NIX_CHAN_E_LBKX_CHX(a, b) (0 + 0x100 * (a) + (b))
  78. #define NIX_CHAN_E_RX(a) (0 + 0x100 * (a))
  79. #define NIX_CHAN_E_SDP_CHX(a) (0x700 + (a))
  80. /**
  81. * Enumeration nix_colorresult_e
  82. *
  83. * NIX Color Result Enumeration Enumerates the values of
  84. * NIX_MEM_RESULT_S[COLOR], NIX_AF_TL1()_MD_DEBUG1[COLOR] and
  85. * NIX_AF_TL1()_MD_DEBUG1[COLOR].
  86. */
  87. #define NIX_COLORRESULT_E_GREEN (0)
  88. #define NIX_COLORRESULT_E_RED_DROP (3)
  89. #define NIX_COLORRESULT_E_RED_SEND (2)
  90. #define NIX_COLORRESULT_E_YELLOW (1)
  91. /**
  92. * Enumeration nix_cqerrint_e
  93. *
  94. * NIX Completion Queue Interrupt Enumeration Enumerates the bit index of
  95. * NIX_CQ_CTX_S[CQ_ERR_INT,CQ_ERR_INT_ENA].
  96. */
  97. #define NIX_CQERRINT_E_CQE_FAULT (2)
  98. #define NIX_CQERRINT_E_DOOR_ERR (0)
  99. #define NIX_CQERRINT_E_WR_FULL (1)
  100. /**
  101. * Enumeration nix_intf_e
  102. *
  103. * NIX Interface Number Enumeration Enumerates the bit index of
  104. * NIX_AF_STATUS[CALIBRATE_STATUS].
  105. */
  106. #define NIX_INTF_E_CGXX(a) (0 + (a))
  107. #define NIX_INTF_E_LBKX(a) (3 + (a))
  108. #define NIX_INTF_E_SDP (4)
  109. /**
  110. * Enumeration nix_lf_int_vec_e
  111. *
  112. * NIX Local Function Interrupt Vector Enumeration Enumerates the NIX
  113. * MSI-X interrupt vectors per LF.
  114. */
  115. #define NIX_LF_INT_VEC_E_CINTX(a) (0x40 + (a))
  116. #define NIX_LF_INT_VEC_E_ERR_INT (0x81)
  117. #define NIX_LF_INT_VEC_E_GINT (0x80)
  118. #define NIX_LF_INT_VEC_E_POISON (0x82)
  119. #define NIX_LF_INT_VEC_E_QINTX(a) (0 + (a))
  120. /**
  121. * Enumeration nix_link_e
  122. *
  123. * NIX Link Number Enumeration Enumerates the receive and transmit links,
  124. * and LINK index of NIX_AF_RX_LINK()_CFG, NIX_AF_RX_LINK()_WRR_CFG,
  125. * NIX_AF_TX_LINK()_NORM_CREDIT, NIX_AF_TX_LINK()_HW_XOFF and
  126. * NIX_AF_TL3_TL2()_LINK()_CFG.
  127. */
  128. #define NIX_LINK_E_CGXX_LMACX(a, b) (0 + 4 * (a) + (b))
  129. #define NIX_LINK_E_LBKX(a) (0xc + (a))
  130. #define NIX_LINK_E_MC (0xe)
  131. #define NIX_LINK_E_SDP (0xd)
  132. /**
  133. * Enumeration nix_lsoalg_e
  134. *
  135. * NIX Large Send Offload Algorithm Enumeration Enumerates
  136. * NIX_AF_LSO_FORMAT()_FIELD()[ALG] values. Specifies algorithm for
  137. * modifying the associated LSO packet field.
  138. */
  139. #define NIX_LSOALG_E_ADD_OFFSET (3)
  140. #define NIX_LSOALG_E_ADD_PAYLEN (2)
  141. #define NIX_LSOALG_E_ADD_SEGNUM (1)
  142. #define NIX_LSOALG_E_NOP (0)
  143. #define NIX_LSOALG_E_TCP_FLAGS (4)
  144. /**
  145. * Enumeration nix_maxsqesz_e
  146. *
  147. * NIX Maximum SQE Size Enumeration Enumerates the values of
  148. * NIX_SQ_CTX_S[MAX_SQE_SIZE].
  149. */
  150. #define NIX_MAXSQESZ_E_W16 (0)
  151. #define NIX_MAXSQESZ_E_W8 (1)
  152. /**
  153. * Enumeration nix_mdtype_e
  154. *
  155. * NIX Meta Descriptor Type Enumeration Enumerates values of
  156. * NIX_AF_MDQ()_MD_DEBUG[MD_TYPE].
  157. */
  158. #define NIX_MDTYPE_E_FLUSH (1)
  159. #define NIX_MDTYPE_E_PMD (2)
  160. #define NIX_MDTYPE_E_RSVD (0)
  161. /**
  162. * Enumeration nix_mnqerr_e
  163. *
  164. * NIX Meta-Descriptor Enqueue Error Enumeration Enumerates
  165. * NIX_LF_MNQ_ERR_DBG[ERRCODE] values.
  166. */
  167. #define NIX_MNQERR_E_CQ_QUERY_ERR (6)
  168. #define NIX_MNQERR_E_LSO_ERR (5)
  169. #define NIX_MNQERR_E_MAXLEN_ERR (8)
  170. #define NIX_MNQERR_E_MAX_SQE_SIZE_ERR (7)
  171. #define NIX_MNQERR_E_SQB_FAULT (2)
  172. #define NIX_MNQERR_E_SQB_POISON (3)
  173. #define NIX_MNQERR_E_SQE_SIZEM1_ZERO (9)
  174. #define NIX_MNQERR_E_SQ_CTX_FAULT (0)
  175. #define NIX_MNQERR_E_SQ_CTX_POISON (1)
  176. #define NIX_MNQERR_E_TOTAL_ERR (4)
  177. /**
  178. * Enumeration nix_ndc_rx_port_e
  179. *
  180. * NIX Receive NDC Port Enumeration Enumerates NIX receive NDC
  181. * (NDC_IDX_E::NIX()_RX) ports and the PORT index of
  182. * NDC_AF_PORT()_RT()_RW()_REQ_PC and NDC_AF_PORT()_RT()_RW()_LAT_PC.
  183. */
  184. #define NIX_NDC_RX_PORT_E_AQ (0)
  185. #define NIX_NDC_RX_PORT_E_CINT (2)
  186. #define NIX_NDC_RX_PORT_E_CQ (1)
  187. #define NIX_NDC_RX_PORT_E_MC (3)
  188. #define NIX_NDC_RX_PORT_E_PKT (4)
  189. #define NIX_NDC_RX_PORT_E_RQ (5)
  190. /**
  191. * Enumeration nix_ndc_tx_port_e
  192. *
  193. * NIX Transmit NDC Port Enumeration Enumerates NIX transmit NDC
  194. * (NDC_IDX_E::NIX()_TX) ports and the PORT index of
  195. * NDC_AF_PORT()_RT()_RW()_REQ_PC and NDC_AF_PORT()_RT()_RW()_LAT_PC.
  196. */
  197. #define NIX_NDC_TX_PORT_E_DEQ (3)
  198. #define NIX_NDC_TX_PORT_E_DMA (4)
  199. #define NIX_NDC_TX_PORT_E_ENQ (1)
  200. #define NIX_NDC_TX_PORT_E_LMT (0)
  201. #define NIX_NDC_TX_PORT_E_MNQ (2)
  202. #define NIX_NDC_TX_PORT_E_XQE (5)
  203. /**
  204. * Enumeration nix_re_opcode_e
  205. *
  206. * NIX Receive Error Opcode Enumeration Enumerates
  207. * NIX_RX_PARSE_S[ERRCODE] values when NIX_RX_PARSE_S[ERRLEV] =
  208. * NPC_ERRLEV_E::RE.
  209. */
  210. #define NIX_RE_OPCODE_E_OL2_LENMISM (0x12)
  211. #define NIX_RE_OPCODE_E_OVERSIZE (0x11)
  212. #define NIX_RE_OPCODE_E_RE_DMAPKT (0xf)
  213. #define NIX_RE_OPCODE_E_RE_FCS (7)
  214. #define NIX_RE_OPCODE_E_RE_FCS_RCV (8)
  215. #define NIX_RE_OPCODE_E_RE_JABBER (2)
  216. #define NIX_RE_OPCODE_E_RE_NONE (0)
  217. #define NIX_RE_OPCODE_E_RE_PARTIAL (1)
  218. #define NIX_RE_OPCODE_E_RE_RX_CTL (0xb)
  219. #define NIX_RE_OPCODE_E_RE_SKIP (0xc)
  220. #define NIX_RE_OPCODE_E_RE_TERMINATE (9)
  221. #define NIX_RE_OPCODE_E_UNDERSIZE (0x10)
  222. /**
  223. * Enumeration nix_redalg_e
  224. *
  225. * NIX Red Algorithm Enumeration Enumerates the different algorithms of
  226. * NIX_SEND_EXT_S[SHP_RA].
  227. */
  228. #define NIX_REDALG_E_DISCARD (3)
  229. #define NIX_REDALG_E_SEND (1)
  230. #define NIX_REDALG_E_STALL (2)
  231. #define NIX_REDALG_E_STD (0)
  232. /**
  233. * Enumeration nix_rqint_e
  234. *
  235. * NIX Receive Queue Interrupt Enumeration Enumerates the bit index of
  236. * NIX_RQ_CTX_S[RQ_INT,RQ_INT_ENA].
  237. */
  238. #define NIX_RQINT_E_DROP (0)
  239. #define NIX_RQINT_E_RX(a) (0 + (a))
  240. #define NIX_RQINT_E_RED (1)
  241. /**
  242. * Enumeration nix_rx_actionop_e
  243. *
  244. * NIX Receive Action Opcode Enumeration Enumerates the values of
  245. * NIX_RX_ACTION_S[OP].
  246. */
  247. #define NIX_RX_ACTIONOP_E_DROP (0)
  248. #define NIX_RX_ACTIONOP_E_MCAST (3)
  249. #define NIX_RX_ACTIONOP_E_MIRROR (6)
  250. #define NIX_RX_ACTIONOP_E_PF_FUNC_DROP (5)
  251. #define NIX_RX_ACTIONOP_E_RSS (4)
  252. #define NIX_RX_ACTIONOP_E_UCAST (1)
  253. #define NIX_RX_ACTIONOP_E_UCAST_IPSEC (2)
  254. /**
  255. * Enumeration nix_rx_mcop_e
  256. *
  257. * NIX Receive Multicast/Mirror Opcode Enumeration Enumerates the values
  258. * of NIX_RX_MCE_S[OP].
  259. */
  260. #define NIX_RX_MCOP_E_RQ (0)
  261. #define NIX_RX_MCOP_E_RSS (1)
  262. /**
  263. * Enumeration nix_rx_perrcode_e
  264. *
  265. * NIX Receive Protocol Error Code Enumeration Enumerates
  266. * NIX_RX_PARSE_S[ERRCODE] values when NIX_RX_PARSE_S[ERRLEV] =
  267. * NPC_ERRLEV_E::NIX.
  268. */
  269. #define NIX_RX_PERRCODE_E_BUFS_OFLOW (0xa)
  270. #define NIX_RX_PERRCODE_E_DATA_FAULT (8)
  271. #define NIX_RX_PERRCODE_E_IL3_LEN (0x20)
  272. #define NIX_RX_PERRCODE_E_IL4_CHK (0x22)
  273. #define NIX_RX_PERRCODE_E_IL4_LEN (0x21)
  274. #define NIX_RX_PERRCODE_E_IL4_PORT (0x23)
  275. #define NIX_RX_PERRCODE_E_MCAST_FAULT (4)
  276. #define NIX_RX_PERRCODE_E_MCAST_POISON (6)
  277. #define NIX_RX_PERRCODE_E_MEMOUT (9)
  278. #define NIX_RX_PERRCODE_E_MIRROR_FAULT (5)
  279. #define NIX_RX_PERRCODE_E_MIRROR_POISON (7)
  280. #define NIX_RX_PERRCODE_E_NPC_RESULT_ERR (2)
  281. #define NIX_RX_PERRCODE_E_OL3_LEN (0x10)
  282. #define NIX_RX_PERRCODE_E_OL4_CHK (0x12)
  283. #define NIX_RX_PERRCODE_E_OL4_LEN (0x11)
  284. #define NIX_RX_PERRCODE_E_OL4_PORT (0x13)
  285. /**
  286. * Enumeration nix_send_status_e
  287. *
  288. * NIX Send Completion Status Enumeration Enumerates values of
  289. * NIX_SEND_COMP_S[STATUS] and NIX_LF_SEND_ERR_DBG[ERRCODE].
  290. */
  291. #define NIX_SEND_STATUS_E_DATA_FAULT (0x16)
  292. #define NIX_SEND_STATUS_E_DATA_POISON (0x17)
  293. #define NIX_SEND_STATUS_E_GOOD (0)
  294. #define NIX_SEND_STATUS_E_INVALID_SUBDC (0x14)
  295. #define NIX_SEND_STATUS_E_JUMP_FAULT (7)
  296. #define NIX_SEND_STATUS_E_JUMP_POISON (8)
  297. #define NIX_SEND_STATUS_E_LOCK_VIOL (0x21)
  298. #define NIX_SEND_STATUS_E_NPC_DROP_ACTION (0x20)
  299. #define NIX_SEND_STATUS_E_NPC_MCAST_ABORT (0x24)
  300. #define NIX_SEND_STATUS_E_NPC_MCAST_CHAN_ERR (0x23)
  301. #define NIX_SEND_STATUS_E_NPC_UCAST_CHAN_ERR (0x22)
  302. #define NIX_SEND_STATUS_E_NPC_VTAG_PTR_ERR (0x25)
  303. #define NIX_SEND_STATUS_E_NPC_VTAG_SIZE_ERR (0x26)
  304. #define NIX_SEND_STATUS_E_SEND_CRC_ERR (0x10)
  305. #define NIX_SEND_STATUS_E_SEND_EXT_ERR (6)
  306. #define NIX_SEND_STATUS_E_SEND_HDR_ERR (5)
  307. #define NIX_SEND_STATUS_E_SEND_IMM_ERR (0x11)
  308. #define NIX_SEND_STATUS_E_SEND_MEM_ERR (0x13)
  309. #define NIX_SEND_STATUS_E_SEND_MEM_FAULT (0x27)
  310. #define NIX_SEND_STATUS_E_SEND_SG_ERR (0x12)
  311. #define NIX_SEND_STATUS_E_SQB_FAULT (3)
  312. #define NIX_SEND_STATUS_E_SQB_POISON (4)
  313. #define NIX_SEND_STATUS_E_SQ_CTX_FAULT (1)
  314. #define NIX_SEND_STATUS_E_SQ_CTX_POISON (2)
  315. #define NIX_SEND_STATUS_E_SUBDC_ORDER_ERR (0x15)
  316. /**
  317. * Enumeration nix_sendcrcalg_e
  318. *
  319. * NIX Send CRC Algorithm Enumeration Enumerates the CRC algorithm used,
  320. * see NIX_SEND_CRC_S[ALG].
  321. */
  322. #define NIX_SENDCRCALG_E_CRC32 (0)
  323. #define NIX_SENDCRCALG_E_CRC32C (1)
  324. #define NIX_SENDCRCALG_E_ONES16 (2)
  325. /**
  326. * Enumeration nix_sendl3type_e
  327. *
  328. * NIX Send Layer 3 Header Type Enumeration Enumerates values of
  329. * NIX_SEND_HDR_S[OL3TYPE], NIX_SEND_HDR_S[IL3TYPE]. Internal: Encoding
  330. * matches DPDK TX IP types: \<pre\> PKT_TX_IP_CKSUM (1ULL \<\< 54)
  331. * PKT_TX_IPV4 (1ULL \<\< 55) PKT_TX_IPV6 (1ULL \<\<
  332. * 56) PKT_TX_OUTER_IP_CKSUM(1ULL \<\< 58) PKT_TX_OUTER_IPV4 (1ULL
  333. * \<\< 59) PKT_TX_OUTER_IPV6 (1ULL \<\< 60) \</pre\>
  334. */
  335. #define NIX_SENDL3TYPE_E_IP4 (2)
  336. #define NIX_SENDL3TYPE_E_IP4_CKSUM (3)
  337. #define NIX_SENDL3TYPE_E_IP6 (4)
  338. #define NIX_SENDL3TYPE_E_NONE (0)
  339. /**
  340. * Enumeration nix_sendl4type_e
  341. *
  342. * NIX Send Layer 4 Header Type Enumeration Enumerates values of
  343. * NIX_SEND_HDR_S[OL4TYPE], NIX_SEND_HDR_S[IL4TYPE]. Internal: Encoding
  344. * matches DPDK TX L4 types. \<pre\> PKT_TX_L4_NO_CKSUM (0ULL \<\< 52)
  345. * // Disable L4 cksum of TX pkt. PKT_TX_TCP_CKSUM (1ULL \<\< 52) //
  346. * TCP cksum of TX pkt. computed by nic. PKT_TX_SCTP_CKSUM (2ULL \<\<
  347. * 52) // SCTP cksum of TX pkt. computed by nic. PKT_TX_UDP_CKSUM
  348. * (3ULL \<\< 52) // UDP cksum of TX pkt. computed by nic. \</pre\>
  349. */
  350. #define NIX_SENDL4TYPE_E_NONE (0)
  351. #define NIX_SENDL4TYPE_E_SCTP_CKSUM (2)
  352. #define NIX_SENDL4TYPE_E_TCP_CKSUM (1)
  353. #define NIX_SENDL4TYPE_E_UDP_CKSUM (3)
  354. /**
  355. * Enumeration nix_sendldtype_e
  356. *
  357. * NIX Send Load Type Enumeration Enumerates the load transaction types
  358. * for reading segment bytes specified by NIX_SEND_SG_S[LD_TYPE] and
  359. * NIX_SEND_JUMP_S[LD_TYPE]. Internal: The hardware implementation
  360. * treats undefined encodings as LDD load type.
  361. */
  362. #define NIX_SENDLDTYPE_E_LDD (0)
  363. #define NIX_SENDLDTYPE_E_LDT (1)
  364. #define NIX_SENDLDTYPE_E_LDWB (2)
  365. /**
  366. * Enumeration nix_sendmemalg_e
  367. *
  368. * NIX Memory Modify Algorithm Enumeration Enumerates the different
  369. * algorithms for modifying memory; see NIX_SEND_MEM_S[ALG]. mbufs_freed
  370. * is the number of gather buffers freed to NPA for the send descriptor.
  371. * See NIX_SEND_HDR_S[DF] and NIX_SEND_SG_S[I*].
  372. */
  373. #define NIX_SENDMEMALG_E_ADD (8)
  374. #define NIX_SENDMEMALG_E_ADDLEN (0xa)
  375. #define NIX_SENDMEMALG_E_ADDMBUF (0xc)
  376. #define NIX_SENDMEMALG_E_SET (0)
  377. #define NIX_SENDMEMALG_E_SETRSLT (2)
  378. #define NIX_SENDMEMALG_E_SETTSTMP (1)
  379. #define NIX_SENDMEMALG_E_SUB (9)
  380. #define NIX_SENDMEMALG_E_SUBLEN (0xb)
  381. #define NIX_SENDMEMALG_E_SUBMBUF (0xd)
  382. /**
  383. * Enumeration nix_sendmemdsz_e
  384. *
  385. * NIX Memory Data Size Enumeration Enumerates the datum size for
  386. * modifying memory; see NIX_SEND_MEM_S[DSZ].
  387. */
  388. #define NIX_SENDMEMDSZ_E_B16 (2)
  389. #define NIX_SENDMEMDSZ_E_B32 (1)
  390. #define NIX_SENDMEMDSZ_E_B64 (0)
  391. #define NIX_SENDMEMDSZ_E_B8 (3)
  392. /**
  393. * Enumeration nix_sqint_e
  394. *
  395. * NIX Send Queue Interrupt Enumeration Enumerates the bit index of
  396. * NIX_SQ_CTX_S[SQ_INT,SQ_INT_ENA].
  397. */
  398. #define NIX_SQINT_E_LMT_ERR (0)
  399. #define NIX_SQINT_E_MNQ_ERR (1)
  400. #define NIX_SQINT_E_SEND_ERR (2)
  401. #define NIX_SQINT_E_SQB_ALLOC_FAIL (3)
  402. /**
  403. * Enumeration nix_sqoperr_e
  404. *
  405. * NIX SQ Operation Error Enumeration Enumerates
  406. * NIX_LF_SQ_OP_ERR_DBG[ERRCODE] values.
  407. */
  408. #define NIX_SQOPERR_E_MAX_SQE_SIZE_ERR (4)
  409. #define NIX_SQOPERR_E_SQB_FAULT (7)
  410. #define NIX_SQOPERR_E_SQB_NULL (6)
  411. #define NIX_SQOPERR_E_SQE_OFLOW (5)
  412. #define NIX_SQOPERR_E_SQE_SIZEM1_ZERO (8)
  413. #define NIX_SQOPERR_E_SQ_CTX_FAULT (1)
  414. #define NIX_SQOPERR_E_SQ_CTX_POISON (2)
  415. #define NIX_SQOPERR_E_SQ_DISABLED (3)
  416. #define NIX_SQOPERR_E_SQ_OOR (0)
  417. /**
  418. * Enumeration nix_stat_lf_rx_e
  419. *
  420. * NIX Local Function Receive Statistics Enumeration Enumerates the last
  421. * index of NIX_AF_LF()_RX_STAT() and NIX_LF_RX_STAT().
  422. */
  423. #define NIX_STAT_LF_RX_E_RX_BCAST (2)
  424. #define NIX_STAT_LF_RX_E_RX_DROP (4)
  425. #define NIX_STAT_LF_RX_E_RX_DROP_OCTS (5)
  426. #define NIX_STAT_LF_RX_E_RX_DRP_BCAST (8)
  427. #define NIX_STAT_LF_RX_E_RX_DRP_L3BCAST (0xa)
  428. #define NIX_STAT_LF_RX_E_RX_DRP_L3MCAST (0xb)
  429. #define NIX_STAT_LF_RX_E_RX_DRP_MCAST (9)
  430. #define NIX_STAT_LF_RX_E_RX_ERR (7)
  431. #define NIX_STAT_LF_RX_E_RX_FCS (6)
  432. #define NIX_STAT_LF_RX_E_RX_MCAST (3)
  433. #define NIX_STAT_LF_RX_E_RX_OCTS (0)
  434. #define NIX_STAT_LF_RX_E_RX_UCAST (1)
  435. /**
  436. * Enumeration nix_stat_lf_tx_e
  437. *
  438. * NIX Local Function Transmit Statistics Enumeration Enumerates the
  439. * index of NIX_AF_LF()_TX_STAT() and NIX_LF_TX_STAT(). These statistics
  440. * do not account for packet replication due to NIX_TX_ACTION_S[OP] =
  441. * NIX_TX_ACTIONOP_E::MCAST.
  442. */
  443. #define NIX_STAT_LF_TX_E_TX_BCAST (1)
  444. #define NIX_STAT_LF_TX_E_TX_DROP (3)
  445. #define NIX_STAT_LF_TX_E_TX_MCAST (2)
  446. #define NIX_STAT_LF_TX_E_TX_OCTS (4)
  447. #define NIX_STAT_LF_TX_E_TX_UCAST (0)
  448. /**
  449. * Enumeration nix_stype_e
  450. *
  451. * NIX SQB Caching Type Enumeration Enumerates the values of
  452. * NIX_SQ_CTX_S[SQE_STYPE].
  453. */
  454. #define NIX_STYPE_E_STF (0)
  455. #define NIX_STYPE_E_STP (2)
  456. #define NIX_STYPE_E_STT (1)
  457. /**
  458. * Enumeration nix_subdc_e
  459. *
  460. * NIX Subdescriptor Operation Enumeration Enumerates send and receive
  461. * subdescriptor codes. The codes differentiate subdescriptors within a
  462. * NIX send or receive descriptor, excluding NIX_SEND_HDR_S for send and
  463. * NIX_CQE_HDR_S/NIX_WQE_HDR_S for receive, which are determined by their
  464. * position as the first subdescriptor, and NIX_RX_PARSE_S, which is
  465. * determined by its position as the second subdescriptor.
  466. */
  467. #define NIX_SUBDC_E_CRC (2)
  468. #define NIX_SUBDC_E_EXT (1)
  469. #define NIX_SUBDC_E_IMM (3)
  470. #define NIX_SUBDC_E_JUMP (6)
  471. #define NIX_SUBDC_E_MEM (5)
  472. #define NIX_SUBDC_E_NOP (0)
  473. #define NIX_SUBDC_E_SG (4)
  474. #define NIX_SUBDC_E_SOD (0xf)
  475. #define NIX_SUBDC_E_WORK (7)
  476. /**
  477. * Enumeration nix_tx_actionop_e
  478. *
  479. * NIX Transmit Action Opcode Enumeration Enumerates the values of
  480. * NIX_TX_ACTION_S[OP].
  481. */
  482. #define NIX_TX_ACTIONOP_E_DROP (0)
  483. #define NIX_TX_ACTIONOP_E_DROP_VIOL (5)
  484. #define NIX_TX_ACTIONOP_E_MCAST (3)
  485. #define NIX_TX_ACTIONOP_E_UCAST_CHAN (2)
  486. #define NIX_TX_ACTIONOP_E_UCAST_DEFAULT (1)
  487. /**
  488. * Enumeration nix_tx_vtagop_e
  489. *
  490. * NIX Transmit Vtag Opcode Enumeration Enumerates the values of
  491. * NIX_TX_VTAG_ACTION_S[VTAG0_OP,VTAG1_OP].
  492. */
  493. #define NIX_TX_VTAGOP_E_INSERT (1)
  494. #define NIX_TX_VTAGOP_E_NOP (0)
  495. #define NIX_TX_VTAGOP_E_REPLACE (2)
  496. /**
  497. * Enumeration nix_txlayer_e
  498. *
  499. * NIX Transmit Layer Enumeration Enumerates the values of
  500. * NIX_AF_LSO_FORMAT()_FIELD()[LAYER].
  501. */
  502. #define NIX_TXLAYER_E_IL3 (2)
  503. #define NIX_TXLAYER_E_IL4 (3)
  504. #define NIX_TXLAYER_E_OL3 (0)
  505. #define NIX_TXLAYER_E_OL4 (1)
  506. /**
  507. * Enumeration nix_vtagsize_e
  508. *
  509. * NIX Vtag Size Enumeration Enumerates the values of
  510. * NIX_AF_TX_VTAG_DEF()_CTL[SIZE] and NIX_AF_LF()_RX_VTAG_TYPE()[SIZE].
  511. */
  512. #define NIX_VTAGSIZE_E_T4 (0)
  513. #define NIX_VTAGSIZE_E_T8 (1)
  514. /**
  515. * Enumeration nix_xqe_type_e
  516. *
  517. * NIX WQE/CQE Type Enumeration Enumerates the values of
  518. * NIX_WQE_HDR_S[WQE_TYPE], NIX_CQE_HDR_S[CQE_TYPE].
  519. */
  520. #define NIX_XQE_TYPE_E_INVALID (0)
  521. #define NIX_XQE_TYPE_E_RX (1)
  522. #define NIX_XQE_TYPE_E_RX_IPSECD (4)
  523. #define NIX_XQE_TYPE_E_RX_IPSECH (3)
  524. #define NIX_XQE_TYPE_E_RX_IPSECS (2)
  525. #define NIX_XQE_TYPE_E_SEND (8)
  526. /**
  527. * Enumeration nix_xqesz_e
  528. *
  529. * NIX WQE/CQE Size Enumeration Enumerates the values of
  530. * NIX_AF_LF()_CFG[XQE_SIZE].
  531. */
  532. #define NIX_XQESZ_E_W16 (1)
  533. #define NIX_XQESZ_E_W64 (0)
  534. /**
  535. * Structure nix_aq_inst_s
  536. *
  537. * NIX Admin Queue Instruction Structure This structure specifies the AQ
  538. * instruction. Instructions and associated software structures are
  539. * stored in memory as little-endian unless NIX_AF_CFG[AF_BE] is set.
  540. * Hardware reads of NIX_AQ_INST_S do not allocate into LLC. Hardware
  541. * reads and writes of the context structure selected by [CTYPE], [LF]
  542. * and [CINDEX] use the NDC and LLC caching style configured for that
  543. * context. For example: * When [CTYPE] = NIX_AQ_CTYPE_E::RQ: use
  544. * NIX_AF_LF()_RSS_CFG[CACHING] and NIX_AF_LF()_RSS_CFG[WAY_MASK]. * When
  545. * [CTYPE] = NIX_AQ_CTYPE_E::MCE: use NIX_AF_RX_MCAST_CFG[CACHING] and
  546. * NIX_AF_RX_MCAST_CFG[WAY_MASK].
  547. */
  548. union nix_aq_inst_s {
  549. u64 u[2];
  550. struct nix_aq_inst_s_s {
  551. u64 op : 4;
  552. u64 ctype : 4;
  553. u64 lf : 7;
  554. u64 reserved_15_23 : 9;
  555. u64 cindex : 20;
  556. u64 reserved_44_62 : 19;
  557. u64 doneint : 1;
  558. u64 res_addr : 64;
  559. } s;
  560. /* struct nix_aq_inst_s_s cn; */
  561. };
  562. /**
  563. * Structure nix_aq_res_s
  564. *
  565. * NIX Admin Queue Result Structure NIX writes this structure after it
  566. * completes the NIX_AQ_INST_S instruction. The result structure is
  567. * exactly 16 bytes, and each instruction completion produces exactly one
  568. * result structure. Results and associated software structures are
  569. * stored in memory as little-endian unless NIX_AF_CFG[AF_BE] is set.
  570. * When [OP] = NIX_AQ_INSTOP_E::INIT, WRITE or READ, this structure is
  571. * immediately followed by context read or write data. See
  572. * NIX_AQ_INSTOP_E. Hardware writes of NIX_AQ_RES_S and context data
  573. * always allocate into LLC. Hardware reads of context data do not
  574. * allocate into LLC.
  575. */
  576. union nix_aq_res_s {
  577. u64 u[2];
  578. struct nix_aq_res_s_s {
  579. u64 op : 4;
  580. u64 ctype : 4;
  581. u64 compcode : 8;
  582. u64 doneint : 1;
  583. u64 reserved_17_63 : 47;
  584. u64 reserved_64_127 : 64;
  585. } s;
  586. /* struct nix_aq_res_s_s cn; */
  587. };
  588. /**
  589. * Structure nix_cint_hw_s
  590. *
  591. * NIX Completion Interrupt Context Hardware Structure This structure
  592. * contains context state maintained by hardware for each completion
  593. * interrupt (CINT) in NDC/LLC/DRAM. Software accesses this structure
  594. * with the NIX_LF_CINT()* registers. Hardware maintains a table of
  595. * NIX_AF_CONST2[CINTS] contiguous NIX_CINT_HW_S structures per LF
  596. * starting at AF IOVA NIX_AF_LF()_CINTS_BASE. Always stored in byte
  597. * invariant little-endian format (LE8).
  598. */
  599. union nix_cint_hw_s {
  600. u64 u[2];
  601. struct nix_cint_hw_s_s {
  602. u64 ecount : 32;
  603. u64 qcount : 16;
  604. u64 intr : 1;
  605. u64 ena : 1;
  606. u64 timer_idx : 8;
  607. u64 reserved_58_63 : 6;
  608. u64 ecount_wait : 32;
  609. u64 qcount_wait : 16;
  610. u64 time_wait : 8;
  611. u64 reserved_120_127 : 8;
  612. } s;
  613. /* struct nix_cint_hw_s_s cn; */
  614. };
  615. /**
  616. * Structure nix_cq_ctx_s
  617. *
  618. * NIX Completion Queue Context Structure This structure contains context
  619. * state maintained by hardware for each CQ in NDC/LLC/DRAM. Software
  620. * uses the same structure format to read and write an CQ context with
  621. * the NIX admin queue.
  622. */
  623. union nix_cq_ctx_s {
  624. u64 u[4];
  625. struct nix_cq_ctx_s_s {
  626. u64 base : 64;
  627. u64 reserved_64_67 : 4;
  628. u64 bp_ena : 1;
  629. u64 reserved_69_71 : 3;
  630. u64 bpid : 9;
  631. u64 reserved_81_83 : 3;
  632. u64 qint_idx : 7;
  633. u64 cq_err : 1;
  634. u64 cint_idx : 7;
  635. u64 avg_con : 9;
  636. u64 wrptr : 20;
  637. u64 tail : 20;
  638. u64 head : 20;
  639. u64 avg_level : 8;
  640. u64 update_time : 16;
  641. u64 bp : 8;
  642. u64 drop : 8;
  643. u64 drop_ena : 1;
  644. u64 ena : 1;
  645. u64 reserved_210_211 : 2;
  646. u64 substream : 20;
  647. u64 caching : 1;
  648. u64 reserved_233_235 : 3;
  649. u64 qsize : 4;
  650. u64 cq_err_int : 8;
  651. u64 cq_err_int_ena : 8;
  652. } s;
  653. /* struct nix_cq_ctx_s_s cn; */
  654. };
  655. /**
  656. * Structure nix_cqe_hdr_s
  657. *
  658. * NIX Completion Queue Entry Header Structure This 64-bit structure
  659. * defines the first word of every CQE. It is immediately followed by
  660. * NIX_RX_PARSE_S in a receive CQE, and by NIX_SEND_COMP_S in a send
  661. * completion CQE. Stored in memory as little-endian unless
  662. * NIX_AF_LF()_CFG[BE] is set.
  663. */
  664. union nix_cqe_hdr_s {
  665. u64 u;
  666. struct nix_cqe_hdr_s_s {
  667. u64 tag : 32;
  668. u64 q : 20;
  669. u64 reserved_52_57 : 6;
  670. u64 node : 2;
  671. u64 cqe_type : 4;
  672. } s;
  673. /* struct nix_cqe_hdr_s_s cn; */
  674. };
  675. /**
  676. * Structure nix_inst_hdr_s
  677. *
  678. * NIX Instruction Header Structure This structure defines the
  679. * instruction header that precedes the packet header supplied to NPC for
  680. * packets to be transmitted by NIX.
  681. */
  682. union nix_inst_hdr_s {
  683. u64 u;
  684. struct nix_inst_hdr_s_s {
  685. u64 pf_func : 16;
  686. u64 sq : 20;
  687. u64 reserved_36_63 : 28;
  688. } s;
  689. /* struct nix_inst_hdr_s_s cn; */
  690. };
  691. /**
  692. * Structure nix_iova_s
  693. *
  694. * NIX I/O Virtual Address Structure
  695. */
  696. union nix_iova_s {
  697. u64 u;
  698. struct nix_iova_s_s {
  699. u64 addr : 64;
  700. } s;
  701. /* struct nix_iova_s_s cn; */
  702. };
  703. /**
  704. * Structure nix_ipsec_dyno_s
  705. *
  706. * INTERNAL: NIX IPSEC Dynamic Ordering Counter Structure Internal: Not
  707. * used; no IPSEC fast-path.
  708. */
  709. union nix_ipsec_dyno_s {
  710. u32 u;
  711. struct nix_ipsec_dyno_s_s {
  712. u32 count : 32;
  713. } s;
  714. /* struct nix_ipsec_dyno_s_s cn; */
  715. };
  716. /**
  717. * Structure nix_mem_result_s
  718. *
  719. * NIX Memory Value Structure When
  720. * NIX_SEND_MEM_S[ALG]=NIX_SENDMEMALG_E::SETRSLT, the value written to
  721. * memory is formed with this structure.
  722. */
  723. union nix_mem_result_s {
  724. u64 u;
  725. struct nix_mem_result_s_s {
  726. u64 v : 1;
  727. u64 color : 2;
  728. u64 reserved_3_63 : 61;
  729. } s;
  730. /* struct nix_mem_result_s_s cn; */
  731. };
  732. /**
  733. * Structure nix_op_q_wdata_s
  734. *
  735. * NIX Statistics Operation Write Data Structure This structure specifies
  736. * the write data format of an atomic 64-bit load-and-add of some
  737. * NIX_LF_RQ_OP_*, NIX_LF_SQ_OP* and NIX_LF_CQ_OP* registers.
  738. */
  739. union nix_op_q_wdata_s {
  740. u64 u;
  741. struct nix_op_q_wdata_s_s {
  742. u64 reserved_0_31 : 32;
  743. u64 q : 20;
  744. u64 reserved_52_63 : 12;
  745. } s;
  746. /* struct nix_op_q_wdata_s_s cn; */
  747. };
  748. /**
  749. * Structure nix_qint_hw_s
  750. *
  751. * NIX Queue Interrupt Context Hardware Structure This structure contains
  752. * context state maintained by hardware for each queue interrupt (QINT)
  753. * in NDC/LLC/DRAM. Software accesses this structure with the
  754. * NIX_LF_QINT()* registers. Hardware maintains a table of
  755. * NIX_AF_CONST2[QINTS] contiguous NIX_QINT_HW_S structures per LF
  756. * starting at IOVA NIX_AF_LF()_QINTS_BASE. Always stored in byte
  757. * invariant little-endian format (LE8).
  758. */
  759. union nix_qint_hw_s {
  760. u32 u;
  761. struct nix_qint_hw_s_s {
  762. u32 count : 22;
  763. u32 reserved_22_30 : 9;
  764. u32 ena : 1;
  765. } s;
  766. /* struct nix_qint_hw_s_s cn; */
  767. };
  768. /**
  769. * Structure nix_rq_ctx_hw_s
  770. *
  771. * NIX Receive Queue Context Structure This structure contains context
  772. * state maintained by hardware for each RQ in NDC/LLC/DRAM. Software
  773. * uses the equivalent NIX_RQ_CTX_S structure format to read and write an
  774. * RQ context with the NIX admin queue. Always stored in byte invariant
  775. * little-endian format (LE8).
  776. */
  777. union nix_rq_ctx_hw_s {
  778. u64 u[16];
  779. struct nix_rq_ctx_hw_s_s {
  780. u64 ena : 1;
  781. u64 sso_ena : 1;
  782. u64 ipsech_ena : 1;
  783. u64 ena_wqwd : 1;
  784. u64 cq : 20;
  785. u64 substream : 20;
  786. u64 wqe_aura : 20;
  787. u64 spb_aura : 20;
  788. u64 lpb_aura : 20;
  789. u64 sso_grp : 10;
  790. u64 sso_tt : 2;
  791. u64 pb_caching : 2;
  792. u64 wqe_caching : 1;
  793. u64 xqe_drop_ena : 1;
  794. u64 spb_drop_ena : 1;
  795. u64 lpb_drop_ena : 1;
  796. u64 wqe_skip : 2;
  797. u64 reserved_124_127 : 4;
  798. u64 reserved_128_139 : 12;
  799. u64 spb_sizem1 : 6;
  800. u64 reserved_146_150 : 5;
  801. u64 spb_ena : 1;
  802. u64 lpb_sizem1 : 12;
  803. u64 first_skip : 7;
  804. u64 reserved_171 : 1;
  805. u64 later_skip : 6;
  806. u64 xqe_imm_size : 6;
  807. u64 reserved_184_189 : 6;
  808. u64 xqe_imm_copy : 1;
  809. u64 xqe_hdr_split : 1;
  810. u64 xqe_drop : 8;
  811. u64 xqe_pass : 8;
  812. u64 wqe_pool_drop : 8;
  813. u64 wqe_pool_pass : 8;
  814. u64 spb_aura_drop : 8;
  815. u64 spb_aura_pass : 8;
  816. u64 spb_pool_drop : 8;
  817. u64 spb_pool_pass : 8;
  818. u64 lpb_aura_drop : 8;
  819. u64 lpb_aura_pass : 8;
  820. u64 lpb_pool_drop : 8;
  821. u64 lpb_pool_pass : 8;
  822. u64 reserved_288_319 : 32;
  823. u64 ltag : 24;
  824. u64 good_utag : 8;
  825. u64 bad_utag : 8;
  826. u64 flow_tagw : 6;
  827. u64 reserved_366_383 : 18;
  828. u64 octs : 48;
  829. u64 reserved_432_447 : 16;
  830. u64 pkts : 48;
  831. u64 reserved_496_511 : 16;
  832. u64 drop_octs : 48;
  833. u64 reserved_560_575 : 16;
  834. u64 drop_pkts : 48;
  835. u64 reserved_624_639 : 16;
  836. u64 re_pkts : 48;
  837. u64 reserved_688_702 : 15;
  838. u64 ena_copy : 1;
  839. u64 reserved_704_739 : 36;
  840. u64 rq_int : 8;
  841. u64 rq_int_ena : 8;
  842. u64 qint_idx : 7;
  843. u64 reserved_763_767 : 5;
  844. u64 reserved_768_831 : 64;
  845. u64 reserved_832_895 : 64;
  846. u64 reserved_896_959 : 64;
  847. u64 reserved_960_1023 : 64;
  848. } s;
  849. /* struct nix_rq_ctx_hw_s_s cn; */
  850. };
  851. /**
  852. * Structure nix_rq_ctx_s
  853. *
  854. * NIX Receive Queue Context Structure This structure specifies the
  855. * format used by software to read and write an RQ context with the NIX
  856. * admin queue.
  857. */
  858. union nix_rq_ctx_s {
  859. u64 u[16];
  860. struct nix_rq_ctx_s_s {
  861. u64 ena : 1;
  862. u64 sso_ena : 1;
  863. u64 ipsech_ena : 1;
  864. u64 ena_wqwd : 1;
  865. u64 cq : 20;
  866. u64 substream : 20;
  867. u64 wqe_aura : 20;
  868. u64 spb_aura : 20;
  869. u64 lpb_aura : 20;
  870. u64 sso_grp : 10;
  871. u64 sso_tt : 2;
  872. u64 pb_caching : 2;
  873. u64 wqe_caching : 1;
  874. u64 xqe_drop_ena : 1;
  875. u64 spb_drop_ena : 1;
  876. u64 lpb_drop_ena : 1;
  877. u64 reserved_122_127 : 6;
  878. u64 reserved_128_139 : 12;
  879. u64 spb_sizem1 : 6;
  880. u64 wqe_skip : 2;
  881. u64 reserved_148_150 : 3;
  882. u64 spb_ena : 1;
  883. u64 lpb_sizem1 : 12;
  884. u64 first_skip : 7;
  885. u64 reserved_171 : 1;
  886. u64 later_skip : 6;
  887. u64 xqe_imm_size : 6;
  888. u64 reserved_184_189 : 6;
  889. u64 xqe_imm_copy : 1;
  890. u64 xqe_hdr_split : 1;
  891. u64 xqe_drop : 8;
  892. u64 xqe_pass : 8;
  893. u64 wqe_pool_drop : 8;
  894. u64 wqe_pool_pass : 8;
  895. u64 spb_aura_drop : 8;
  896. u64 spb_aura_pass : 8;
  897. u64 spb_pool_drop : 8;
  898. u64 spb_pool_pass : 8;
  899. u64 lpb_aura_drop : 8;
  900. u64 lpb_aura_pass : 8;
  901. u64 lpb_pool_drop : 8;
  902. u64 lpb_pool_pass : 8;
  903. u64 reserved_288_291 : 4;
  904. u64 rq_int : 8;
  905. u64 rq_int_ena : 8;
  906. u64 qint_idx : 7;
  907. u64 reserved_315_319 : 5;
  908. u64 ltag : 24;
  909. u64 good_utag : 8;
  910. u64 bad_utag : 8;
  911. u64 flow_tagw : 6;
  912. u64 reserved_366_383 : 18;
  913. u64 octs : 48;
  914. u64 reserved_432_447 : 16;
  915. u64 pkts : 48;
  916. u64 reserved_496_511 : 16;
  917. u64 drop_octs : 48;
  918. u64 reserved_560_575 : 16;
  919. u64 drop_pkts : 48;
  920. u64 reserved_624_639 : 16;
  921. u64 re_pkts : 48;
  922. u64 reserved_688_703 : 16;
  923. u64 reserved_704_767 : 64;
  924. u64 reserved_768_831 : 64;
  925. u64 reserved_832_895 : 64;
  926. u64 reserved_896_959 : 64;
  927. u64 reserved_960_1023 : 64;
  928. } s;
  929. /* struct nix_rq_ctx_s_s cn; */
  930. };
  931. /**
  932. * Structure nix_rsse_s
  933. *
  934. * NIX Receive Side Scaling Entry Structure This structure specifies the
  935. * format of each hardware entry in the NIX RSS tables in NDC/LLC/DRAM.
  936. * See NIX_AF_LF()_RSS_BASE and NIX_AF_LF()_RSS_GRP(). Software uses the
  937. * same structure format to read and write an RSS table entry with the
  938. * NIX admin queue.
  939. */
  940. union nix_rsse_s {
  941. u32 u;
  942. struct nix_rsse_s_s {
  943. u32 rq : 20;
  944. u32 reserved_20_31 : 12;
  945. } s;
  946. /* struct nix_rsse_s_s cn; */
  947. };
  948. /**
  949. * Structure nix_rx_action_s
  950. *
  951. * NIX Receive Action Structure This structure defines the format of
  952. * NPC_RESULT_S[ACTION] for a receive packet.
  953. */
  954. union nix_rx_action_s {
  955. u64 u;
  956. struct nix_rx_action_s_s {
  957. u64 op : 4;
  958. u64 pf_func : 16;
  959. u64 index : 20;
  960. u64 match_id : 16;
  961. u64 flow_key_alg : 5;
  962. u64 reserved_61_63 : 3;
  963. } s;
  964. /* struct nix_rx_action_s_s cn; */
  965. };
  966. /**
  967. * Structure nix_rx_imm_s
  968. *
  969. * NIX Receive Immediate Subdescriptor Structure The receive immediate
  970. * subdescriptor indicates that bytes immediately following this
  971. * NIX_RX_IMM_S (after skipping [APAD] bytes) were saved from the
  972. * received packet. The next subdescriptor following this NIX_RX_IMM_S
  973. * (when one exists) will follow the immediate bytes, after rounding up
  974. * the address to a multiple of 16 bytes.
  975. */
  976. union nix_rx_imm_s {
  977. u64 u;
  978. struct nix_rx_imm_s_s {
  979. u64 size : 16;
  980. u64 apad : 3;
  981. u64 reserved_19_59 : 41;
  982. u64 subdc : 4;
  983. } s;
  984. /* struct nix_rx_imm_s_s cn; */
  985. };
  986. /**
  987. * Structure nix_rx_mce_s
  988. *
  989. * NIX Receive Multicast/Mirror Entry Structure This structure specifies
  990. * the format of entries in the NIX receive multicast/mirror table
  991. * maintained by hardware in NDC/LLC/DRAM. See NIX_AF_RX_MCAST_BASE and
  992. * NIX_AF_RX_MCAST_CFG. Note the table may contain both multicast and
  993. * mirror replication lists. Software uses the same structure format to
  994. * read and write a multicast/mirror table entry with the NIX admin
  995. * queue.
  996. */
  997. union nix_rx_mce_s {
  998. u64 u;
  999. struct nix_rx_mce_s_s {
  1000. u64 op : 2;
  1001. u64 reserved_2 : 1;
  1002. u64 eol : 1;
  1003. u64 index : 20;
  1004. u64 reserved_24_31 : 8;
  1005. u64 pf_func : 16;
  1006. u64 next : 16;
  1007. } s;
  1008. /* struct nix_rx_mce_s_s cn; */
  1009. };
  1010. /**
  1011. * Structure nix_rx_parse_s
  1012. *
  1013. * NIX Receive Parse Structure This structure contains the receive packet
  1014. * parse result. It immediately follows NIX_CQE_HDR_S in a receive CQE,
  1015. * or NIX_WQE_HDR_S in a receive WQE. Stored in memory as little-endian
  1016. * unless NIX_AF_LF()_CFG[BE] is set. Header layers are always 2-byte
  1017. * aligned, so all header pointers in this structure ([EOH_PTR], [LAPTR]
  1018. * through [LHPTR], [VTAG*_PTR]) are even.
  1019. */
  1020. union nix_rx_parse_s {
  1021. u64 u[7];
  1022. struct nix_rx_parse_s_s {
  1023. u64 chan : 12;
  1024. u64 desc_sizem1 : 5;
  1025. u64 imm_copy : 1;
  1026. u64 express : 1;
  1027. u64 wqwd : 1;
  1028. u64 errlev : 4;
  1029. u64 errcode : 8;
  1030. u64 latype : 4;
  1031. u64 lbtype : 4;
  1032. u64 lctype : 4;
  1033. u64 ldtype : 4;
  1034. u64 letype : 4;
  1035. u64 lftype : 4;
  1036. u64 lgtype : 4;
  1037. u64 lhtype : 4;
  1038. u64 pkt_lenm1 : 16;
  1039. u64 l2m : 1;
  1040. u64 l2b : 1;
  1041. u64 l3m : 1;
  1042. u64 l3b : 1;
  1043. u64 vtag0_valid : 1;
  1044. u64 vtag0_gone : 1;
  1045. u64 vtag1_valid : 1;
  1046. u64 vtag1_gone : 1;
  1047. u64 pkind : 6;
  1048. u64 reserved_94_95 : 2;
  1049. u64 vtag0_tci : 16;
  1050. u64 vtag1_tci : 16;
  1051. u64 laflags : 8;
  1052. u64 lbflags : 8;
  1053. u64 lcflags : 8;
  1054. u64 ldflags : 8;
  1055. u64 leflags : 8;
  1056. u64 lfflags : 8;
  1057. u64 lgflags : 8;
  1058. u64 lhflags : 8;
  1059. u64 eoh_ptr : 8;
  1060. u64 wqe_aura : 20;
  1061. u64 pb_aura : 20;
  1062. u64 match_id : 16;
  1063. u64 laptr : 8;
  1064. u64 lbptr : 8;
  1065. u64 lcptr : 8;
  1066. u64 ldptr : 8;
  1067. u64 leptr : 8;
  1068. u64 lfptr : 8;
  1069. u64 lgptr : 8;
  1070. u64 lhptr : 8;
  1071. u64 vtag0_ptr : 8;
  1072. u64 vtag1_ptr : 8;
  1073. u64 flow_key_alg : 5;
  1074. u64 reserved_341_383 : 43;
  1075. u64 reserved_384_447 : 64;
  1076. } s;
  1077. /* struct nix_rx_parse_s_s cn; */
  1078. };
  1079. /**
  1080. * Structure nix_rx_sg_s
  1081. *
  1082. * NIX Receive Scatter/Gather Subdescriptor Structure The receive
  1083. * scatter/gather subdescriptor specifies one to three segments of packet
  1084. * data bytes. There may be multiple NIX_RX_SG_Ss in each NIX receive
  1085. * descriptor. NIX_RX_SG_S is immediately followed by one NIX_IOVA_S
  1086. * word when [SEGS] = 1, three NIX_IOVA_S words when [SEGS] \>= 2. Each
  1087. * NIX_IOVA_S word specifies the LF IOVA of first packet data byte in the
  1088. * corresponding segment; first NIX_IOVA_S word for segment 1, second
  1089. * word for segment 2, third word for segment 3. Note the third word is
  1090. * present when [SEGS] \>= 2 but only valid when [SEGS] = 3.
  1091. */
  1092. union nix_rx_sg_s {
  1093. u64 u;
  1094. struct nix_rx_sg_s_s {
  1095. u64 seg1_size : 16;
  1096. u64 seg2_size : 16;
  1097. u64 seg3_size : 16;
  1098. u64 segs : 2;
  1099. u64 reserved_50_59 : 10;
  1100. u64 subdc : 4;
  1101. } s;
  1102. /* struct nix_rx_sg_s_s cn; */
  1103. };
  1104. /**
  1105. * Structure nix_rx_vtag_action_s
  1106. *
  1107. * NIX Receive Vtag Action Structure This structure defines the format of
  1108. * NPC_RESULT_S[VTAG_ACTION] for a receive packet. It specifies up to two
  1109. * Vtags (e.g. C-VLAN/S-VLAN tags, 802.1BR E-TAG) for optional capture
  1110. * and/or stripping.
  1111. */
  1112. union nix_rx_vtag_action_s {
  1113. u64 u;
  1114. struct nix_rx_vtag_action_s_s {
  1115. u64 vtag0_relptr : 8;
  1116. u64 vtag0_lid : 3;
  1117. u64 reserved_11 : 1;
  1118. u64 vtag0_type : 3;
  1119. u64 vtag0_valid : 1;
  1120. u64 reserved_16_31 : 16;
  1121. u64 vtag1_relptr : 8;
  1122. u64 vtag1_lid : 3;
  1123. u64 reserved_43 : 1;
  1124. u64 vtag1_type : 3;
  1125. u64 vtag1_valid : 1;
  1126. u64 reserved_48_63 : 16;
  1127. } s;
  1128. /* struct nix_rx_vtag_action_s_s cn; */
  1129. };
  1130. /**
  1131. * Structure nix_send_comp_s
  1132. *
  1133. * NIX Send Completion Structure This structure immediately follows
  1134. * NIX_CQE_HDR_S in a send completion CQE.
  1135. */
  1136. union nix_send_comp_s {
  1137. u64 u;
  1138. struct nix_send_comp_s_s {
  1139. u64 status : 8;
  1140. u64 sqe_id : 16;
  1141. u64 reserved_24_63 : 40;
  1142. } s;
  1143. /* struct nix_send_comp_s_s cn; */
  1144. };
  1145. /**
  1146. * Structure nix_send_crc_s
  1147. *
  1148. * NIX Send CRC Subdescriptor Structure The send CRC subdescriptor
  1149. * specifies a CRC calculation be performed during transmission. Ignored
  1150. * when present in a send descriptor with NIX_SEND_EXT_S[LSO] set. There
  1151. * may be up to two NIX_SEND_CRC_Ss per send descriptor. NIX_SEND_CRC_S
  1152. * constraints: * When present, NIX_SEND_CRC_S subdescriptors must
  1153. * precede all NIX_SEND_SG_S, NIX_SEND_IMM_S and NIX_SEND_MEM_S
  1154. * subdescriptors in the send descriptor. * NIX_SEND_CRC_S subdescriptors
  1155. * must follow the same order as their checksum and insert regions in the
  1156. * packet, i.e. the checksum and insert regions of a NIX_SEND_CRC_S must
  1157. * come after the checksum and insert regions of a preceding
  1158. * NIX_SEND_CRC_S. There must be no overlap between any NIX_SEND_CRC_S
  1159. * checksum and insert regions. * If either
  1160. * NIX_SEND_HDR_S[OL4TYPE,IL4TYPE] = NIX_SENDL4TYPE_E::SCTP_CKSUM, the
  1161. * SCTP checksum region and NIX_SEND_CRC_S insert region must not
  1162. * overlap, and likewise the NIX_SEND_CRC_S checksum region and SCTP
  1163. * insert region must not overlap. * If either
  1164. * NIX_SEND_HDR_S[OL3TYPE,IL3TYPE] = NIX_SENDL3TYPE_E::IP4_CKSUM, the
  1165. * IPv4 header checksum region and NIX_SEND_CRC_S insert region must not
  1166. * overlap. * Any checksums inserted by
  1167. * NIX_SEND_HDR_S[OL3TYPE,OL4TYPE,IL3TYPE,IL4TYPE] must be outside of the
  1168. * NIX_SEND_CRC_S checksum and insert regions. Hardware adjusts [START],
  1169. * [SIZE] and [INSERT] as needed to account for any VLAN inserted by
  1170. * NIX_SEND_EXT_S[VLAN*] or Vtag inserted by NIX_TX_VTAG_ACTION_S.
  1171. */
  1172. union nix_send_crc_s {
  1173. u64 u[2];
  1174. struct nix_send_crc_s_s {
  1175. u64 size : 16;
  1176. u64 start : 16;
  1177. u64 insert : 16;
  1178. u64 reserved_48_57 : 10;
  1179. u64 alg : 2;
  1180. u64 subdc : 4;
  1181. u64 iv : 32;
  1182. u64 reserved_96_127 : 32;
  1183. } s;
  1184. /* struct nix_send_crc_s_s cn; */
  1185. };
  1186. /**
  1187. * Structure nix_send_ext_s
  1188. *
  1189. * NIX Send Extended Header Subdescriptor Structure The send extended
  1190. * header specifies LSO, VLAN insertion, timestamp and/or scheduling
  1191. * services on the packet. If present, it must immediately follow
  1192. * NIX_SEND_HDR_S. All fields are assumed to be zero when this
  1193. * subdescriptor is not present.
  1194. */
  1195. union nix_send_ext_s {
  1196. u64 u[2];
  1197. struct nix_send_ext_s_s {
  1198. u64 lso_mps : 14;
  1199. u64 lso : 1;
  1200. u64 tstmp : 1;
  1201. u64 lso_sb : 8;
  1202. u64 lso_format : 5;
  1203. u64 reserved_29_31 : 3;
  1204. u64 shp_chg : 9;
  1205. u64 shp_dis : 1;
  1206. u64 shp_ra : 2;
  1207. u64 markptr : 8;
  1208. u64 markform : 7;
  1209. u64 mark_en : 1;
  1210. u64 subdc : 4;
  1211. u64 vlan0_ins_ptr : 8;
  1212. u64 vlan0_ins_tci : 16;
  1213. u64 vlan1_ins_ptr : 8;
  1214. u64 vlan1_ins_tci : 16;
  1215. u64 vlan0_ins_ena : 1;
  1216. u64 vlan1_ins_ena : 1;
  1217. u64 reserved_114_127 : 14;
  1218. } s;
  1219. /* struct nix_send_ext_s_s cn; */
  1220. };
  1221. /**
  1222. * Structure nix_send_hdr_s
  1223. *
  1224. * NIX Send Header Subdescriptor Structure The send header is the first
  1225. * subdescriptor of every send descriptor.
  1226. */
  1227. union nix_send_hdr_s {
  1228. u64 u[2];
  1229. struct nix_send_hdr_s_s {
  1230. u64 total : 18;
  1231. u64 reserved_18 : 1;
  1232. u64 df : 1;
  1233. u64 aura : 20;
  1234. u64 sizem1 : 3;
  1235. u64 pnc : 1;
  1236. u64 sq : 20;
  1237. u64 ol3ptr : 8;
  1238. u64 ol4ptr : 8;
  1239. u64 il3ptr : 8;
  1240. u64 il4ptr : 8;
  1241. u64 ol3type : 4;
  1242. u64 ol4type : 4;
  1243. u64 il3type : 4;
  1244. u64 il4type : 4;
  1245. u64 sqe_id : 16;
  1246. } s;
  1247. /* struct nix_send_hdr_s_s cn; */
  1248. };
  1249. /**
  1250. * Structure nix_send_imm_s
  1251. *
  1252. * NIX Send Immediate Subdescriptor Structure The send immediate
  1253. * subdescriptor requests that bytes immediately following this
  1254. * NIX_SEND_IMM_S (after skipping [APAD] bytes) are to be included in the
  1255. * packet data. The next subdescriptor following this NIX_SEND_IMM_S
  1256. * (when one exists) will follow the immediate bytes, after rounding up
  1257. * the address to a multiple of 16 bytes. There may be multiple
  1258. * NIX_SEND_IMM_S in one NIX send descriptor. A NIX_SEND_IMM_S is ignored
  1259. * in a NIX send descriptor if the sum of all prior
  1260. * NIX_SEND_SG_S[SEG*_SIZE]s and NIX_SEND_IMM_S[SIZE]s meets or exceeds
  1261. * NIX_SEND_HDR_S[TOTAL]. When NIX_SEND_EXT_S[LSO] is set in the
  1262. * descriptor, all NIX_SEND_IMM_S bytes must be included in the first
  1263. * NIX_SEND_EXT_S[LSO_SB] bytes of the source packet.
  1264. */
  1265. union nix_send_imm_s {
  1266. u64 u;
  1267. struct nix_send_imm_s_s {
  1268. u64 size : 16;
  1269. u64 apad : 3;
  1270. u64 reserved_19_59 : 41;
  1271. u64 subdc : 4;
  1272. } s;
  1273. /* struct nix_send_imm_s_s cn; */
  1274. };
  1275. /**
  1276. * Structure nix_send_jump_s
  1277. *
  1278. * NIX Send Jump Subdescriptor Structure The send jump subdescriptor
  1279. * selects a new address for fetching the remaining subdescriptors of a
  1280. * send descriptor. This allows software to create a send descriptor
  1281. * longer than SQE size selected by NIX_SQ_CTX_S[MAX_SQE_SIZE]. There
  1282. * can be only one NIX_SEND_JUMP_S subdescriptor in a send descriptor. If
  1283. * present, it must immediately follow NIX_SEND_HDR_S if NIX_SEND_EXT_S
  1284. * is not present, else it must immediately follow NIX_SEND_EXT_S. In
  1285. * either case, it must terminate the SQE enqueued by software.
  1286. */
  1287. union nix_send_jump_s {
  1288. u64 u[2];
  1289. struct nix_send_jump_s_s {
  1290. u64 sizem1 : 7;
  1291. u64 reserved_7_13 : 7;
  1292. u64 ld_type : 2;
  1293. u64 aura : 20;
  1294. u64 reserved_36_58 : 23;
  1295. u64 f : 1;
  1296. u64 subdc : 4;
  1297. u64 addr : 64;
  1298. } s;
  1299. /* struct nix_send_jump_s_s cn; */
  1300. };
  1301. /**
  1302. * Structure nix_send_mem_s
  1303. *
  1304. * NIX Send Memory Subdescriptor Structure The send memory subdescriptor
  1305. * atomically sets, increments or decrements a memory location.
  1306. * NIX_SEND_MEM_S subdescriptors must follow all NIX_SEND_SG_S and
  1307. * NIX_SEND_IMM_S subdescriptors in the NIX send descriptor. NIX will not
  1308. * initiate the memory update for this subdescriptor until after it has
  1309. * completed all LLC/DRAM fetches that service all prior NIX_SEND_SG_S
  1310. * subdescriptors. The memory update is executed once, even if the packet
  1311. * is replicated due to NIX_TX_ACTION_S[OP] = NIX_TX_ACTIONOP_E::MCAST.
  1312. * Performance is best if a memory decrement by one is used rather than
  1313. * any other memory set/increment/decrement. (Less internal bus bandwidth
  1314. * is used with memory decrements by one.) When NIX_SEND_EXT_S[LSO] is
  1315. * set in the descriptor, NIX executes the memory update only while
  1316. * processing the last LSO segment, after processing prior segments.
  1317. */
  1318. union nix_send_mem_s {
  1319. u64 u[2];
  1320. struct nix_send_mem_s_s {
  1321. u64 offset : 16;
  1322. u64 reserved_16_52 : 37;
  1323. u64 wmem : 1;
  1324. u64 dsz : 2;
  1325. u64 alg : 4;
  1326. u64 subdc : 4;
  1327. u64 addr : 64;
  1328. } s;
  1329. /* struct nix_send_mem_s_s cn; */
  1330. };
  1331. /**
  1332. * Structure nix_send_sg_s
  1333. *
  1334. * NIX Send Scatter/Gather Subdescriptor Structure The send
  1335. * scatter/gather subdescriptor requests one to three segments of packet
  1336. * data bytes to be transmitted. There may be multiple NIX_SEND_SG_Ss in
  1337. * each NIX send descriptor. NIX_SEND_SG_S is immediately followed by
  1338. * one NIX_IOVA_S word when [SEGS] = 1, three NIX_IOVA_S words when
  1339. * [SEGS] \>= 2. Each NIX_IOVA_S word specifies the LF IOVA of first
  1340. * packet data byte in the corresponding segment; first NIX_IOVA_S word
  1341. * for segment 1, second word for segment 2, third word for segment 3.
  1342. * Note the third word is present when [SEGS] \>= 2 but only valid when
  1343. * [SEGS] = 3. If the sum of all prior NIX_SEND_SG_S[SEG*_SIZE]s and
  1344. * NIX_SEND_IMM_S[SIZE]s meets or exceeds NIX_SEND_HDR_S[TOTAL], this
  1345. * subdescriptor will not contribute any packet data but may free buffers
  1346. * to NPA (see [I1]).
  1347. */
  1348. union nix_send_sg_s {
  1349. u64 u;
  1350. struct nix_send_sg_s_s {
  1351. u64 seg1_size : 16;
  1352. u64 seg2_size : 16;
  1353. u64 seg3_size : 16;
  1354. u64 segs : 2;
  1355. u64 reserved_50_54 : 5;
  1356. u64 i1 : 1;
  1357. u64 i2 : 1;
  1358. u64 i3 : 1;
  1359. u64 ld_type : 2;
  1360. u64 subdc : 4;
  1361. } s;
  1362. /* struct nix_send_sg_s_s cn; */
  1363. };
  1364. /**
  1365. * Structure nix_send_work_s
  1366. *
  1367. * NIX Send Work Subdescriptor Structure This subdescriptor adds work to
  1368. * the SSO. At most one NIX_SEND_WORK_S subdescriptor can exist in the
  1369. * NIX send descriptor. If a NIX_SEND_WORK_S exists in the descriptor, it
  1370. * must be the last subdescriptor. NIX will not initiate the work add for
  1371. * this subdescriptor until after (1) it has completed all LLC/DRAM
  1372. * fetches that service all prior NIX_SEND_SG_S subdescriptors, (2) it
  1373. * has fetched all subdescriptors in the descriptor, and (3) all
  1374. * NIX_SEND_MEM_S[WMEM]=1 LLC/DRAM updates have completed. Provided the
  1375. * path of descriptors from the SQ through NIX to an output FIFO is
  1376. * unmodified between the descriptors (as should normally be the case,
  1377. * but it is possible for software to change the path), NIX also (1) will
  1378. * submit the SSO add works from all descriptors in the SQ in order, and
  1379. * (2) will not submit an SSO work add until after all prior descriptors
  1380. * in the SQ have completed their NIX_SEND_SG_S processing, and (3) will
  1381. * not submit an SSO work add until after it has fetched all
  1382. * subdescriptors from prior descriptors in the SQ. When
  1383. * NIX_SEND_EXT_S[LSO] is set in the descriptor, NIX executes the
  1384. * NIX_SEND_WORK_S work add only while processing the last LSO segment,
  1385. * after processing prior segments. Hardware ignores NIX_SEND_WORK_S
  1386. * when NIX_SQ_CTX_S[SSO_ENA] is clear.
  1387. */
  1388. union nix_send_work_s {
  1389. u64 u[2];
  1390. struct nix_send_work_s_s {
  1391. u64 tag : 32;
  1392. u64 tt : 2;
  1393. u64 grp : 10;
  1394. u64 reserved_44_59 : 16;
  1395. u64 subdc : 4;
  1396. u64 addr : 64;
  1397. } s;
  1398. /* struct nix_send_work_s_s cn; */
  1399. };
  1400. /**
  1401. * Structure nix_sq_ctx_hw_s
  1402. *
  1403. * NIX SQ Context Hardware Structure This structure contains context
  1404. * state maintained by hardware for each SQ in NDC/LLC/DRAM. Software
  1405. * uses the equivalent NIX_SQ_CTX_S structure format to read and write an
  1406. * SQ context with the NIX admin queue. Always stored in byte invariant
  1407. * little-endian format (LE8).
  1408. */
  1409. union nix_sq_ctx_hw_s {
  1410. u64 u[16];
  1411. struct nix_sq_ctx_hw_s_s {
  1412. u64 ena : 1;
  1413. u64 substream : 20;
  1414. u64 max_sqe_size : 2;
  1415. u64 sqe_way_mask : 16;
  1416. u64 sqb_aura : 20;
  1417. u64 gbl_rsvd1 : 5;
  1418. u64 cq_id : 20;
  1419. u64 cq_ena : 1;
  1420. u64 qint_idx : 6;
  1421. u64 gbl_rsvd2 : 1;
  1422. u64 sq_int : 8;
  1423. u64 sq_int_ena : 8;
  1424. u64 xoff : 1;
  1425. u64 sqe_stype : 2;
  1426. u64 gbl_rsvd : 17;
  1427. u64 head_sqb : 64;
  1428. u64 head_offset : 6;
  1429. u64 sqb_dequeue_count : 16;
  1430. u64 default_chan : 12;
  1431. u64 sdp_mcast : 1;
  1432. u64 sso_ena : 1;
  1433. u64 dse_rsvd1 : 28;
  1434. u64 sqb_enqueue_count : 16;
  1435. u64 tail_offset : 6;
  1436. u64 lmt_dis : 1;
  1437. u64 smq_rr_quantum : 24;
  1438. u64 dnq_rsvd1 : 17;
  1439. u64 tail_sqb : 64;
  1440. u64 next_sqb : 64;
  1441. u64 mnq_dis : 1;
  1442. u64 smq : 9;
  1443. u64 smq_pend : 1;
  1444. u64 smq_next_sq : 20;
  1445. u64 smq_next_sq_vld : 1;
  1446. u64 scm1_rsvd2 : 32;
  1447. u64 smenq_sqb : 64;
  1448. u64 smenq_offset : 6;
  1449. u64 cq_limit : 8;
  1450. u64 smq_rr_count : 25;
  1451. u64 scm_lso_rem : 18;
  1452. u64 scm_dq_rsvd0 : 7;
  1453. u64 smq_lso_segnum : 8;
  1454. u64 vfi_lso_total : 18;
  1455. u64 vfi_lso_sizem1 : 3;
  1456. u64 vfi_lso_sb : 8;
  1457. u64 vfi_lso_mps : 14;
  1458. u64 vfi_lso_vlan0_ins_ena : 1;
  1459. u64 vfi_lso_vlan1_ins_ena : 1;
  1460. u64 vfi_lso_vld : 1;
  1461. u64 smenq_next_sqb_vld : 1;
  1462. u64 scm_dq_rsvd1 : 9;
  1463. u64 smenq_next_sqb : 64;
  1464. u64 seb_rsvd1 : 64;
  1465. u64 drop_pkts : 48;
  1466. u64 drop_octs_lsw : 16;
  1467. u64 drop_octs_msw : 32;
  1468. u64 pkts_lsw : 32;
  1469. u64 pkts_msw : 16;
  1470. u64 octs : 48;
  1471. } s;
  1472. /* struct nix_sq_ctx_hw_s_s cn; */
  1473. };
  1474. /**
  1475. * Structure nix_sq_ctx_s
  1476. *
  1477. * NIX Send Queue Context Structure This structure specifies the format
  1478. * used by software with the NIX admin queue to read and write a send
  1479. * queue's NIX_SQ_CTX_HW_S structure maintained by hardware in
  1480. * NDC/LLC/DRAM. The SQ statistics ([OCTS], [PKTS], [DROP_OCTS],
  1481. * [DROP_PKTS]) do not account for packet replication due to
  1482. * NIX_TX_ACTION_S[OP] = NIX_TX_ACTIONOP_E::MCAST.
  1483. */
  1484. union nix_sq_ctx_s {
  1485. u64 u[16];
  1486. struct nix_sq_ctx_s_s {
  1487. u64 ena : 1;
  1488. u64 qint_idx : 6;
  1489. u64 substream : 20;
  1490. u64 sdp_mcast : 1;
  1491. u64 cq : 20;
  1492. u64 sqe_way_mask : 16;
  1493. u64 smq : 9;
  1494. u64 cq_ena : 1;
  1495. u64 xoff : 1;
  1496. u64 sso_ena : 1;
  1497. u64 smq_rr_quantum : 24;
  1498. u64 default_chan : 12;
  1499. u64 sqb_count : 16;
  1500. u64 smq_rr_count : 25;
  1501. u64 sqb_aura : 20;
  1502. u64 sq_int : 8;
  1503. u64 sq_int_ena : 8;
  1504. u64 sqe_stype : 2;
  1505. u64 reserved_191 : 1;
  1506. u64 max_sqe_size : 2;
  1507. u64 cq_limit : 8;
  1508. u64 lmt_dis : 1;
  1509. u64 mnq_dis : 1;
  1510. u64 smq_next_sq : 20;
  1511. u64 smq_lso_segnum : 8;
  1512. u64 tail_offset : 6;
  1513. u64 smenq_offset : 6;
  1514. u64 head_offset : 6;
  1515. u64 smenq_next_sqb_vld : 1;
  1516. u64 smq_pend : 1;
  1517. u64 smq_next_sq_vld : 1;
  1518. u64 reserved_253_255 : 3;
  1519. u64 next_sqb : 64;
  1520. u64 tail_sqb : 64;
  1521. u64 smenq_sqb : 64;
  1522. u64 smenq_next_sqb : 64;
  1523. u64 head_sqb : 64;
  1524. u64 reserved_576_583 : 8;
  1525. u64 vfi_lso_total : 18;
  1526. u64 vfi_lso_sizem1 : 3;
  1527. u64 vfi_lso_sb : 8;
  1528. u64 vfi_lso_mps : 14;
  1529. u64 vfi_lso_vlan0_ins_ena : 1;
  1530. u64 vfi_lso_vlan1_ins_ena : 1;
  1531. u64 vfi_lso_vld : 1;
  1532. u64 reserved_630_639 : 10;
  1533. u64 scm_lso_rem : 18;
  1534. u64 reserved_658_703 : 46;
  1535. u64 octs : 48;
  1536. u64 reserved_752_767 : 16;
  1537. u64 pkts : 48;
  1538. u64 reserved_816_831 : 16;
  1539. u64 reserved_832_895 : 64;
  1540. u64 drop_octs : 48;
  1541. u64 reserved_944_959 : 16;
  1542. u64 drop_pkts : 48;
  1543. u64 reserved_1008_1023 : 16;
  1544. } s;
  1545. /* struct nix_sq_ctx_s_s cn; */
  1546. };
  1547. /**
  1548. * Structure nix_tx_action_s
  1549. *
  1550. * NIX Transmit Action Structure This structure defines the format of
  1551. * NPC_RESULT_S[ACTION] for a transmit packet.
  1552. */
  1553. union nix_tx_action_s {
  1554. u64 u;
  1555. struct nix_tx_action_s_s {
  1556. u64 op : 4;
  1557. u64 reserved_4_11 : 8;
  1558. u64 index : 20;
  1559. u64 match_id : 16;
  1560. u64 reserved_48_63 : 16;
  1561. } s;
  1562. /* struct nix_tx_action_s_s cn; */
  1563. };
  1564. /**
  1565. * Structure nix_tx_vtag_action_s
  1566. *
  1567. * NIX Transmit Vtag Action Structure This structure defines the format
  1568. * of NPC_RESULT_S[VTAG_ACTION] for a transmit packet. It specifies the
  1569. * optional insertion or replacement of up to two Vtags (e.g.
  1570. * C-VLAN/S-VLAN tags, 802.1BR E-TAG). If two Vtags are specified: * The
  1571. * Vtag 0 byte offset from packet start (see [VTAG0_RELPTR]) must be less
  1572. * than or equal to the Vtag 1 byte offset. * Hardware executes the Vtag
  1573. * 0 action first, Vtag 1 action second. * If Vtag 0 is inserted,
  1574. * hardware adjusts the Vtag 1 byte offset accordingly. Thus, if the two
  1575. * offsets are equal in the structure, hardware inserts Vtag 1
  1576. * immediately after Vtag 0 in the packet. A Vtag must not be inserted
  1577. * or replaced within an outer or inner L3/L4 header, but may be inserted
  1578. * or replaced within an outer L4 payload.
  1579. */
  1580. union nix_tx_vtag_action_s {
  1581. u64 u;
  1582. struct nix_tx_vtag_action_s_s {
  1583. u64 vtag0_relptr : 8;
  1584. u64 vtag0_lid : 3;
  1585. u64 reserved_11 : 1;
  1586. u64 vtag0_op : 2;
  1587. u64 reserved_14_15 : 2;
  1588. u64 vtag0_def : 10;
  1589. u64 reserved_26_31 : 6;
  1590. u64 vtag1_relptr : 8;
  1591. u64 vtag1_lid : 3;
  1592. u64 reserved_43 : 1;
  1593. u64 vtag1_op : 2;
  1594. u64 reserved_46_47 : 2;
  1595. u64 vtag1_def : 10;
  1596. u64 reserved_58_63 : 6;
  1597. } s;
  1598. /* struct nix_tx_vtag_action_s_s cn; */
  1599. };
  1600. /**
  1601. * Structure nix_wqe_hdr_s
  1602. *
  1603. * NIX Work Queue Entry Header Structure This 64-bit structure defines
  1604. * the first word of every receive WQE generated by NIX. It is
  1605. * immediately followed by NIX_RX_PARSE_S. Stored in memory as little-
  1606. * endian unless NIX_AF_LF()_CFG[BE] is set.
  1607. */
  1608. union nix_wqe_hdr_s {
  1609. u64 u;
  1610. struct nix_wqe_hdr_s_s {
  1611. u64 tag : 32;
  1612. u64 tt : 2;
  1613. u64 grp : 10;
  1614. u64 node : 2;
  1615. u64 q : 14;
  1616. u64 wqe_type : 4;
  1617. } s;
  1618. /* struct nix_wqe_hdr_s_s cn; */
  1619. };
  1620. /**
  1621. * Register (RVU_PF_BAR0) nix#_af_aq_base
  1622. *
  1623. * NIX AF Admin Queue Base Address Register
  1624. */
  1625. union nixx_af_aq_base {
  1626. u64 u;
  1627. struct nixx_af_aq_base_s {
  1628. u64 reserved_0_6 : 7;
  1629. u64 base_addr : 46;
  1630. u64 reserved_53_63 : 11;
  1631. } s;
  1632. /* struct nixx_af_aq_base_s cn; */
  1633. };
  1634. static inline u64 NIXX_AF_AQ_BASE(void)
  1635. __attribute__ ((pure, always_inline));
  1636. static inline u64 NIXX_AF_AQ_BASE(void)
  1637. {
  1638. return 0x410;
  1639. }
  1640. /**
  1641. * Register (RVU_PF_BAR0) nix#_af_aq_cfg
  1642. *
  1643. * NIX AF Admin Queue Configuration Register
  1644. */
  1645. union nixx_af_aq_cfg {
  1646. u64 u;
  1647. struct nixx_af_aq_cfg_s {
  1648. u64 qsize : 4;
  1649. u64 reserved_4_63 : 60;
  1650. } s;
  1651. /* struct nixx_af_aq_cfg_s cn; */
  1652. };
  1653. static inline u64 NIXX_AF_AQ_CFG(void)
  1654. __attribute__ ((pure, always_inline));
  1655. static inline u64 NIXX_AF_AQ_CFG(void)
  1656. {
  1657. return 0x400;
  1658. }
  1659. /**
  1660. * Register (RVU_PF_BAR0) nix#_af_aq_done
  1661. *
  1662. * NIX AF Admin Queue Done Count Register
  1663. */
  1664. union nixx_af_aq_done {
  1665. u64 u;
  1666. struct nixx_af_aq_done_s {
  1667. u64 done : 20;
  1668. u64 reserved_20_63 : 44;
  1669. } s;
  1670. /* struct nixx_af_aq_done_s cn; */
  1671. };
  1672. static inline u64 NIXX_AF_AQ_DONE(void)
  1673. __attribute__ ((pure, always_inline));
  1674. static inline u64 NIXX_AF_AQ_DONE(void)
  1675. {
  1676. return 0x450;
  1677. }
  1678. /**
  1679. * Register (RVU_PF_BAR0) nix#_af_aq_done_ack
  1680. *
  1681. * NIX AF Admin Queue Done Count Ack Register This register is written by
  1682. * software to acknowledge interrupts.
  1683. */
  1684. union nixx_af_aq_done_ack {
  1685. u64 u;
  1686. struct nixx_af_aq_done_ack_s {
  1687. u64 done_ack : 20;
  1688. u64 reserved_20_63 : 44;
  1689. } s;
  1690. /* struct nixx_af_aq_done_ack_s cn; */
  1691. };
  1692. static inline u64 NIXX_AF_AQ_DONE_ACK(void)
  1693. __attribute__ ((pure, always_inline));
  1694. static inline u64 NIXX_AF_AQ_DONE_ACK(void)
  1695. {
  1696. return 0x460;
  1697. }
  1698. /**
  1699. * Register (RVU_PF_BAR0) nix#_af_aq_done_ena_w1c
  1700. *
  1701. * NIX AF Admin Queue Done Interrupt Enable Clear Register
  1702. */
  1703. union nixx_af_aq_done_ena_w1c {
  1704. u64 u;
  1705. struct nixx_af_aq_done_ena_w1c_s {
  1706. u64 done : 1;
  1707. u64 reserved_1_63 : 63;
  1708. } s;
  1709. /* struct nixx_af_aq_done_ena_w1c_s cn; */
  1710. };
  1711. static inline u64 NIXX_AF_AQ_DONE_ENA_W1C(void)
  1712. __attribute__ ((pure, always_inline));
  1713. static inline u64 NIXX_AF_AQ_DONE_ENA_W1C(void)
  1714. {
  1715. return 0x498;
  1716. }
  1717. /**
  1718. * Register (RVU_PF_BAR0) nix#_af_aq_done_ena_w1s
  1719. *
  1720. * NIX AF Admin Queue Done Interrupt Enable Set Register
  1721. */
  1722. union nixx_af_aq_done_ena_w1s {
  1723. u64 u;
  1724. struct nixx_af_aq_done_ena_w1s_s {
  1725. u64 done : 1;
  1726. u64 reserved_1_63 : 63;
  1727. } s;
  1728. /* struct nixx_af_aq_done_ena_w1s_s cn; */
  1729. };
  1730. static inline u64 NIXX_AF_AQ_DONE_ENA_W1S(void)
  1731. __attribute__ ((pure, always_inline));
  1732. static inline u64 NIXX_AF_AQ_DONE_ENA_W1S(void)
  1733. {
  1734. return 0x490;
  1735. }
  1736. /**
  1737. * Register (RVU_PF_BAR0) nix#_af_aq_done_int
  1738. *
  1739. * INTERNAL: NIX AF Admin Queue Done Interrupt Register
  1740. */
  1741. union nixx_af_aq_done_int {
  1742. u64 u;
  1743. struct nixx_af_aq_done_int_s {
  1744. u64 done : 1;
  1745. u64 reserved_1_63 : 63;
  1746. } s;
  1747. /* struct nixx_af_aq_done_int_s cn; */
  1748. };
  1749. static inline u64 NIXX_AF_AQ_DONE_INT(void)
  1750. __attribute__ ((pure, always_inline));
  1751. static inline u64 NIXX_AF_AQ_DONE_INT(void)
  1752. {
  1753. return 0x480;
  1754. }
  1755. /**
  1756. * Register (RVU_PF_BAR0) nix#_af_aq_done_int_w1s
  1757. *
  1758. * INTERNAL: NIX AF Admin Queue Done Interrupt Set Register
  1759. */
  1760. union nixx_af_aq_done_int_w1s {
  1761. u64 u;
  1762. struct nixx_af_aq_done_int_w1s_s {
  1763. u64 done : 1;
  1764. u64 reserved_1_63 : 63;
  1765. } s;
  1766. /* struct nixx_af_aq_done_int_w1s_s cn; */
  1767. };
  1768. static inline u64 NIXX_AF_AQ_DONE_INT_W1S(void)
  1769. __attribute__ ((pure, always_inline));
  1770. static inline u64 NIXX_AF_AQ_DONE_INT_W1S(void)
  1771. {
  1772. return 0x488;
  1773. }
  1774. /**
  1775. * Register (RVU_PF_BAR0) nix#_af_aq_done_timer
  1776. *
  1777. * NIX AF Admin Queue Done Interrupt Timer Register
  1778. */
  1779. union nixx_af_aq_done_timer {
  1780. u64 u;
  1781. struct nixx_af_aq_done_timer_s {
  1782. u64 count : 16;
  1783. u64 reserved_16_63 : 48;
  1784. } s;
  1785. /* struct nixx_af_aq_done_timer_s cn; */
  1786. };
  1787. static inline u64 NIXX_AF_AQ_DONE_TIMER(void)
  1788. __attribute__ ((pure, always_inline));
  1789. static inline u64 NIXX_AF_AQ_DONE_TIMER(void)
  1790. {
  1791. return 0x470;
  1792. }
  1793. /**
  1794. * Register (RVU_PF_BAR0) nix#_af_aq_done_wait
  1795. *
  1796. * NIX AF Admin Queue Done Interrupt Coalescing Wait Register Specifies
  1797. * the queue interrupt coalescing settings.
  1798. */
  1799. union nixx_af_aq_done_wait {
  1800. u64 u;
  1801. struct nixx_af_aq_done_wait_s {
  1802. u64 num_wait : 20;
  1803. u64 reserved_20_31 : 12;
  1804. u64 time_wait : 16;
  1805. u64 reserved_48_63 : 16;
  1806. } s;
  1807. /* struct nixx_af_aq_done_wait_s cn; */
  1808. };
  1809. static inline u64 NIXX_AF_AQ_DONE_WAIT(void)
  1810. __attribute__ ((pure, always_inline));
  1811. static inline u64 NIXX_AF_AQ_DONE_WAIT(void)
  1812. {
  1813. return 0x440;
  1814. }
  1815. /**
  1816. * Register (RVU_PF_BAR0) nix#_af_aq_door
  1817. *
  1818. * NIX AF Admin Queue Doorbell Register Software writes to this register
  1819. * to enqueue entries to AQ.
  1820. */
  1821. union nixx_af_aq_door {
  1822. u64 u;
  1823. struct nixx_af_aq_door_s {
  1824. u64 count : 16;
  1825. u64 reserved_16_63 : 48;
  1826. } s;
  1827. /* struct nixx_af_aq_door_s cn; */
  1828. };
  1829. static inline u64 NIXX_AF_AQ_DOOR(void)
  1830. __attribute__ ((pure, always_inline));
  1831. static inline u64 NIXX_AF_AQ_DOOR(void)
  1832. {
  1833. return 0x430;
  1834. }
  1835. /**
  1836. * Register (RVU_PF_BAR0) nix#_af_aq_status
  1837. *
  1838. * NIX AF Admin Queue Status Register
  1839. */
  1840. union nixx_af_aq_status {
  1841. u64 u;
  1842. struct nixx_af_aq_status_s {
  1843. u64 reserved_0_3 : 4;
  1844. u64 head_ptr : 20;
  1845. u64 reserved_24_35 : 12;
  1846. u64 tail_ptr : 20;
  1847. u64 reserved_56_61 : 6;
  1848. u64 aq_busy : 1;
  1849. u64 aq_err : 1;
  1850. } s;
  1851. struct nixx_af_aq_status_cn {
  1852. u64 reserved_0_3 : 4;
  1853. u64 head_ptr : 20;
  1854. u64 reserved_24_31 : 8;
  1855. u64 reserved_32_35 : 4;
  1856. u64 tail_ptr : 20;
  1857. u64 reserved_56_61 : 6;
  1858. u64 aq_busy : 1;
  1859. u64 aq_err : 1;
  1860. } cn;
  1861. };
  1862. static inline u64 NIXX_AF_AQ_STATUS(void)
  1863. __attribute__ ((pure, always_inline));
  1864. static inline u64 NIXX_AF_AQ_STATUS(void)
  1865. {
  1866. return 0x420;
  1867. }
  1868. /**
  1869. * Register (RVU_PF_BAR0) nix#_af_avg_delay
  1870. *
  1871. * NIX AF Queue Average Delay Register
  1872. */
  1873. union nixx_af_avg_delay {
  1874. u64 u;
  1875. struct nixx_af_avg_delay_s {
  1876. u64 avg_dly : 19;
  1877. u64 reserved_19_23 : 5;
  1878. u64 avg_timer : 16;
  1879. u64 reserved_40_63 : 24;
  1880. } s;
  1881. /* struct nixx_af_avg_delay_s cn; */
  1882. };
  1883. static inline u64 NIXX_AF_AVG_DELAY(void)
  1884. __attribute__ ((pure, always_inline));
  1885. static inline u64 NIXX_AF_AVG_DELAY(void)
  1886. {
  1887. return 0xe0;
  1888. }
  1889. /**
  1890. * Register (RVU_PF_BAR0) nix#_af_bar2_alias#
  1891. *
  1892. * NIX Admin Function BAR2 Alias Registers These registers alias to the
  1893. * NIX BAR2 registers for the PF and function selected by
  1894. * NIX_AF_BAR2_SEL[PF_FUNC]. Internal: Not implemented. Placeholder for
  1895. * bug33464.
  1896. */
  1897. union nixx_af_bar2_aliasx {
  1898. u64 u;
  1899. struct nixx_af_bar2_aliasx_s {
  1900. u64 data : 64;
  1901. } s;
  1902. /* struct nixx_af_bar2_aliasx_s cn; */
  1903. };
  1904. static inline u64 NIXX_AF_BAR2_ALIASX(u64 a)
  1905. __attribute__ ((pure, always_inline));
  1906. static inline u64 NIXX_AF_BAR2_ALIASX(u64 a)
  1907. {
  1908. return 0x9100000 + 8 * a;
  1909. }
  1910. /**
  1911. * Register (RVU_PF_BAR0) nix#_af_bar2_sel
  1912. *
  1913. * NIX Admin Function BAR2 Select Register This register configures BAR2
  1914. * accesses from the NIX_AF_BAR2_ALIAS() registers in BAR0. Internal: Not
  1915. * implemented. Placeholder for bug33464.
  1916. */
  1917. union nixx_af_bar2_sel {
  1918. u64 u;
  1919. struct nixx_af_bar2_sel_s {
  1920. u64 alias_pf_func : 16;
  1921. u64 alias_ena : 1;
  1922. u64 reserved_17_63 : 47;
  1923. } s;
  1924. /* struct nixx_af_bar2_sel_s cn; */
  1925. };
  1926. static inline u64 NIXX_AF_BAR2_SEL(void)
  1927. __attribute__ ((pure, always_inline));
  1928. static inline u64 NIXX_AF_BAR2_SEL(void)
  1929. {
  1930. return 0x9000000;
  1931. }
  1932. /**
  1933. * Register (RVU_PF_BAR0) nix#_af_blk_rst
  1934. *
  1935. * NIX AF Block Reset Register
  1936. */
  1937. union nixx_af_blk_rst {
  1938. u64 u;
  1939. struct nixx_af_blk_rst_s {
  1940. u64 rst : 1;
  1941. u64 reserved_1_62 : 62;
  1942. u64 busy : 1;
  1943. } s;
  1944. /* struct nixx_af_blk_rst_s cn; */
  1945. };
  1946. static inline u64 NIXX_AF_BLK_RST(void)
  1947. __attribute__ ((pure, always_inline));
  1948. static inline u64 NIXX_AF_BLK_RST(void)
  1949. {
  1950. return 0xb0;
  1951. }
  1952. /**
  1953. * Register (RVU_PF_BAR0) nix#_af_cfg
  1954. *
  1955. * NIX AF General Configuration Register
  1956. */
  1957. union nixx_af_cfg {
  1958. u64 u;
  1959. struct nixx_af_cfg_s {
  1960. u64 force_cond_clk_en : 1;
  1961. u64 force_rx_gbl_clk_en : 1;
  1962. u64 force_rx_strm_clk_en : 1;
  1963. u64 force_cqm_clk_en : 1;
  1964. u64 force_seb_clk_en : 1;
  1965. u64 force_sqm_clk_en : 1;
  1966. u64 force_pse_clk_en : 1;
  1967. u64 reserved_7 : 1;
  1968. u64 af_be : 1;
  1969. u64 calibrate_x2p : 1;
  1970. u64 force_intf_clk_en : 1;
  1971. u64 reserved_11_63 : 53;
  1972. } s;
  1973. /* struct nixx_af_cfg_s cn; */
  1974. };
  1975. static inline u64 NIXX_AF_CFG(void)
  1976. __attribute__ ((pure, always_inline));
  1977. static inline u64 NIXX_AF_CFG(void)
  1978. {
  1979. return 0;
  1980. }
  1981. /**
  1982. * Register (RVU_PF_BAR0) nix#_af_cint_delay
  1983. *
  1984. * NIX AF Completion Interrupt Delay Register
  1985. */
  1986. union nixx_af_cint_delay {
  1987. u64 u;
  1988. struct nixx_af_cint_delay_s {
  1989. u64 cint_dly : 10;
  1990. u64 reserved_10_15 : 6;
  1991. u64 cint_timer : 16;
  1992. u64 reserved_32_63 : 32;
  1993. } s;
  1994. /* struct nixx_af_cint_delay_s cn; */
  1995. };
  1996. static inline u64 NIXX_AF_CINT_DELAY(void)
  1997. __attribute__ ((pure, always_inline));
  1998. static inline u64 NIXX_AF_CINT_DELAY(void)
  1999. {
  2000. return 0xf0;
  2001. }
  2002. /**
  2003. * Register (RVU_PF_BAR0) nix#_af_cint_timer#
  2004. *
  2005. * NIX AF Completion Interrupt Timer Registers
  2006. */
  2007. union nixx_af_cint_timerx {
  2008. u64 u;
  2009. struct nixx_af_cint_timerx_s {
  2010. u64 expir_time : 16;
  2011. u64 cint : 7;
  2012. u64 reserved_23 : 1;
  2013. u64 lf : 8;
  2014. u64 active : 1;
  2015. u64 reserved_33_63 : 31;
  2016. } s;
  2017. /* struct nixx_af_cint_timerx_s cn; */
  2018. };
  2019. static inline u64 NIXX_AF_CINT_TIMERX(u64 a)
  2020. __attribute__ ((pure, always_inline));
  2021. static inline u64 NIXX_AF_CINT_TIMERX(u64 a)
  2022. {
  2023. return 0x1a40 + 0x40000 * a;
  2024. }
  2025. /**
  2026. * Register (RVU_PF_BAR0) nix#_af_const
  2027. *
  2028. * NIX AF Constants Register This register contains constants for
  2029. * software discovery.
  2030. */
  2031. union nixx_af_const {
  2032. u64 u;
  2033. struct nixx_af_const_s {
  2034. u64 cgx_lmac_channels : 8;
  2035. u64 cgx_lmacs : 4;
  2036. u64 num_cgx : 4;
  2037. u64 lbk_channels : 8;
  2038. u64 num_lbk : 4;
  2039. u64 num_sdp : 4;
  2040. u64 reserved_32_47 : 16;
  2041. u64 links : 8;
  2042. u64 intfs : 4;
  2043. u64 reserved_60_63 : 4;
  2044. } s;
  2045. /* struct nixx_af_const_s cn; */
  2046. };
  2047. static inline u64 NIXX_AF_CONST(void)
  2048. __attribute__ ((pure, always_inline));
  2049. static inline u64 NIXX_AF_CONST(void)
  2050. {
  2051. return 0x20;
  2052. }
  2053. /**
  2054. * Register (RVU_PF_BAR0) nix#_af_const1
  2055. *
  2056. * NIX AF Constants 1 Register This register contains constants for
  2057. * software discovery.
  2058. */
  2059. union nixx_af_const1 {
  2060. u64 u;
  2061. struct nixx_af_const1_s {
  2062. u64 sdp_channels : 12;
  2063. u64 rx_bpids : 12;
  2064. u64 lf_tx_stats : 8;
  2065. u64 lf_rx_stats : 8;
  2066. u64 lso_format_fields : 8;
  2067. u64 lso_formats : 8;
  2068. u64 reserved_56_63 : 8;
  2069. } s;
  2070. /* struct nixx_af_const1_s cn; */
  2071. };
  2072. static inline u64 NIXX_AF_CONST1(void)
  2073. __attribute__ ((pure, always_inline));
  2074. static inline u64 NIXX_AF_CONST1(void)
  2075. {
  2076. return 0x28;
  2077. }
  2078. /**
  2079. * Register (RVU_PF_BAR0) nix#_af_const2
  2080. *
  2081. * NIX AF Constants 2 Register This register contains constants for
  2082. * software discovery.
  2083. */
  2084. union nixx_af_const2 {
  2085. u64 u;
  2086. struct nixx_af_const2_s {
  2087. u64 lfs : 12;
  2088. u64 qints : 12;
  2089. u64 cints : 12;
  2090. u64 reserved_36_63 : 28;
  2091. } s;
  2092. /* struct nixx_af_const2_s cn; */
  2093. };
  2094. static inline u64 NIXX_AF_CONST2(void)
  2095. __attribute__ ((pure, always_inline));
  2096. static inline u64 NIXX_AF_CONST2(void)
  2097. {
  2098. return 0x30;
  2099. }
  2100. /**
  2101. * Register (RVU_PF_BAR0) nix#_af_const3
  2102. *
  2103. * NIX AF Constants 2 Register This register contains constants for
  2104. * software discovery.
  2105. */
  2106. union nixx_af_const3 {
  2107. u64 u;
  2108. struct nixx_af_const3_s {
  2109. u64 sq_ctx_log2bytes : 4;
  2110. u64 rq_ctx_log2bytes : 4;
  2111. u64 cq_ctx_log2bytes : 4;
  2112. u64 rsse_log2bytes : 4;
  2113. u64 mce_log2bytes : 4;
  2114. u64 qint_log2bytes : 4;
  2115. u64 cint_log2bytes : 4;
  2116. u64 dyno_log2bytes : 4;
  2117. u64 reserved_32_63 : 32;
  2118. } s;
  2119. /* struct nixx_af_const3_s cn; */
  2120. };
  2121. static inline u64 NIXX_AF_CONST3(void)
  2122. __attribute__ ((pure, always_inline));
  2123. static inline u64 NIXX_AF_CONST3(void)
  2124. {
  2125. return 0x38;
  2126. }
  2127. /**
  2128. * Register (RVU_PF_BAR0) nix#_af_cq_const
  2129. *
  2130. * NIX AF CQ Constants Register This register contains constants for
  2131. * software discovery.
  2132. */
  2133. union nixx_af_cq_const {
  2134. u64 u;
  2135. struct nixx_af_cq_const_s {
  2136. u64 queues_per_lf : 24;
  2137. u64 reserved_24_63 : 40;
  2138. } s;
  2139. /* struct nixx_af_cq_const_s cn; */
  2140. };
  2141. static inline u64 NIXX_AF_CQ_CONST(void)
  2142. __attribute__ ((pure, always_inline));
  2143. static inline u64 NIXX_AF_CQ_CONST(void)
  2144. {
  2145. return 0x48;
  2146. }
  2147. /**
  2148. * Register (RVU_PF_BAR0) nix#_af_cqm_bp_test
  2149. *
  2150. * INTERNAL: NIX AF CQM Backpressure Test Registers
  2151. */
  2152. union nixx_af_cqm_bp_test {
  2153. u64 u;
  2154. struct nixx_af_cqm_bp_test_s {
  2155. u64 lfsr_freq : 12;
  2156. u64 reserved_12_15 : 4;
  2157. u64 bp_cfg : 24;
  2158. u64 enable : 12;
  2159. u64 reserved_52_63 : 12;
  2160. } s;
  2161. /* struct nixx_af_cqm_bp_test_s cn; */
  2162. };
  2163. static inline u64 NIXX_AF_CQM_BP_TEST(void)
  2164. __attribute__ ((pure, always_inline));
  2165. static inline u64 NIXX_AF_CQM_BP_TEST(void)
  2166. {
  2167. return 0x48c0;
  2168. }
  2169. /**
  2170. * Register (RVU_PF_BAR0) nix#_af_cqm_eco
  2171. *
  2172. * INTERNAL: AF CQM ECO Register
  2173. */
  2174. union nixx_af_cqm_eco {
  2175. u64 u;
  2176. struct nixx_af_cqm_eco_s {
  2177. u64 eco_rw : 64;
  2178. } s;
  2179. /* struct nixx_af_cqm_eco_s cn; */
  2180. };
  2181. static inline u64 NIXX_AF_CQM_ECO(void)
  2182. __attribute__ ((pure, always_inline));
  2183. static inline u64 NIXX_AF_CQM_ECO(void)
  2184. {
  2185. return 0x590;
  2186. }
  2187. /**
  2188. * Register (RVU_PF_BAR0) nix#_af_csi_eco
  2189. *
  2190. * INTERNAL: AF CSI ECO Register
  2191. */
  2192. union nixx_af_csi_eco {
  2193. u64 u;
  2194. struct nixx_af_csi_eco_s {
  2195. u64 eco_rw : 64;
  2196. } s;
  2197. /* struct nixx_af_csi_eco_s cn; */
  2198. };
  2199. static inline u64 NIXX_AF_CSI_ECO(void)
  2200. __attribute__ ((pure, always_inline));
  2201. static inline u64 NIXX_AF_CSI_ECO(void)
  2202. {
  2203. return 0x580;
  2204. }
  2205. /**
  2206. * Register (RVU_PF_BAR0) nix#_af_err_int
  2207. *
  2208. * NIX Admin Function Error Interrupt Register
  2209. */
  2210. union nixx_af_err_int {
  2211. u64 u;
  2212. struct nixx_af_err_int_s {
  2213. u64 rx_mcast_data_fault : 1;
  2214. u64 rx_mirror_data_fault : 1;
  2215. u64 rx_mcast_wqe_fault : 1;
  2216. u64 rx_mirror_wqe_fault : 1;
  2217. u64 rx_mce_fault : 1;
  2218. u64 rx_mce_list_err : 1;
  2219. u64 rx_unmapped_pf_func : 1;
  2220. u64 reserved_7_11 : 5;
  2221. u64 aq_door_err : 1;
  2222. u64 aq_res_fault : 1;
  2223. u64 aq_inst_fault : 1;
  2224. u64 reserved_15_63 : 49;
  2225. } s;
  2226. /* struct nixx_af_err_int_s cn; */
  2227. };
  2228. static inline u64 NIXX_AF_ERR_INT(void)
  2229. __attribute__ ((pure, always_inline));
  2230. static inline u64 NIXX_AF_ERR_INT(void)
  2231. {
  2232. return 0x180;
  2233. }
  2234. /**
  2235. * Register (RVU_PF_BAR0) nix#_af_err_int_ena_w1c
  2236. *
  2237. * NIX Admin Function Error Interrupt Enable Clear Register This register
  2238. * clears interrupt enable bits.
  2239. */
  2240. union nixx_af_err_int_ena_w1c {
  2241. u64 u;
  2242. struct nixx_af_err_int_ena_w1c_s {
  2243. u64 rx_mcast_data_fault : 1;
  2244. u64 rx_mirror_data_fault : 1;
  2245. u64 rx_mcast_wqe_fault : 1;
  2246. u64 rx_mirror_wqe_fault : 1;
  2247. u64 rx_mce_fault : 1;
  2248. u64 rx_mce_list_err : 1;
  2249. u64 rx_unmapped_pf_func : 1;
  2250. u64 reserved_7_11 : 5;
  2251. u64 aq_door_err : 1;
  2252. u64 aq_res_fault : 1;
  2253. u64 aq_inst_fault : 1;
  2254. u64 reserved_15_63 : 49;
  2255. } s;
  2256. /* struct nixx_af_err_int_ena_w1c_s cn; */
  2257. };
  2258. static inline u64 NIXX_AF_ERR_INT_ENA_W1C(void)
  2259. __attribute__ ((pure, always_inline));
  2260. static inline u64 NIXX_AF_ERR_INT_ENA_W1C(void)
  2261. {
  2262. return 0x198;
  2263. }
  2264. /**
  2265. * Register (RVU_PF_BAR0) nix#_af_err_int_ena_w1s
  2266. *
  2267. * NIX Admin Function Error Interrupt Enable Set Register This register
  2268. * sets interrupt enable bits.
  2269. */
  2270. union nixx_af_err_int_ena_w1s {
  2271. u64 u;
  2272. struct nixx_af_err_int_ena_w1s_s {
  2273. u64 rx_mcast_data_fault : 1;
  2274. u64 rx_mirror_data_fault : 1;
  2275. u64 rx_mcast_wqe_fault : 1;
  2276. u64 rx_mirror_wqe_fault : 1;
  2277. u64 rx_mce_fault : 1;
  2278. u64 rx_mce_list_err : 1;
  2279. u64 rx_unmapped_pf_func : 1;
  2280. u64 reserved_7_11 : 5;
  2281. u64 aq_door_err : 1;
  2282. u64 aq_res_fault : 1;
  2283. u64 aq_inst_fault : 1;
  2284. u64 reserved_15_63 : 49;
  2285. } s;
  2286. /* struct nixx_af_err_int_ena_w1s_s cn; */
  2287. };
  2288. static inline u64 NIXX_AF_ERR_INT_ENA_W1S(void)
  2289. __attribute__ ((pure, always_inline));
  2290. static inline u64 NIXX_AF_ERR_INT_ENA_W1S(void)
  2291. {
  2292. return 0x190;
  2293. }
  2294. /**
  2295. * Register (RVU_PF_BAR0) nix#_af_err_int_w1s
  2296. *
  2297. * NIX Admin Function Error Interrupt Set Register This register sets
  2298. * interrupt bits.
  2299. */
  2300. union nixx_af_err_int_w1s {
  2301. u64 u;
  2302. struct nixx_af_err_int_w1s_s {
  2303. u64 rx_mcast_data_fault : 1;
  2304. u64 rx_mirror_data_fault : 1;
  2305. u64 rx_mcast_wqe_fault : 1;
  2306. u64 rx_mirror_wqe_fault : 1;
  2307. u64 rx_mce_fault : 1;
  2308. u64 rx_mce_list_err : 1;
  2309. u64 rx_unmapped_pf_func : 1;
  2310. u64 reserved_7_11 : 5;
  2311. u64 aq_door_err : 1;
  2312. u64 aq_res_fault : 1;
  2313. u64 aq_inst_fault : 1;
  2314. u64 reserved_15_63 : 49;
  2315. } s;
  2316. /* struct nixx_af_err_int_w1s_s cn; */
  2317. };
  2318. static inline u64 NIXX_AF_ERR_INT_W1S(void)
  2319. __attribute__ ((pure, always_inline));
  2320. static inline u64 NIXX_AF_ERR_INT_W1S(void)
  2321. {
  2322. return 0x188;
  2323. }
  2324. /**
  2325. * Register (RVU_PF_BAR0) nix#_af_expr_tx_fifo_status
  2326. *
  2327. * INTERNAL: NIX AF Express Transmit FIFO Status Register Internal:
  2328. * 802.3br frame preemption/express path is defeatured. Old definition:
  2329. * Status of FIFO which transmits express packets to CGX and LBK.
  2330. */
  2331. union nixx_af_expr_tx_fifo_status {
  2332. u64 u;
  2333. struct nixx_af_expr_tx_fifo_status_s {
  2334. u64 count : 12;
  2335. u64 reserved_12_63 : 52;
  2336. } s;
  2337. /* struct nixx_af_expr_tx_fifo_status_s cn; */
  2338. };
  2339. static inline u64 NIXX_AF_EXPR_TX_FIFO_STATUS(void)
  2340. __attribute__ ((pure, always_inline));
  2341. static inline u64 NIXX_AF_EXPR_TX_FIFO_STATUS(void)
  2342. {
  2343. return 0x640;
  2344. }
  2345. /**
  2346. * Register (RVU_PF_BAR0) nix#_af_gen_int
  2347. *
  2348. * NIX AF General Interrupt Register
  2349. */
  2350. union nixx_af_gen_int {
  2351. u64 u;
  2352. struct nixx_af_gen_int_s {
  2353. u64 rx_mcast_drop : 1;
  2354. u64 rx_mirror_drop : 1;
  2355. u64 reserved_2 : 1;
  2356. u64 tl1_drain : 1;
  2357. u64 smq_flush_done : 1;
  2358. u64 reserved_5_63 : 59;
  2359. } s;
  2360. /* struct nixx_af_gen_int_s cn; */
  2361. };
  2362. static inline u64 NIXX_AF_GEN_INT(void)
  2363. __attribute__ ((pure, always_inline));
  2364. static inline u64 NIXX_AF_GEN_INT(void)
  2365. {
  2366. return 0x160;
  2367. }
  2368. /**
  2369. * Register (RVU_PF_BAR0) nix#_af_gen_int_ena_w1c
  2370. *
  2371. * NIX AF General Interrupt Enable Clear Register This register clears
  2372. * interrupt enable bits.
  2373. */
  2374. union nixx_af_gen_int_ena_w1c {
  2375. u64 u;
  2376. struct nixx_af_gen_int_ena_w1c_s {
  2377. u64 rx_mcast_drop : 1;
  2378. u64 rx_mirror_drop : 1;
  2379. u64 reserved_2 : 1;
  2380. u64 tl1_drain : 1;
  2381. u64 smq_flush_done : 1;
  2382. u64 reserved_5_63 : 59;
  2383. } s;
  2384. /* struct nixx_af_gen_int_ena_w1c_s cn; */
  2385. };
  2386. static inline u64 NIXX_AF_GEN_INT_ENA_W1C(void)
  2387. __attribute__ ((pure, always_inline));
  2388. static inline u64 NIXX_AF_GEN_INT_ENA_W1C(void)
  2389. {
  2390. return 0x178;
  2391. }
  2392. /**
  2393. * Register (RVU_PF_BAR0) nix#_af_gen_int_ena_w1s
  2394. *
  2395. * NIX AF General Interrupt Enable Set Register This register sets
  2396. * interrupt enable bits.
  2397. */
  2398. union nixx_af_gen_int_ena_w1s {
  2399. u64 u;
  2400. struct nixx_af_gen_int_ena_w1s_s {
  2401. u64 rx_mcast_drop : 1;
  2402. u64 rx_mirror_drop : 1;
  2403. u64 reserved_2 : 1;
  2404. u64 tl1_drain : 1;
  2405. u64 smq_flush_done : 1;
  2406. u64 reserved_5_63 : 59;
  2407. } s;
  2408. /* struct nixx_af_gen_int_ena_w1s_s cn; */
  2409. };
  2410. static inline u64 NIXX_AF_GEN_INT_ENA_W1S(void)
  2411. __attribute__ ((pure, always_inline));
  2412. static inline u64 NIXX_AF_GEN_INT_ENA_W1S(void)
  2413. {
  2414. return 0x170;
  2415. }
  2416. /**
  2417. * Register (RVU_PF_BAR0) nix#_af_gen_int_w1s
  2418. *
  2419. * NIX AF General Interrupt Set Register This register sets interrupt
  2420. * bits.
  2421. */
  2422. union nixx_af_gen_int_w1s {
  2423. u64 u;
  2424. struct nixx_af_gen_int_w1s_s {
  2425. u64 rx_mcast_drop : 1;
  2426. u64 rx_mirror_drop : 1;
  2427. u64 reserved_2 : 1;
  2428. u64 tl1_drain : 1;
  2429. u64 smq_flush_done : 1;
  2430. u64 reserved_5_63 : 59;
  2431. } s;
  2432. /* struct nixx_af_gen_int_w1s_s cn; */
  2433. };
  2434. static inline u64 NIXX_AF_GEN_INT_W1S(void)
  2435. __attribute__ ((pure, always_inline));
  2436. static inline u64 NIXX_AF_GEN_INT_W1S(void)
  2437. {
  2438. return 0x168;
  2439. }
  2440. /**
  2441. * Register (RVU_PF_BAR0) nix#_af_lf#_cfg
  2442. *
  2443. * NIX AF Local Function Configuration Registers
  2444. */
  2445. union nixx_af_lfx_cfg {
  2446. u64 u;
  2447. struct nixx_af_lfx_cfg_s {
  2448. u64 npa_pf_func : 16;
  2449. u64 sso_pf_func : 16;
  2450. u64 be : 1;
  2451. u64 xqe_size : 2;
  2452. u64 reserved_35_63 : 29;
  2453. } s;
  2454. /* struct nixx_af_lfx_cfg_s cn; */
  2455. };
  2456. static inline u64 NIXX_AF_LFX_CFG(u64 a)
  2457. __attribute__ ((pure, always_inline));
  2458. static inline u64 NIXX_AF_LFX_CFG(u64 a)
  2459. {
  2460. return 0x4000 + 0x20000 * a;
  2461. }
  2462. /**
  2463. * Register (RVU_PF_BAR0) nix#_af_lf#_cints_base
  2464. *
  2465. * NIX AF Local Function Completion Interrupts Base Address Registers
  2466. * This register specifies the base AF IOVA of LF's completion interrupt
  2467. * context table in NDC/LLC/DRAM. The table consists of
  2468. * NIX_AF_CONST2[CINTS] contiguous NIX_CINT_HW_S structures. After
  2469. * writing to this register, software should read it back to ensure that
  2470. * the write has completed before accessing any NIX_LF_CINT()_*
  2471. * registers.
  2472. */
  2473. union nixx_af_lfx_cints_base {
  2474. u64 u;
  2475. struct nixx_af_lfx_cints_base_s {
  2476. u64 reserved_0_6 : 7;
  2477. u64 addr : 46;
  2478. u64 reserved_53_63 : 11;
  2479. } s;
  2480. /* struct nixx_af_lfx_cints_base_s cn; */
  2481. };
  2482. static inline u64 NIXX_AF_LFX_CINTS_BASE(u64 a)
  2483. __attribute__ ((pure, always_inline));
  2484. static inline u64 NIXX_AF_LFX_CINTS_BASE(u64 a)
  2485. {
  2486. return 0x4130 + 0x20000 * a;
  2487. }
  2488. /**
  2489. * Register (RVU_PF_BAR0) nix#_af_lf#_cints_cfg
  2490. *
  2491. * NIX AF Local Function Completion Interrupts Configuration Registers
  2492. * This register controls access to the LF's completion interrupt context
  2493. * table in NDC/LLC/DRAM. The table consists of NIX_AF_CONST2[CINTS]
  2494. * contiguous NIX_CINT_HW_S structures. The size of each structure is 1
  2495. * \<\< NIX_AF_CONST3[CINT_LOG2BYTES]. After writing to this register,
  2496. * software should read it back to ensure that the write has completed
  2497. * before accessing any NIX_LF_CINT()_* registers.
  2498. */
  2499. union nixx_af_lfx_cints_cfg {
  2500. u64 u;
  2501. struct nixx_af_lfx_cints_cfg_s {
  2502. u64 reserved_0_19 : 20;
  2503. u64 way_mask : 16;
  2504. u64 caching : 1;
  2505. u64 reserved_37_63 : 27;
  2506. } s;
  2507. /* struct nixx_af_lfx_cints_cfg_s cn; */
  2508. };
  2509. static inline u64 NIXX_AF_LFX_CINTS_CFG(u64 a)
  2510. __attribute__ ((pure, always_inline));
  2511. static inline u64 NIXX_AF_LFX_CINTS_CFG(u64 a)
  2512. {
  2513. return 0x4120 + 0x20000 * a;
  2514. }
  2515. /**
  2516. * Register (RVU_PF_BAR0) nix#_af_lf#_cqs_base
  2517. *
  2518. * NIX AF Local Function Completion Queues Base Address Register This
  2519. * register specifies the base AF IOVA of the LF's CQ context table. The
  2520. * table consists of NIX_AF_LF()_CQS_CFG[MAX_QUEUESM1]+1 contiguous
  2521. * NIX_CQ_CTX_S structures.
  2522. */
  2523. union nixx_af_lfx_cqs_base {
  2524. u64 u;
  2525. struct nixx_af_lfx_cqs_base_s {
  2526. u64 reserved_0_6 : 7;
  2527. u64 addr : 46;
  2528. u64 reserved_53_63 : 11;
  2529. } s;
  2530. /* struct nixx_af_lfx_cqs_base_s cn; */
  2531. };
  2532. static inline u64 NIXX_AF_LFX_CQS_BASE(u64 a)
  2533. __attribute__ ((pure, always_inline));
  2534. static inline u64 NIXX_AF_LFX_CQS_BASE(u64 a)
  2535. {
  2536. return 0x4070 + 0x20000 * a;
  2537. }
  2538. /**
  2539. * Register (RVU_PF_BAR0) nix#_af_lf#_cqs_cfg
  2540. *
  2541. * NIX AF Local Function Completion Queues Configuration Register This
  2542. * register configures completion queues in the LF.
  2543. */
  2544. union nixx_af_lfx_cqs_cfg {
  2545. u64 u;
  2546. struct nixx_af_lfx_cqs_cfg_s {
  2547. u64 max_queuesm1 : 20;
  2548. u64 way_mask : 16;
  2549. u64 caching : 1;
  2550. u64 reserved_37_63 : 27;
  2551. } s;
  2552. /* struct nixx_af_lfx_cqs_cfg_s cn; */
  2553. };
  2554. static inline u64 NIXX_AF_LFX_CQS_CFG(u64 a)
  2555. __attribute__ ((pure, always_inline));
  2556. static inline u64 NIXX_AF_LFX_CQS_CFG(u64 a)
  2557. {
  2558. return 0x4060 + 0x20000 * a;
  2559. }
  2560. /**
  2561. * Register (RVU_PF_BAR0) nix#_af_lf#_lock#
  2562. *
  2563. * NIX AF Local Function Lockdown Registers Internal: The NIX lockdown
  2564. * depth of 32 bytes is shallow compared to 96 bytes for NIC and meant
  2565. * for outer MAC and/or VLAN (optionally preceded by a small number of
  2566. * skip bytes). NPC's MCAM can be used for deeper protocol-aware
  2567. * lockdown.
  2568. */
  2569. union nixx_af_lfx_lockx {
  2570. u64 u;
  2571. struct nixx_af_lfx_lockx_s {
  2572. u64 data : 32;
  2573. u64 bit_ena : 32;
  2574. } s;
  2575. /* struct nixx_af_lfx_lockx_s cn; */
  2576. };
  2577. static inline u64 NIXX_AF_LFX_LOCKX(u64 a, u64 b)
  2578. __attribute__ ((pure, always_inline));
  2579. static inline u64 NIXX_AF_LFX_LOCKX(u64 a, u64 b)
  2580. {
  2581. return 0x4300 + 0x20000 * a + 8 * b;
  2582. }
  2583. /**
  2584. * Register (RVU_PF_BAR0) nix#_af_lf#_qints_base
  2585. *
  2586. * NIX AF Local Function Queue Interrupts Base Address Registers This
  2587. * register specifies the base AF IOVA of LF's queue interrupt context
  2588. * table in NDC/LLC/DRAM. The table consists of NIX_AF_CONST2[QINTS]
  2589. * contiguous NIX_QINT_HW_S structures. After writing to this register,
  2590. * software should read it back to ensure that the write has completed
  2591. * before accessing any NIX_LF_QINT()_* registers.
  2592. */
  2593. union nixx_af_lfx_qints_base {
  2594. u64 u;
  2595. struct nixx_af_lfx_qints_base_s {
  2596. u64 reserved_0_6 : 7;
  2597. u64 addr : 46;
  2598. u64 reserved_53_63 : 11;
  2599. } s;
  2600. /* struct nixx_af_lfx_qints_base_s cn; */
  2601. };
  2602. static inline u64 NIXX_AF_LFX_QINTS_BASE(u64 a)
  2603. __attribute__ ((pure, always_inline));
  2604. static inline u64 NIXX_AF_LFX_QINTS_BASE(u64 a)
  2605. {
  2606. return 0x4110 + 0x20000 * a;
  2607. }
  2608. /**
  2609. * Register (RVU_PF_BAR0) nix#_af_lf#_qints_cfg
  2610. *
  2611. * NIX AF Local Function Queue Interrupts Configuration Registers This
  2612. * register controls access to the LF's queue interrupt context table in
  2613. * NDC/LLC/DRAM. The table consists of NIX_AF_CONST2[QINTS] contiguous
  2614. * NIX_QINT_HW_S structures. The size of each structure is 1 \<\<
  2615. * NIX_AF_CONST3[QINT_LOG2BYTES]. After writing to this register,
  2616. * software should read it back to ensure that the write has completed
  2617. * before accessing any NIX_LF_QINT()_* registers.
  2618. */
  2619. union nixx_af_lfx_qints_cfg {
  2620. u64 u;
  2621. struct nixx_af_lfx_qints_cfg_s {
  2622. u64 reserved_0_19 : 20;
  2623. u64 way_mask : 16;
  2624. u64 caching : 1;
  2625. u64 reserved_37_63 : 27;
  2626. } s;
  2627. /* struct nixx_af_lfx_qints_cfg_s cn; */
  2628. };
  2629. static inline u64 NIXX_AF_LFX_QINTS_CFG(u64 a)
  2630. __attribute__ ((pure, always_inline));
  2631. static inline u64 NIXX_AF_LFX_QINTS_CFG(u64 a)
  2632. {
  2633. return 0x4100 + 0x20000 * a;
  2634. }
  2635. /**
  2636. * Register (RVU_PF_BAR0) nix#_af_lf#_rqs_base
  2637. *
  2638. * NIX AF Local Function Receive Queues Base Address Register This
  2639. * register specifies the base AF IOVA of the LF's RQ context table. The
  2640. * table consists of NIX_AF_LF()_RQS_CFG[MAX_QUEUESM1]+1 contiguous
  2641. * NIX_RQ_CTX_S structures.
  2642. */
  2643. union nixx_af_lfx_rqs_base {
  2644. u64 u;
  2645. struct nixx_af_lfx_rqs_base_s {
  2646. u64 reserved_0_6 : 7;
  2647. u64 addr : 46;
  2648. u64 reserved_53_63 : 11;
  2649. } s;
  2650. /* struct nixx_af_lfx_rqs_base_s cn; */
  2651. };
  2652. static inline u64 NIXX_AF_LFX_RQS_BASE(u64 a)
  2653. __attribute__ ((pure, always_inline));
  2654. static inline u64 NIXX_AF_LFX_RQS_BASE(u64 a)
  2655. {
  2656. return 0x4050 + 0x20000 * a;
  2657. }
  2658. /**
  2659. * Register (RVU_PF_BAR0) nix#_af_lf#_rqs_cfg
  2660. *
  2661. * NIX AF Local Function Receive Queues Configuration Register This
  2662. * register configures receive queues in the LF.
  2663. */
  2664. union nixx_af_lfx_rqs_cfg {
  2665. u64 u;
  2666. struct nixx_af_lfx_rqs_cfg_s {
  2667. u64 max_queuesm1 : 20;
  2668. u64 way_mask : 16;
  2669. u64 caching : 1;
  2670. u64 reserved_37_63 : 27;
  2671. } s;
  2672. /* struct nixx_af_lfx_rqs_cfg_s cn; */
  2673. };
  2674. static inline u64 NIXX_AF_LFX_RQS_CFG(u64 a)
  2675. __attribute__ ((pure, always_inline));
  2676. static inline u64 NIXX_AF_LFX_RQS_CFG(u64 a)
  2677. {
  2678. return 0x4040 + 0x20000 * a;
  2679. }
  2680. /**
  2681. * Register (RVU_PF_BAR0) nix#_af_lf#_rss_base
  2682. *
  2683. * NIX AF Local Function Receive Size Scaling Table Base Address Register
  2684. * This register specifies the base AF IOVA of the RSS table per LF. The
  2685. * table is present when NIX_AF_LF()_RSS_CFG[ENA] is set and consists of
  2686. * 1 \<\< (NIX_AF_LF()_RSS_CFG[SIZE] + 8) contiguous NIX_RSSE_S
  2687. * structures, where the size of each structure is 1 \<\<
  2688. * NIX_AF_CONST3[RSSE_LOG2BYTES]. See NIX_AF_LF()_RSS_GRP().
  2689. */
  2690. union nixx_af_lfx_rss_base {
  2691. u64 u;
  2692. struct nixx_af_lfx_rss_base_s {
  2693. u64 reserved_0_6 : 7;
  2694. u64 addr : 46;
  2695. u64 reserved_53_63 : 11;
  2696. } s;
  2697. /* struct nixx_af_lfx_rss_base_s cn; */
  2698. };
  2699. static inline u64 NIXX_AF_LFX_RSS_BASE(u64 a)
  2700. __attribute__ ((pure, always_inline));
  2701. static inline u64 NIXX_AF_LFX_RSS_BASE(u64 a)
  2702. {
  2703. return 0x40d0 + 0x20000 * a;
  2704. }
  2705. /**
  2706. * Register (RVU_PF_BAR0) nix#_af_lf#_rss_cfg
  2707. *
  2708. * NIX AF Local Function Receive Size Scaling Table Configuration
  2709. * Register See NIX_AF_LF()_RSS_BASE and NIX_AF_LF()_RSS_GRP().
  2710. */
  2711. union nixx_af_lfx_rss_cfg {
  2712. u64 u;
  2713. struct nixx_af_lfx_rss_cfg_s {
  2714. u64 size : 4;
  2715. u64 ena : 1;
  2716. u64 adder_is_tag_lsb : 1;
  2717. u64 reserved_6_19 : 14;
  2718. u64 way_mask : 16;
  2719. u64 caching : 1;
  2720. u64 reserved_37_63 : 27;
  2721. } s;
  2722. struct nixx_af_lfx_rss_cfg_cn96xxp1 {
  2723. u64 size : 4;
  2724. u64 ena : 1;
  2725. u64 reserved_5_19 : 15;
  2726. u64 way_mask : 16;
  2727. u64 caching : 1;
  2728. u64 reserved_37_63 : 27;
  2729. } cn96xxp1;
  2730. /* struct nixx_af_lfx_rss_cfg_s cn96xxp3; */
  2731. /* struct nixx_af_lfx_rss_cfg_cn96xxp1 cnf95xx; */
  2732. };
  2733. static inline u64 NIXX_AF_LFX_RSS_CFG(u64 a)
  2734. __attribute__ ((pure, always_inline));
  2735. static inline u64 NIXX_AF_LFX_RSS_CFG(u64 a)
  2736. {
  2737. return 0x40c0 + 0x20000 * a;
  2738. }
  2739. /**
  2740. * Register (RVU_PF_BAR0) nix#_af_lf#_rss_grp#
  2741. *
  2742. * NIX AF Local Function Receive Side Scaling Group Registers A receive
  2743. * packet targets a LF's RSS group when its NIX_RX_ACTION_S[OP] =
  2744. * NIX_RX_ACTIONOP_E::RSS, or its target multicast list has an entry with
  2745. * NIX_RX_MCE_S[OP] = NIX_RX_MCOP_E::RSS. The RSS group index (this
  2746. * register's last index) is NIX_RX_ACTION_S[INDEX] or
  2747. * NIX_RX_MCE_S[INDEX]. The RSS computation is as follows: * The
  2748. * packet's flow_tag (see NIX_LF_RX_SECRET()) and RSS group are used to
  2749. * select a NIX_RSSE_S entry in the LF's RSS table (see [SIZEM1]). *
  2750. * NIX_RSSE_S selects the packet's destination RQ.
  2751. */
  2752. union nixx_af_lfx_rss_grpx {
  2753. u64 u;
  2754. struct nixx_af_lfx_rss_grpx_s {
  2755. u64 offset : 11;
  2756. u64 reserved_11_15 : 5;
  2757. u64 sizem1 : 3;
  2758. u64 reserved_19_63 : 45;
  2759. } s;
  2760. /* struct nixx_af_lfx_rss_grpx_s cn; */
  2761. };
  2762. static inline u64 NIXX_AF_LFX_RSS_GRPX(u64 a, u64 b)
  2763. __attribute__ ((pure, always_inline));
  2764. static inline u64 NIXX_AF_LFX_RSS_GRPX(u64 a, u64 b)
  2765. {
  2766. return 0x4600 + 0x20000 * a + 8 * b;
  2767. }
  2768. /**
  2769. * Register (RVU_PF_BAR0) nix#_af_lf#_rx_cfg
  2770. *
  2771. * NIX AF Local Function Receive Configuration Register
  2772. */
  2773. union nixx_af_lfx_rx_cfg {
  2774. u64 u;
  2775. struct nixx_af_lfx_rx_cfg_s {
  2776. u64 reserved_0_31 : 32;
  2777. u64 drop_re : 1;
  2778. u64 lenerr_en : 1;
  2779. u64 ip6_udp_opt : 1;
  2780. u64 dis_apad : 1;
  2781. u64 csum_il4 : 1;
  2782. u64 csum_ol4 : 1;
  2783. u64 len_il4 : 1;
  2784. u64 len_il3 : 1;
  2785. u64 len_ol4 : 1;
  2786. u64 len_ol3 : 1;
  2787. u64 reserved_42_63 : 22;
  2788. } s;
  2789. struct nixx_af_lfx_rx_cfg_cn96xxp1 {
  2790. u64 reserved_0_31 : 32;
  2791. u64 reserved_32 : 1;
  2792. u64 lenerr_en : 1;
  2793. u64 ip6_udp_opt : 1;
  2794. u64 dis_apad : 1;
  2795. u64 csum_il4 : 1;
  2796. u64 csum_ol4 : 1;
  2797. u64 len_il4 : 1;
  2798. u64 len_il3 : 1;
  2799. u64 len_ol4 : 1;
  2800. u64 len_ol3 : 1;
  2801. u64 reserved_42_63 : 22;
  2802. } cn96xxp1;
  2803. /* struct nixx_af_lfx_rx_cfg_s cn96xxp3; */
  2804. /* struct nixx_af_lfx_rx_cfg_s cnf95xx; */
  2805. };
  2806. static inline u64 NIXX_AF_LFX_RX_CFG(u64 a)
  2807. __attribute__ ((pure, always_inline));
  2808. static inline u64 NIXX_AF_LFX_RX_CFG(u64 a)
  2809. {
  2810. return 0x40a0 + 0x20000 * a;
  2811. }
  2812. /**
  2813. * Register (RVU_PF_BAR0) nix#_af_lf#_rx_ipsec_cfg0
  2814. *
  2815. * INTERNAL: NIX AF LF Receive IPSEC Configuration Registers Internal:
  2816. * Not used; no IPSEC fast-path.
  2817. */
  2818. union nixx_af_lfx_rx_ipsec_cfg0 {
  2819. u64 u;
  2820. struct nixx_af_lfx_rx_ipsec_cfg0_s {
  2821. u64 lenm1_max : 14;
  2822. u64 reserved_14_15 : 2;
  2823. u64 sa_pow2_size : 4;
  2824. u64 tag_const : 24;
  2825. u64 tt : 2;
  2826. u64 defcpt : 1;
  2827. u64 hshcpt : 1;
  2828. u64 reserved_48_63 : 16;
  2829. } s;
  2830. /* struct nixx_af_lfx_rx_ipsec_cfg0_s cn; */
  2831. };
  2832. static inline u64 NIXX_AF_LFX_RX_IPSEC_CFG0(u64 a)
  2833. __attribute__ ((pure, always_inline));
  2834. static inline u64 NIXX_AF_LFX_RX_IPSEC_CFG0(u64 a)
  2835. {
  2836. return 0x4140 + 0x20000 * a;
  2837. }
  2838. /**
  2839. * Register (RVU_PF_BAR0) nix#_af_lf#_rx_ipsec_cfg1
  2840. *
  2841. * INTERNAL: NIX AF LF Receive IPSEC Security Association Configuration
  2842. * Register Internal: Not used; no IPSEC fast-path.
  2843. */
  2844. union nixx_af_lfx_rx_ipsec_cfg1 {
  2845. u64 u;
  2846. struct nixx_af_lfx_rx_ipsec_cfg1_s {
  2847. u64 sa_idx_max : 32;
  2848. u64 sa_idx_w : 5;
  2849. u64 reserved_37_63 : 27;
  2850. } s;
  2851. /* struct nixx_af_lfx_rx_ipsec_cfg1_s cn; */
  2852. };
  2853. static inline u64 NIXX_AF_LFX_RX_IPSEC_CFG1(u64 a)
  2854. __attribute__ ((pure, always_inline));
  2855. static inline u64 NIXX_AF_LFX_RX_IPSEC_CFG1(u64 a)
  2856. {
  2857. return 0x4148 + 0x20000 * a;
  2858. }
  2859. /**
  2860. * Register (RVU_PF_BAR0) nix#_af_lf#_rx_ipsec_dyno_base
  2861. *
  2862. * INTERNAL: NIX AF LF Receive IPSEC Dynamic Ordering Base Address
  2863. * Registers Internal: Not used; no IPSEC fast-path.
  2864. */
  2865. union nixx_af_lfx_rx_ipsec_dyno_base {
  2866. u64 u;
  2867. struct nixx_af_lfx_rx_ipsec_dyno_base_s {
  2868. u64 reserved_0_6 : 7;
  2869. u64 addr : 46;
  2870. u64 reserved_53_63 : 11;
  2871. } s;
  2872. /* struct nixx_af_lfx_rx_ipsec_dyno_base_s cn; */
  2873. };
  2874. static inline u64 NIXX_AF_LFX_RX_IPSEC_DYNO_BASE(u64 a)
  2875. __attribute__ ((pure, always_inline));
  2876. static inline u64 NIXX_AF_LFX_RX_IPSEC_DYNO_BASE(u64 a)
  2877. {
  2878. return 0x4158 + 0x20000 * a;
  2879. }
  2880. /**
  2881. * Register (RVU_PF_BAR0) nix#_af_lf#_rx_ipsec_dyno_cfg
  2882. *
  2883. * INTERNAL: NIX AF LF Receive IPSEC Dynamic Ordering Base Address
  2884. * Registers Internal: Not used; no IPSEC fast-path.
  2885. */
  2886. union nixx_af_lfx_rx_ipsec_dyno_cfg {
  2887. u64 u;
  2888. struct nixx_af_lfx_rx_ipsec_dyno_cfg_s {
  2889. u64 dyno_idx_w : 4;
  2890. u64 dyno_ena : 1;
  2891. u64 reserved_5_19 : 15;
  2892. u64 way_mask : 16;
  2893. u64 caching : 1;
  2894. u64 reserved_37_63 : 27;
  2895. } s;
  2896. /* struct nixx_af_lfx_rx_ipsec_dyno_cfg_s cn; */
  2897. };
  2898. static inline u64 NIXX_AF_LFX_RX_IPSEC_DYNO_CFG(u64 a)
  2899. __attribute__ ((pure, always_inline));
  2900. static inline u64 NIXX_AF_LFX_RX_IPSEC_DYNO_CFG(u64 a)
  2901. {
  2902. return 0x4150 + 0x20000 * a;
  2903. }
  2904. /**
  2905. * Register (RVU_PF_BAR0) nix#_af_lf#_rx_ipsec_sa_base
  2906. *
  2907. * INTERNAL: NIX AF LF Receive IPSEC Security Association Base Address
  2908. * Register Internal: Not used; no IPSEC fast-path.
  2909. */
  2910. union nixx_af_lfx_rx_ipsec_sa_base {
  2911. u64 u;
  2912. struct nixx_af_lfx_rx_ipsec_sa_base_s {
  2913. u64 reserved_0_6 : 7;
  2914. u64 addr : 46;
  2915. u64 reserved_53_63 : 11;
  2916. } s;
  2917. /* struct nixx_af_lfx_rx_ipsec_sa_base_s cn; */
  2918. };
  2919. static inline u64 NIXX_AF_LFX_RX_IPSEC_SA_BASE(u64 a)
  2920. __attribute__ ((pure, always_inline));
  2921. static inline u64 NIXX_AF_LFX_RX_IPSEC_SA_BASE(u64 a)
  2922. {
  2923. return 0x4170 + 0x20000 * a;
  2924. }
  2925. /**
  2926. * Register (RVU_PF_BAR0) nix#_af_lf#_rx_stat#
  2927. *
  2928. * NIX AF Local Function Receive Statistics Registers The last dimension
  2929. * indicates which statistic, and is enumerated by NIX_STAT_LF_RX_E.
  2930. */
  2931. union nixx_af_lfx_rx_statx {
  2932. u64 u;
  2933. struct nixx_af_lfx_rx_statx_s {
  2934. u64 stat : 48;
  2935. u64 reserved_48_63 : 16;
  2936. } s;
  2937. /* struct nixx_af_lfx_rx_statx_s cn; */
  2938. };
  2939. static inline u64 NIXX_AF_LFX_RX_STATX(u64 a, u64 b)
  2940. __attribute__ ((pure, always_inline));
  2941. static inline u64 NIXX_AF_LFX_RX_STATX(u64 a, u64 b)
  2942. {
  2943. return 0x4500 + 0x20000 * a + 8 * b;
  2944. }
  2945. /**
  2946. * Register (RVU_PF_BAR0) nix#_af_lf#_rx_vtag_type#
  2947. *
  2948. * NIX AF Local Function Receive Vtag Type Registers These registers
  2949. * specify optional Vtag (e.g. VLAN, E-TAG) actions for received packets.
  2950. * Indexed by NIX_RX_VTAG_ACTION_S[VTAG*_TYPE].
  2951. */
  2952. union nixx_af_lfx_rx_vtag_typex {
  2953. u64 u;
  2954. struct nixx_af_lfx_rx_vtag_typex_s {
  2955. u64 size : 1;
  2956. u64 reserved_1_3 : 3;
  2957. u64 strip : 1;
  2958. u64 capture : 1;
  2959. u64 reserved_6_63 : 58;
  2960. } s;
  2961. /* struct nixx_af_lfx_rx_vtag_typex_s cn; */
  2962. };
  2963. static inline u64 NIXX_AF_LFX_RX_VTAG_TYPEX(u64 a, u64 b)
  2964. __attribute__ ((pure, always_inline));
  2965. static inline u64 NIXX_AF_LFX_RX_VTAG_TYPEX(u64 a, u64 b)
  2966. {
  2967. return 0x4200 + 0x20000 * a + 8 * b;
  2968. }
  2969. /**
  2970. * Register (RVU_PF_BAR0) nix#_af_lf#_sqs_base
  2971. *
  2972. * NIX AF Local Function Send Queues Base Address Register This register
  2973. * specifies the base AF IOVA of the LF's SQ context table. The table
  2974. * consists of NIX_AF_LF()_SQS_CFG[MAX_QUEUESM1]+1 contiguous
  2975. * NIX_SQ_CTX_HW_S structures.
  2976. */
  2977. union nixx_af_lfx_sqs_base {
  2978. u64 u;
  2979. struct nixx_af_lfx_sqs_base_s {
  2980. u64 reserved_0_6 : 7;
  2981. u64 addr : 46;
  2982. u64 reserved_53_63 : 11;
  2983. } s;
  2984. /* struct nixx_af_lfx_sqs_base_s cn; */
  2985. };
  2986. static inline u64 NIXX_AF_LFX_SQS_BASE(u64 a)
  2987. __attribute__ ((pure, always_inline));
  2988. static inline u64 NIXX_AF_LFX_SQS_BASE(u64 a)
  2989. {
  2990. return 0x4030 + 0x20000 * a;
  2991. }
  2992. /**
  2993. * Register (RVU_PF_BAR0) nix#_af_lf#_sqs_cfg
  2994. *
  2995. * NIX AF Local Function Send Queues Configuration Register This register
  2996. * configures send queues in the LF.
  2997. */
  2998. union nixx_af_lfx_sqs_cfg {
  2999. u64 u;
  3000. struct nixx_af_lfx_sqs_cfg_s {
  3001. u64 max_queuesm1 : 20;
  3002. u64 way_mask : 16;
  3003. u64 caching : 1;
  3004. u64 reserved_37_63 : 27;
  3005. } s;
  3006. /* struct nixx_af_lfx_sqs_cfg_s cn; */
  3007. };
  3008. static inline u64 NIXX_AF_LFX_SQS_CFG(u64 a)
  3009. __attribute__ ((pure, always_inline));
  3010. static inline u64 NIXX_AF_LFX_SQS_CFG(u64 a)
  3011. {
  3012. return 0x4020 + 0x20000 * a;
  3013. }
  3014. /**
  3015. * Register (RVU_PF_BAR0) nix#_af_lf#_tx_cfg
  3016. *
  3017. * NIX AF Local Function Transmit Configuration Register
  3018. */
  3019. union nixx_af_lfx_tx_cfg {
  3020. u64 u;
  3021. struct nixx_af_lfx_tx_cfg_s {
  3022. u64 vlan0_ins_etype : 16;
  3023. u64 vlan1_ins_etype : 16;
  3024. u64 send_tstmp_ena : 1;
  3025. u64 lock_viol_cqe_ena : 1;
  3026. u64 lock_ena : 1;
  3027. u64 reserved_35_63 : 29;
  3028. } s;
  3029. /* struct nixx_af_lfx_tx_cfg_s cn; */
  3030. };
  3031. static inline u64 NIXX_AF_LFX_TX_CFG(u64 a)
  3032. __attribute__ ((pure, always_inline));
  3033. static inline u64 NIXX_AF_LFX_TX_CFG(u64 a)
  3034. {
  3035. return 0x4080 + 0x20000 * a;
  3036. }
  3037. /**
  3038. * Register (RVU_PF_BAR0) nix#_af_lf#_tx_cfg2
  3039. *
  3040. * NIX AF Local Function Transmit Configuration Register
  3041. */
  3042. union nixx_af_lfx_tx_cfg2 {
  3043. u64 u;
  3044. struct nixx_af_lfx_tx_cfg2_s {
  3045. u64 lmt_ena : 1;
  3046. u64 reserved_1_63 : 63;
  3047. } s;
  3048. /* struct nixx_af_lfx_tx_cfg2_s cn; */
  3049. };
  3050. static inline u64 NIXX_AF_LFX_TX_CFG2(u64 a)
  3051. __attribute__ ((pure, always_inline));
  3052. static inline u64 NIXX_AF_LFX_TX_CFG2(u64 a)
  3053. {
  3054. return 0x4028 + 0x20000 * a;
  3055. }
  3056. /**
  3057. * Register (RVU_PF_BAR0) nix#_af_lf#_tx_parse_cfg
  3058. *
  3059. * NIX AF Local Function Transmit Parse Configuration Register
  3060. */
  3061. union nixx_af_lfx_tx_parse_cfg {
  3062. u64 u;
  3063. struct nixx_af_lfx_tx_parse_cfg_s {
  3064. u64 pkind : 6;
  3065. u64 reserved_6_63 : 58;
  3066. } s;
  3067. /* struct nixx_af_lfx_tx_parse_cfg_s cn; */
  3068. };
  3069. static inline u64 NIXX_AF_LFX_TX_PARSE_CFG(u64 a)
  3070. __attribute__ ((pure, always_inline));
  3071. static inline u64 NIXX_AF_LFX_TX_PARSE_CFG(u64 a)
  3072. {
  3073. return 0x4090 + 0x20000 * a;
  3074. }
  3075. /**
  3076. * Register (RVU_PF_BAR0) nix#_af_lf#_tx_stat#
  3077. *
  3078. * NIX AF Local Function Transmit Statistics Registers The last dimension
  3079. * indicates which statistic, and is enumerated by NIX_STAT_LF_TX_E.
  3080. */
  3081. union nixx_af_lfx_tx_statx {
  3082. u64 u;
  3083. struct nixx_af_lfx_tx_statx_s {
  3084. u64 stat : 48;
  3085. u64 reserved_48_63 : 16;
  3086. } s;
  3087. /* struct nixx_af_lfx_tx_statx_s cn; */
  3088. };
  3089. static inline u64 NIXX_AF_LFX_TX_STATX(u64 a, u64 b)
  3090. __attribute__ ((pure, always_inline));
  3091. static inline u64 NIXX_AF_LFX_TX_STATX(u64 a, u64 b)
  3092. {
  3093. return 0x4400 + 0x20000 * a + 8 * b;
  3094. }
  3095. /**
  3096. * Register (RVU_PF_BAR0) nix#_af_lf#_tx_status
  3097. *
  3098. * NIX AF LF Transmit Status Register
  3099. */
  3100. union nixx_af_lfx_tx_status {
  3101. u64 u;
  3102. struct nixx_af_lfx_tx_status_s {
  3103. u64 sq_ctx_err : 1;
  3104. u64 reserved_1_63 : 63;
  3105. } s;
  3106. /* struct nixx_af_lfx_tx_status_s cn; */
  3107. };
  3108. static inline u64 NIXX_AF_LFX_TX_STATUS(u64 a)
  3109. __attribute__ ((pure, always_inline));
  3110. static inline u64 NIXX_AF_LFX_TX_STATUS(u64 a)
  3111. {
  3112. return 0x4180 + 0x20000 * a;
  3113. }
  3114. /**
  3115. * Register (RVU_PF_BAR0) nix#_af_lf_rst
  3116. *
  3117. * NIX Admin Function LF Reset Register
  3118. */
  3119. union nixx_af_lf_rst {
  3120. u64 u;
  3121. struct nixx_af_lf_rst_s {
  3122. u64 lf : 8;
  3123. u64 reserved_8_11 : 4;
  3124. u64 exec : 1;
  3125. u64 reserved_13_63 : 51;
  3126. } s;
  3127. /* struct nixx_af_lf_rst_s cn; */
  3128. };
  3129. static inline u64 NIXX_AF_LF_RST(void)
  3130. __attribute__ ((pure, always_inline));
  3131. static inline u64 NIXX_AF_LF_RST(void)
  3132. {
  3133. return 0x150;
  3134. }
  3135. /**
  3136. * Register (RVU_PF_BAR0) nix#_af_lso_cfg
  3137. *
  3138. * NIX AF Large Send Offload Configuration Register
  3139. */
  3140. union nixx_af_lso_cfg {
  3141. u64 u;
  3142. struct nixx_af_lso_cfg_s {
  3143. u64 tcp_lsf : 16;
  3144. u64 tcp_msf : 16;
  3145. u64 tcp_fsf : 16;
  3146. u64 reserved_48_62 : 15;
  3147. u64 enable : 1;
  3148. } s;
  3149. /* struct nixx_af_lso_cfg_s cn; */
  3150. };
  3151. static inline u64 NIXX_AF_LSO_CFG(void)
  3152. __attribute__ ((pure, always_inline));
  3153. static inline u64 NIXX_AF_LSO_CFG(void)
  3154. {
  3155. return 0xa8;
  3156. }
  3157. /**
  3158. * Register (RVU_PF_BAR0) nix#_af_lso_format#_field#
  3159. *
  3160. * NIX AF Large Send Offload Format Field Registers These registers
  3161. * specify LSO packet modification formats. Each format may modify up to
  3162. * eight packet fields with the following constraints: * If fewer than
  3163. * eight fields are modified, [ALG] must be NIX_LSOALG_E::NOP in the
  3164. * unused field registers. * Modified fields must be specified in
  3165. * contiguous field registers starting with NIX_AF_LSO_FORMAT()_FIELD(0).
  3166. * * Modified fields cannot overlap. * Multiple fields with the same
  3167. * [LAYER] value must be specified in ascending [OFFSET] order. * Fields
  3168. * in different layers must be specified in ascending [LAYER] order.
  3169. */
  3170. union nixx_af_lso_formatx_fieldx {
  3171. u64 u;
  3172. struct nixx_af_lso_formatx_fieldx_s {
  3173. u64 offset : 8;
  3174. u64 layer : 2;
  3175. u64 reserved_10_11 : 2;
  3176. u64 sizem1 : 2;
  3177. u64 reserved_14_15 : 2;
  3178. u64 alg : 3;
  3179. u64 reserved_19_63 : 45;
  3180. } s;
  3181. /* struct nixx_af_lso_formatx_fieldx_s cn; */
  3182. };
  3183. static inline u64 NIXX_AF_LSO_FORMATX_FIELDX(u64 a, u64 b)
  3184. __attribute__ ((pure, always_inline));
  3185. static inline u64 NIXX_AF_LSO_FORMATX_FIELDX(u64 a, u64 b)
  3186. {
  3187. return 0x1b00 + 0x10000 * a + 8 * b;
  3188. }
  3189. /**
  3190. * Register (RVU_PF_BAR0) nix#_af_mark_format#_ctl
  3191. *
  3192. * NIX AF Packet Marking Format Registers Describes packet marking
  3193. * calculations for YELLOW and for NIX_COLORRESULT_E::RED_SEND packets.
  3194. * NIX_SEND_EXT_S[MARKFORM] selects the CSR used for the packet
  3195. * descriptor. All the packet marking offset calculations assume big-
  3196. * endian bits within a byte. For example, if NIX_SEND_EXT_S[MARKPTR] is
  3197. * 3 and [OFFSET] is 5 and the packet is YELLOW, the NIX marking hardware
  3198. * would do this: _ byte[3]\<2:0\> |= [Y_VAL]\<3:1\> _
  3199. * byte[3]\<2:0\> &= ~[Y_MASK]\<3:1\> _ byte[4]\<7\> |= [Y_VAL]\<0\>
  3200. * _ byte[4]\<7\> &= ~[Y_MASK]\<0\> where byte[3] is the third byte
  3201. * in the packet, and byte[4] the fourth. For another example, if
  3202. * NIX_SEND_EXT_S[MARKPTR] is 3 and [OFFSET] is 0 and the packet is
  3203. * NIX_COLORRESULT_E::RED_SEND, _ byte[3]\<7:4\> |= [R_VAL]\<3:0\> _
  3204. * byte[3]\<7:4\> &= ~[R_MASK]\<3:0\>
  3205. */
  3206. union nixx_af_mark_formatx_ctl {
  3207. u64 u;
  3208. struct nixx_af_mark_formatx_ctl_s {
  3209. u64 r_val : 4;
  3210. u64 r_mask : 4;
  3211. u64 y_val : 4;
  3212. u64 y_mask : 4;
  3213. u64 offset : 3;
  3214. u64 reserved_19_63 : 45;
  3215. } s;
  3216. /* struct nixx_af_mark_formatx_ctl_s cn; */
  3217. };
  3218. static inline u64 NIXX_AF_MARK_FORMATX_CTL(u64 a)
  3219. __attribute__ ((pure, always_inline));
  3220. static inline u64 NIXX_AF_MARK_FORMATX_CTL(u64 a)
  3221. {
  3222. return 0x900 + 0x40000 * a;
  3223. }
  3224. /**
  3225. * Register (RVU_PF_BAR0) nix#_af_mc_mirror_const
  3226. *
  3227. * NIX AF Multicast/Mirror Constants Register This register contains
  3228. * constants for software discovery.
  3229. */
  3230. union nixx_af_mc_mirror_const {
  3231. u64 u;
  3232. struct nixx_af_mc_mirror_const_s {
  3233. u64 buf_size : 16;
  3234. u64 reserved_16_63 : 48;
  3235. } s;
  3236. /* struct nixx_af_mc_mirror_const_s cn; */
  3237. };
  3238. static inline u64 NIXX_AF_MC_MIRROR_CONST(void)
  3239. __attribute__ ((pure, always_inline));
  3240. static inline u64 NIXX_AF_MC_MIRROR_CONST(void)
  3241. {
  3242. return 0x98;
  3243. }
  3244. /**
  3245. * Register (RVU_PF_BAR0) nix#_af_mdq#_cir
  3246. *
  3247. * NIX AF Meta Descriptor Queue Committed Information Rate Registers This
  3248. * register has the same bit fields as NIX_AF_TL1()_CIR.
  3249. */
  3250. union nixx_af_mdqx_cir {
  3251. u64 u;
  3252. struct nixx_af_mdqx_cir_s {
  3253. u64 enable : 1;
  3254. u64 rate_mantissa : 8;
  3255. u64 rate_exponent : 4;
  3256. u64 rate_divider_exponent : 4;
  3257. u64 reserved_17_28 : 12;
  3258. u64 burst_mantissa : 8;
  3259. u64 burst_exponent : 4;
  3260. u64 reserved_41_63 : 23;
  3261. } s;
  3262. /* struct nixx_af_mdqx_cir_s cn; */
  3263. };
  3264. static inline u64 NIXX_AF_MDQX_CIR(u64 a)
  3265. __attribute__ ((pure, always_inline));
  3266. static inline u64 NIXX_AF_MDQX_CIR(u64 a)
  3267. {
  3268. return 0x1420 + 0x10000 * a;
  3269. }
  3270. /**
  3271. * Register (RVU_PF_BAR0) nix#_af_mdq#_md_debug
  3272. *
  3273. * NIX AF Meta Descriptor Queue Meta Descriptor State Debug Registers
  3274. * This register provides access to the meta descriptor at the front of
  3275. * the MDQ. An MDQ can hold up to 8 packet meta descriptors (PMD) and one
  3276. * flush meta descriptor (FMD).
  3277. */
  3278. union nixx_af_mdqx_md_debug {
  3279. u64 u;
  3280. struct nixx_af_mdqx_md_debug_s {
  3281. u64 pkt_len : 16;
  3282. u64 red_algo_override : 2;
  3283. u64 shp_dis : 1;
  3284. u64 reserved_19 : 1;
  3285. u64 shp_chg : 9;
  3286. u64 reserved_29_31 : 3;
  3287. u64 sqm_pkt_id : 13;
  3288. u64 reserved_45_60 : 16;
  3289. u64 md_type : 2;
  3290. u64 reserved_63 : 1;
  3291. } s;
  3292. /* struct nixx_af_mdqx_md_debug_s cn; */
  3293. };
  3294. static inline u64 NIXX_AF_MDQX_MD_DEBUG(u64 a)
  3295. __attribute__ ((pure, always_inline));
  3296. static inline u64 NIXX_AF_MDQX_MD_DEBUG(u64 a)
  3297. {
  3298. return 0x14c0 + 0x10000 * a;
  3299. }
  3300. /**
  3301. * Register (RVU_PF_BAR0) nix#_af_mdq#_parent
  3302. *
  3303. * NIX AF Meta Descriptor Queue Topology Registers
  3304. */
  3305. union nixx_af_mdqx_parent {
  3306. u64 u;
  3307. struct nixx_af_mdqx_parent_s {
  3308. u64 reserved_0_15 : 16;
  3309. u64 parent : 9;
  3310. u64 reserved_25_63 : 39;
  3311. } s;
  3312. /* struct nixx_af_mdqx_parent_s cn; */
  3313. };
  3314. static inline u64 NIXX_AF_MDQX_PARENT(u64 a)
  3315. __attribute__ ((pure, always_inline));
  3316. static inline u64 NIXX_AF_MDQX_PARENT(u64 a)
  3317. {
  3318. return 0x1480 + 0x10000 * a;
  3319. }
  3320. /**
  3321. * Register (RVU_PF_BAR0) nix#_af_mdq#_pir
  3322. *
  3323. * NIX AF Meta Descriptor Queue Peak Information Rate Registers This
  3324. * register has the same bit fields as NIX_AF_TL1()_CIR.
  3325. */
  3326. union nixx_af_mdqx_pir {
  3327. u64 u;
  3328. struct nixx_af_mdqx_pir_s {
  3329. u64 enable : 1;
  3330. u64 rate_mantissa : 8;
  3331. u64 rate_exponent : 4;
  3332. u64 rate_divider_exponent : 4;
  3333. u64 reserved_17_28 : 12;
  3334. u64 burst_mantissa : 8;
  3335. u64 burst_exponent : 4;
  3336. u64 reserved_41_63 : 23;
  3337. } s;
  3338. /* struct nixx_af_mdqx_pir_s cn; */
  3339. };
  3340. static inline u64 NIXX_AF_MDQX_PIR(u64 a)
  3341. __attribute__ ((pure, always_inline));
  3342. static inline u64 NIXX_AF_MDQX_PIR(u64 a)
  3343. {
  3344. return 0x1430 + 0x10000 * a;
  3345. }
  3346. /**
  3347. * Register (RVU_PF_BAR0) nix#_af_mdq#_pointers
  3348. *
  3349. * INTERNAL: NIX AF Meta Descriptor 4 Linked List Pointers Debug Register
  3350. * This register has the same bit fields as NIX_AF_TL4()_POINTERS.
  3351. */
  3352. union nixx_af_mdqx_pointers {
  3353. u64 u;
  3354. struct nixx_af_mdqx_pointers_s {
  3355. u64 next : 9;
  3356. u64 reserved_9_15 : 7;
  3357. u64 prev : 9;
  3358. u64 reserved_25_63 : 39;
  3359. } s;
  3360. /* struct nixx_af_mdqx_pointers_s cn; */
  3361. };
  3362. static inline u64 NIXX_AF_MDQX_POINTERS(u64 a)
  3363. __attribute__ ((pure, always_inline));
  3364. static inline u64 NIXX_AF_MDQX_POINTERS(u64 a)
  3365. {
  3366. return 0x1460 + 0x10000 * a;
  3367. }
  3368. /**
  3369. * Register (RVU_PF_BAR0) nix#_af_mdq#_ptr_fifo
  3370. *
  3371. * INTERNAL: NIX Meta Descriptor Queue Pointer FIFO State Debug Registers
  3372. */
  3373. union nixx_af_mdqx_ptr_fifo {
  3374. u64 u;
  3375. struct nixx_af_mdqx_ptr_fifo_s {
  3376. u64 tail : 4;
  3377. u64 head : 4;
  3378. u64 p_con : 1;
  3379. u64 reserved_9_63 : 55;
  3380. } s;
  3381. /* struct nixx_af_mdqx_ptr_fifo_s cn; */
  3382. };
  3383. static inline u64 NIXX_AF_MDQX_PTR_FIFO(u64 a)
  3384. __attribute__ ((pure, always_inline));
  3385. static inline u64 NIXX_AF_MDQX_PTR_FIFO(u64 a)
  3386. {
  3387. return 0x14d0 + 0x10000 * a;
  3388. }
  3389. /**
  3390. * Register (RVU_PF_BAR0) nix#_af_mdq#_sched_state
  3391. *
  3392. * NIX AF Meta Descriptor Queue Scheduling Control State Registers This
  3393. * register has the same bit fields as NIX_AF_TL2()_SCHED_STATE.
  3394. */
  3395. union nixx_af_mdqx_sched_state {
  3396. u64 u;
  3397. struct nixx_af_mdqx_sched_state_s {
  3398. u64 rr_count : 25;
  3399. u64 reserved_25_63 : 39;
  3400. } s;
  3401. /* struct nixx_af_mdqx_sched_state_s cn; */
  3402. };
  3403. static inline u64 NIXX_AF_MDQX_SCHED_STATE(u64 a)
  3404. __attribute__ ((pure, always_inline));
  3405. static inline u64 NIXX_AF_MDQX_SCHED_STATE(u64 a)
  3406. {
  3407. return 0x1440 + 0x10000 * a;
  3408. }
  3409. /**
  3410. * Register (RVU_PF_BAR0) nix#_af_mdq#_schedule
  3411. *
  3412. * NIX AF Meta Descriptor Queue Scheduling Control Registers This
  3413. * register has the same bit fields as NIX_AF_TL2()_SCHEDULE.
  3414. */
  3415. union nixx_af_mdqx_schedule {
  3416. u64 u;
  3417. struct nixx_af_mdqx_schedule_s {
  3418. u64 rr_quantum : 24;
  3419. u64 prio : 4;
  3420. u64 reserved_28_63 : 36;
  3421. } s;
  3422. /* struct nixx_af_mdqx_schedule_s cn; */
  3423. };
  3424. static inline u64 NIXX_AF_MDQX_SCHEDULE(u64 a)
  3425. __attribute__ ((pure, always_inline));
  3426. static inline u64 NIXX_AF_MDQX_SCHEDULE(u64 a)
  3427. {
  3428. return 0x1400 + 0x10000 * a;
  3429. }
  3430. /**
  3431. * Register (RVU_PF_BAR0) nix#_af_mdq#_shape
  3432. *
  3433. * NIX AF Meta Descriptor Queue Shaping Control Registers This register
  3434. * has the same bit fields as NIX_AF_TL3()_SHAPE.
  3435. */
  3436. union nixx_af_mdqx_shape {
  3437. u64 u;
  3438. struct nixx_af_mdqx_shape_s {
  3439. u64 adjust : 9;
  3440. u64 red_algo : 2;
  3441. u64 red_disable : 1;
  3442. u64 yellow_disable : 1;
  3443. u64 reserved_13_23 : 11;
  3444. u64 length_disable : 1;
  3445. u64 schedule_list : 2;
  3446. u64 reserved_27_63 : 37;
  3447. } s;
  3448. /* struct nixx_af_mdqx_shape_s cn; */
  3449. };
  3450. static inline u64 NIXX_AF_MDQX_SHAPE(u64 a)
  3451. __attribute__ ((pure, always_inline));
  3452. static inline u64 NIXX_AF_MDQX_SHAPE(u64 a)
  3453. {
  3454. return 0x1410 + 0x10000 * a;
  3455. }
  3456. /**
  3457. * Register (RVU_PF_BAR0) nix#_af_mdq#_shape_state
  3458. *
  3459. * NIX AF Meta Descriptor Queue Shaping State Registers This register has
  3460. * the same bit fields as NIX_AF_TL2()_SHAPE_STATE. This register must
  3461. * not be written during normal operation.
  3462. */
  3463. union nixx_af_mdqx_shape_state {
  3464. u64 u;
  3465. struct nixx_af_mdqx_shape_state_s {
  3466. u64 cir_accum : 26;
  3467. u64 pir_accum : 26;
  3468. u64 color : 2;
  3469. u64 reserved_54_63 : 10;
  3470. } s;
  3471. /* struct nixx_af_mdqx_shape_state_s cn; */
  3472. };
  3473. static inline u64 NIXX_AF_MDQX_SHAPE_STATE(u64 a)
  3474. __attribute__ ((pure, always_inline));
  3475. static inline u64 NIXX_AF_MDQX_SHAPE_STATE(u64 a)
  3476. {
  3477. return 0x1450 + 0x10000 * a;
  3478. }
  3479. /**
  3480. * Register (RVU_PF_BAR0) nix#_af_mdq#_sw_xoff
  3481. *
  3482. * NIX AF Meta Descriptor Controlled XOFF Registers This register has the
  3483. * same bit fields as NIX_AF_TL1()_SW_XOFF
  3484. */
  3485. union nixx_af_mdqx_sw_xoff {
  3486. u64 u;
  3487. struct nixx_af_mdqx_sw_xoff_s {
  3488. u64 xoff : 1;
  3489. u64 drain : 1;
  3490. u64 reserved_2 : 1;
  3491. u64 drain_irq : 1;
  3492. u64 reserved_4_63 : 60;
  3493. } s;
  3494. /* struct nixx_af_mdqx_sw_xoff_s cn; */
  3495. };
  3496. static inline u64 NIXX_AF_MDQX_SW_XOFF(u64 a)
  3497. __attribute__ ((pure, always_inline));
  3498. static inline u64 NIXX_AF_MDQX_SW_XOFF(u64 a)
  3499. {
  3500. return 0x1470 + 0x10000 * a;
  3501. }
  3502. /**
  3503. * Register (RVU_PF_BAR0) nix#_af_mdq_const
  3504. *
  3505. * NIX AF Meta Descriptor Queue Constants Register This register contains
  3506. * constants for software discovery.
  3507. */
  3508. union nixx_af_mdq_const {
  3509. u64 u;
  3510. struct nixx_af_mdq_const_s {
  3511. u64 count : 16;
  3512. u64 reserved_16_63 : 48;
  3513. } s;
  3514. /* struct nixx_af_mdq_const_s cn; */
  3515. };
  3516. static inline u64 NIXX_AF_MDQ_CONST(void)
  3517. __attribute__ ((pure, always_inline));
  3518. static inline u64 NIXX_AF_MDQ_CONST(void)
  3519. {
  3520. return 0x90;
  3521. }
  3522. /**
  3523. * Register (RVU_PF_BAR0) nix#_af_ndc_cfg
  3524. *
  3525. * NIX AF General Configuration Register
  3526. */
  3527. union nixx_af_ndc_cfg {
  3528. u64 u;
  3529. struct nixx_af_ndc_cfg_s {
  3530. u64 ndc_ign_pois : 1;
  3531. u64 byp_sq : 1;
  3532. u64 byp_sqb : 1;
  3533. u64 byp_cqs : 1;
  3534. u64 byp_cints : 1;
  3535. u64 byp_dyno : 1;
  3536. u64 byp_mce : 1;
  3537. u64 byp_rqc : 1;
  3538. u64 byp_rsse : 1;
  3539. u64 byp_mc_data : 1;
  3540. u64 byp_mc_wqe : 1;
  3541. u64 byp_mr_data : 1;
  3542. u64 byp_mr_wqe : 1;
  3543. u64 byp_qints : 1;
  3544. u64 reserved_14_63 : 50;
  3545. } s;
  3546. /* struct nixx_af_ndc_cfg_s cn; */
  3547. };
  3548. static inline u64 NIXX_AF_NDC_CFG(void)
  3549. __attribute__ ((pure, always_inline));
  3550. static inline u64 NIXX_AF_NDC_CFG(void)
  3551. {
  3552. return 0x18;
  3553. }
  3554. /**
  3555. * Register (RVU_PF_BAR0) nix#_af_ndc_rx_sync
  3556. *
  3557. * NIX AF Receive NDC Sync Register Used to synchronize the NIX receive
  3558. * NDC (NDC_IDX_E::NIX()_RX).
  3559. */
  3560. union nixx_af_ndc_rx_sync {
  3561. u64 u;
  3562. struct nixx_af_ndc_rx_sync_s {
  3563. u64 lf : 8;
  3564. u64 reserved_8_11 : 4;
  3565. u64 exec : 1;
  3566. u64 reserved_13_63 : 51;
  3567. } s;
  3568. /* struct nixx_af_ndc_rx_sync_s cn; */
  3569. };
  3570. static inline u64 NIXX_AF_NDC_RX_SYNC(void)
  3571. __attribute__ ((pure, always_inline));
  3572. static inline u64 NIXX_AF_NDC_RX_SYNC(void)
  3573. {
  3574. return 0x3e0;
  3575. }
  3576. /**
  3577. * Register (RVU_PF_BAR0) nix#_af_ndc_tx_sync
  3578. *
  3579. * NIX AF NDC_TX Sync Register Used to synchronize the NIX transmit NDC
  3580. * (NDC_IDX_E::NIX()_TX).
  3581. */
  3582. union nixx_af_ndc_tx_sync {
  3583. u64 u;
  3584. struct nixx_af_ndc_tx_sync_s {
  3585. u64 lf : 8;
  3586. u64 reserved_8_11 : 4;
  3587. u64 exec : 1;
  3588. u64 reserved_13_63 : 51;
  3589. } s;
  3590. /* struct nixx_af_ndc_tx_sync_s cn; */
  3591. };
  3592. static inline u64 NIXX_AF_NDC_TX_SYNC(void)
  3593. __attribute__ ((pure, always_inline));
  3594. static inline u64 NIXX_AF_NDC_TX_SYNC(void)
  3595. {
  3596. return 0x3f0;
  3597. }
  3598. /**
  3599. * Register (RVU_PF_BAR0) nix#_af_norm_tx_fifo_status
  3600. *
  3601. * NIX AF Normal Transmit FIFO Status Register Status of FIFO which
  3602. * transmits normal packets to CGX and LBK.
  3603. */
  3604. union nixx_af_norm_tx_fifo_status {
  3605. u64 u;
  3606. struct nixx_af_norm_tx_fifo_status_s {
  3607. u64 count : 12;
  3608. u64 reserved_12_63 : 52;
  3609. } s;
  3610. /* struct nixx_af_norm_tx_fifo_status_s cn; */
  3611. };
  3612. static inline u64 NIXX_AF_NORM_TX_FIFO_STATUS(void)
  3613. __attribute__ ((pure, always_inline));
  3614. static inline u64 NIXX_AF_NORM_TX_FIFO_STATUS(void)
  3615. {
  3616. return 0x648;
  3617. }
  3618. /**
  3619. * Register (RVU_PF_BAR0) nix#_af_pq#_dbg_arb_link_exp
  3620. *
  3621. * INTERNAL: NIX AF PQ Arb Link EXPRESS Debug Register
  3622. */
  3623. union nixx_af_pqx_dbg_arb_link_exp {
  3624. u64 u;
  3625. struct nixx_af_pqx_dbg_arb_link_exp_s {
  3626. u64 req : 1;
  3627. u64 act_c_con : 1;
  3628. u64 cnt : 2;
  3629. u64 reserved_4_5 : 2;
  3630. u64 rr_mask : 1;
  3631. u64 reserved_7_63 : 57;
  3632. } s;
  3633. /* struct nixx_af_pqx_dbg_arb_link_exp_s cn; */
  3634. };
  3635. static inline u64 NIXX_AF_PQX_DBG_ARB_LINK_EXP(u64 a)
  3636. __attribute__ ((pure, always_inline));
  3637. static inline u64 NIXX_AF_PQX_DBG_ARB_LINK_EXP(u64 a)
  3638. {
  3639. return 0xce8 + 0x10000 * a;
  3640. }
  3641. /**
  3642. * Register (RVU_PF_BAR0) nix#_af_pq#_dbg_arb_link_nrm
  3643. *
  3644. * INTERNAL: NIX AF PQ Arb Link NORMAL Debug Register
  3645. */
  3646. union nixx_af_pqx_dbg_arb_link_nrm {
  3647. u64 u;
  3648. struct nixx_af_pqx_dbg_arb_link_nrm_s {
  3649. u64 req : 1;
  3650. u64 act_c_con : 1;
  3651. u64 cnt : 2;
  3652. u64 reserved_4_5 : 2;
  3653. u64 rr_mask : 1;
  3654. u64 reserved_7_63 : 57;
  3655. } s;
  3656. /* struct nixx_af_pqx_dbg_arb_link_nrm_s cn; */
  3657. };
  3658. static inline u64 NIXX_AF_PQX_DBG_ARB_LINK_NRM(u64 a)
  3659. __attribute__ ((pure, always_inline));
  3660. static inline u64 NIXX_AF_PQX_DBG_ARB_LINK_NRM(u64 a)
  3661. {
  3662. return 0xce0 + 0x10000 * a;
  3663. }
  3664. /**
  3665. * Register (RVU_PF_BAR0) nix#_af_pq#_dbg_arb_link_sdp
  3666. *
  3667. * INTERNAL: NIX AF PQ Arb Link SDP Debug Register
  3668. */
  3669. union nixx_af_pqx_dbg_arb_link_sdp {
  3670. u64 u;
  3671. struct nixx_af_pqx_dbg_arb_link_sdp_s {
  3672. u64 req : 1;
  3673. u64 act_c_con : 1;
  3674. u64 cnt : 2;
  3675. u64 reserved_4_5 : 2;
  3676. u64 rr_mask : 1;
  3677. u64 reserved_7_63 : 57;
  3678. } s;
  3679. /* struct nixx_af_pqx_dbg_arb_link_sdp_s cn; */
  3680. };
  3681. static inline u64 NIXX_AF_PQX_DBG_ARB_LINK_SDP(u64 a)
  3682. __attribute__ ((pure, always_inline));
  3683. static inline u64 NIXX_AF_PQX_DBG_ARB_LINK_SDP(u64 a)
  3684. {
  3685. return 0xcf0 + 0x10000 * a;
  3686. }
  3687. /**
  3688. * Register (RVU_PF_BAR0) nix#_af_pq_arb_crd_rdy_debug
  3689. *
  3690. * INTERNAL: NIX AF PQ_ARB Node Credit Ready Registers NIX AF PQ ARB
  3691. * Credit ready register
  3692. */
  3693. union nixx_af_pq_arb_crd_rdy_debug {
  3694. u64 u;
  3695. struct nixx_af_pq_arb_crd_rdy_debug_s {
  3696. u64 node_crd_rdy : 28;
  3697. u64 reserved_28_63 : 36;
  3698. } s;
  3699. /* struct nixx_af_pq_arb_crd_rdy_debug_s cn; */
  3700. };
  3701. static inline u64 NIXX_AF_PQ_ARB_CRD_RDY_DEBUG(void)
  3702. __attribute__ ((pure, always_inline));
  3703. static inline u64 NIXX_AF_PQ_ARB_CRD_RDY_DEBUG(void)
  3704. {
  3705. return 0xf10;
  3706. }
  3707. /**
  3708. * Register (RVU_PF_BAR0) nix#_af_pq_arb_dwrr_msk_debug
  3709. *
  3710. * INTERNAL: NIX AF PQ_ARB DWRR mask set read only debug Registers
  3711. */
  3712. union nixx_af_pq_arb_dwrr_msk_debug {
  3713. u64 u;
  3714. struct nixx_af_pq_arb_dwrr_msk_debug_s {
  3715. u64 node_dwrr_mask_set : 28;
  3716. u64 reserved_28_63 : 36;
  3717. } s;
  3718. /* struct nixx_af_pq_arb_dwrr_msk_debug_s cn; */
  3719. };
  3720. static inline u64 NIXX_AF_PQ_ARB_DWRR_MSK_DEBUG(void)
  3721. __attribute__ ((pure, always_inline));
  3722. static inline u64 NIXX_AF_PQ_ARB_DWRR_MSK_DEBUG(void)
  3723. {
  3724. return 0xf30;
  3725. }
  3726. /**
  3727. * Register (RVU_PF_BAR0) nix#_af_pq_arb_node_gnt_debug
  3728. *
  3729. * INTERNAL: NIX AF PQ_ARB Node Grant vector Registers
  3730. */
  3731. union nixx_af_pq_arb_node_gnt_debug {
  3732. u64 u;
  3733. struct nixx_af_pq_arb_node_gnt_debug_s {
  3734. u64 node_grant_vec : 28;
  3735. u64 reserved_28_63 : 36;
  3736. } s;
  3737. /* struct nixx_af_pq_arb_node_gnt_debug_s cn; */
  3738. };
  3739. static inline u64 NIXX_AF_PQ_ARB_NODE_GNT_DEBUG(void)
  3740. __attribute__ ((pure, always_inline));
  3741. static inline u64 NIXX_AF_PQ_ARB_NODE_GNT_DEBUG(void)
  3742. {
  3743. return 0xf20;
  3744. }
  3745. /**
  3746. * Register (RVU_PF_BAR0) nix#_af_pq_arb_node_req_debug
  3747. *
  3748. * INTERNAL: NIX AF PQ_ARB Node Request Debug Registers NIX AF PQ ARB
  3749. * Node Request Debug register
  3750. */
  3751. union nixx_af_pq_arb_node_req_debug {
  3752. u64 u;
  3753. struct nixx_af_pq_arb_node_req_debug_s {
  3754. u64 node_req : 28;
  3755. u64 reserved_28_63 : 36;
  3756. } s;
  3757. /* struct nixx_af_pq_arb_node_req_debug_s cn; */
  3758. };
  3759. static inline u64 NIXX_AF_PQ_ARB_NODE_REQ_DEBUG(void)
  3760. __attribute__ ((pure, always_inline));
  3761. static inline u64 NIXX_AF_PQ_ARB_NODE_REQ_DEBUG(void)
  3762. {
  3763. return 0xf00;
  3764. }
  3765. /**
  3766. * Register (RVU_PF_BAR0) nix#_af_pq_arb_shape_vld_dbg
  3767. *
  3768. * INTERNAL: NIX AF PQ_ARB shape valid set Register
  3769. */
  3770. union nixx_af_pq_arb_shape_vld_dbg {
  3771. u64 u;
  3772. struct nixx_af_pq_arb_shape_vld_dbg_s {
  3773. u64 node_shape_vld_set : 28;
  3774. u64 reserved_28_63 : 36;
  3775. } s;
  3776. /* struct nixx_af_pq_arb_shape_vld_dbg_s cn; */
  3777. };
  3778. static inline u64 NIXX_AF_PQ_ARB_SHAPE_VLD_DBG(void)
  3779. __attribute__ ((pure, always_inline));
  3780. static inline u64 NIXX_AF_PQ_ARB_SHAPE_VLD_DBG(void)
  3781. {
  3782. return 0xf40;
  3783. }
  3784. /**
  3785. * Register (RVU_PF_BAR0) nix#_af_pq_dbg_arb_0
  3786. *
  3787. * INTERNAL: NIX AF PQ Arb Debug 0 Register
  3788. */
  3789. union nixx_af_pq_dbg_arb_0 {
  3790. u64 u;
  3791. struct nixx_af_pq_dbg_arb_0_s {
  3792. u64 rr_mask_clr : 1;
  3793. u64 reserved_1_63 : 63;
  3794. } s;
  3795. /* struct nixx_af_pq_dbg_arb_0_s cn; */
  3796. };
  3797. static inline u64 NIXX_AF_PQ_DBG_ARB_0(void)
  3798. __attribute__ ((pure, always_inline));
  3799. static inline u64 NIXX_AF_PQ_DBG_ARB_0(void)
  3800. {
  3801. return 0xcf8;
  3802. }
  3803. /**
  3804. * Register (RVU_PF_BAR0) nix#_af_pq_lnk_#_dwrr_msk_dbg
  3805. *
  3806. * INTERNAL: NIX AF PQ_ARB Physical Link DWRR MASK Registers
  3807. */
  3808. union nixx_af_pq_lnk_x_dwrr_msk_dbg {
  3809. u64 u;
  3810. struct nixx_af_pq_lnk_x_dwrr_msk_dbg_s {
  3811. u64 link_dwrr_mask_set : 28;
  3812. u64 reserved_28_63 : 36;
  3813. } s;
  3814. /* struct nixx_af_pq_lnk_x_dwrr_msk_dbg_s cn; */
  3815. };
  3816. static inline u64 NIXX_AF_PQ_LNK_X_DWRR_MSK_DBG(u64 a)
  3817. __attribute__ ((pure, always_inline));
  3818. static inline u64 NIXX_AF_PQ_LNK_X_DWRR_MSK_DBG(u64 a)
  3819. {
  3820. return 0x1100 + 0x10000 * a;
  3821. }
  3822. /**
  3823. * Register (RVU_PF_BAR0) nix#_af_pse_400_rate_divider
  3824. *
  3825. * INTERNAL: NIX AF PSE 400 Rate Divider Register
  3826. */
  3827. union nixx_af_pse_400_rate_divider {
  3828. u64 u;
  3829. struct nixx_af_pse_400_rate_divider_s {
  3830. u64 rate_div_cfg : 9;
  3831. u64 reserved_9_63 : 55;
  3832. } s;
  3833. /* struct nixx_af_pse_400_rate_divider_s cn; */
  3834. };
  3835. static inline u64 NIXX_AF_PSE_400_RATE_DIVIDER(void)
  3836. __attribute__ ((pure, always_inline));
  3837. static inline u64 NIXX_AF_PSE_400_RATE_DIVIDER(void)
  3838. {
  3839. return 0x830;
  3840. }
  3841. /**
  3842. * Register (RVU_PF_BAR0) nix#_af_pse_active_cycles_pc
  3843. *
  3844. * NIX AF Active Cycles Register These registers are indexed by the
  3845. * conditional clock domain number.
  3846. */
  3847. union nixx_af_pse_active_cycles_pc {
  3848. u64 u;
  3849. struct nixx_af_pse_active_cycles_pc_s {
  3850. u64 act_cyc : 64;
  3851. } s;
  3852. /* struct nixx_af_pse_active_cycles_pc_s cn; */
  3853. };
  3854. static inline u64 NIXX_AF_PSE_ACTIVE_CYCLES_PC(void)
  3855. __attribute__ ((pure, always_inline));
  3856. static inline u64 NIXX_AF_PSE_ACTIVE_CYCLES_PC(void)
  3857. {
  3858. return 0x8c0;
  3859. }
  3860. /**
  3861. * Register (RVU_PF_BAR0) nix#_af_pse_bp_test0
  3862. *
  3863. * INTERNAL: NIX AF PSE Backpressure Test 0 Register
  3864. */
  3865. union nixx_af_pse_bp_test0 {
  3866. u64 u;
  3867. struct nixx_af_pse_bp_test0_s {
  3868. u64 lfsr_freq : 12;
  3869. u64 reserved_12_63 : 52;
  3870. } s;
  3871. struct nixx_af_pse_bp_test0_cn96xxp1 {
  3872. u64 lfsr_freq : 12;
  3873. u64 reserved_12_15 : 4;
  3874. u64 bp_cfg : 8;
  3875. u64 reserved_24_59 : 36;
  3876. u64 enable : 4;
  3877. } cn96xxp1;
  3878. struct nixx_af_pse_bp_test0_cn96xxp3 {
  3879. u64 lfsr_freq : 12;
  3880. u64 reserved_12_15 : 4;
  3881. u64 reserved_16_19 : 4;
  3882. u64 bp_cfg : 12;
  3883. u64 reserved_32_55 : 24;
  3884. u64 reserved_56_57 : 2;
  3885. u64 enable : 6;
  3886. } cn96xxp3;
  3887. /* struct nixx_af_pse_bp_test0_cn96xxp1 cnf95xxp1; */
  3888. struct nixx_af_pse_bp_test0_cnf95xxp2 {
  3889. u64 lfsr_freq : 12;
  3890. u64 reserved_12_15 : 4;
  3891. u64 bp_cfg : 8;
  3892. u64 reserved_24_31 : 8;
  3893. u64 reserved_32_55 : 24;
  3894. u64 reserved_56_59 : 4;
  3895. u64 enable : 4;
  3896. } cnf95xxp2;
  3897. };
  3898. static inline u64 NIXX_AF_PSE_BP_TEST0(void)
  3899. __attribute__ ((pure, always_inline));
  3900. static inline u64 NIXX_AF_PSE_BP_TEST0(void)
  3901. {
  3902. return 0x840;
  3903. }
  3904. /**
  3905. * Register (RVU_PF_BAR0) nix#_af_pse_bp_test1
  3906. *
  3907. * INTERNAL: NIX AF PSE Backpressure Test 1 Register
  3908. */
  3909. union nixx_af_pse_bp_test1 {
  3910. u64 u;
  3911. struct nixx_af_pse_bp_test1_s {
  3912. u64 lfsr_freq : 12;
  3913. u64 reserved_12_15 : 4;
  3914. u64 bp_cfg : 10;
  3915. u64 reserved_26_63 : 38;
  3916. } s;
  3917. struct nixx_af_pse_bp_test1_cn96xxp1 {
  3918. u64 lfsr_freq : 12;
  3919. u64 reserved_12_15 : 4;
  3920. u64 bp_cfg : 8;
  3921. u64 reserved_24_59 : 36;
  3922. u64 enable : 4;
  3923. } cn96xxp1;
  3924. struct nixx_af_pse_bp_test1_cn96xxp3 {
  3925. u64 lfsr_freq : 12;
  3926. u64 reserved_12_15 : 4;
  3927. u64 bp_cfg : 10;
  3928. u64 reserved_26_31 : 6;
  3929. u64 reserved_32_55 : 24;
  3930. u64 reserved_56_58 : 3;
  3931. u64 enable : 5;
  3932. } cn96xxp3;
  3933. /* struct nixx_af_pse_bp_test1_cn96xxp1 cnf95xxp1; */
  3934. struct nixx_af_pse_bp_test1_cnf95xxp2 {
  3935. u64 lfsr_freq : 12;
  3936. u64 reserved_12_15 : 4;
  3937. u64 bp_cfg : 8;
  3938. u64 reserved_24_31 : 8;
  3939. u64 reserved_32_55 : 24;
  3940. u64 reserved_56_59 : 4;
  3941. u64 enable : 4;
  3942. } cnf95xxp2;
  3943. };
  3944. static inline u64 NIXX_AF_PSE_BP_TEST1(void)
  3945. __attribute__ ((pure, always_inline));
  3946. static inline u64 NIXX_AF_PSE_BP_TEST1(void)
  3947. {
  3948. return 0x850;
  3949. }
  3950. /**
  3951. * Register (RVU_PF_BAR0) nix#_af_pse_bp_test2
  3952. *
  3953. * INTERNAL: NIX AF PSE Backpressure Test 2 Register
  3954. */
  3955. union nixx_af_pse_bp_test2 {
  3956. u64 u;
  3957. struct nixx_af_pse_bp_test2_s {
  3958. u64 lfsr_freq : 12;
  3959. u64 reserved_12_15 : 4;
  3960. u64 bp_cfg : 10;
  3961. u64 reserved_26_63 : 38;
  3962. } s;
  3963. struct nixx_af_pse_bp_test2_cn96xxp1 {
  3964. u64 lfsr_freq : 12;
  3965. u64 reserved_12_15 : 4;
  3966. u64 bp_cfg : 8;
  3967. u64 reserved_24_59 : 36;
  3968. u64 enable : 4;
  3969. } cn96xxp1;
  3970. struct nixx_af_pse_bp_test2_cn96xxp3 {
  3971. u64 lfsr_freq : 12;
  3972. u64 reserved_12_15 : 4;
  3973. u64 bp_cfg : 10;
  3974. u64 reserved_26_31 : 6;
  3975. u64 reserved_32_55 : 24;
  3976. u64 reserved_56_58 : 3;
  3977. u64 enable : 5;
  3978. } cn96xxp3;
  3979. /* struct nixx_af_pse_bp_test2_cn96xxp1 cnf95xxp1; */
  3980. struct nixx_af_pse_bp_test2_cnf95xxp2 {
  3981. u64 lfsr_freq : 12;
  3982. u64 reserved_12_15 : 4;
  3983. u64 bp_cfg : 8;
  3984. u64 reserved_24_31 : 8;
  3985. u64 reserved_32_55 : 24;
  3986. u64 reserved_56_59 : 4;
  3987. u64 enable : 4;
  3988. } cnf95xxp2;
  3989. };
  3990. static inline u64 NIXX_AF_PSE_BP_TEST2(void)
  3991. __attribute__ ((pure, always_inline));
  3992. static inline u64 NIXX_AF_PSE_BP_TEST2(void)
  3993. {
  3994. return 0x860;
  3995. }
  3996. /**
  3997. * Register (RVU_PF_BAR0) nix#_af_pse_bp_test3
  3998. *
  3999. * INTERNAL: NIX AF PSE Backpressure Test 3 Register
  4000. */
  4001. union nixx_af_pse_bp_test3 {
  4002. u64 u;
  4003. struct nixx_af_pse_bp_test3_s {
  4004. u64 lfsr_freq : 12;
  4005. u64 reserved_12_15 : 4;
  4006. u64 bp_cfg : 10;
  4007. u64 reserved_26_63 : 38;
  4008. } s;
  4009. struct nixx_af_pse_bp_test3_cn96xxp1 {
  4010. u64 lfsr_freq : 12;
  4011. u64 reserved_12_15 : 4;
  4012. u64 bp_cfg : 8;
  4013. u64 reserved_24_59 : 36;
  4014. u64 enable : 4;
  4015. } cn96xxp1;
  4016. struct nixx_af_pse_bp_test3_cn96xxp3 {
  4017. u64 lfsr_freq : 12;
  4018. u64 reserved_12_15 : 4;
  4019. u64 bp_cfg : 10;
  4020. u64 reserved_26_31 : 6;
  4021. u64 reserved_32_55 : 24;
  4022. u64 reserved_56_58 : 3;
  4023. u64 enable : 5;
  4024. } cn96xxp3;
  4025. /* struct nixx_af_pse_bp_test3_cn96xxp1 cnf95xxp1; */
  4026. struct nixx_af_pse_bp_test3_cnf95xxp2 {
  4027. u64 lfsr_freq : 12;
  4028. u64 reserved_12_15 : 4;
  4029. u64 bp_cfg : 8;
  4030. u64 reserved_24_31 : 8;
  4031. u64 reserved_32_55 : 24;
  4032. u64 reserved_56_59 : 4;
  4033. u64 enable : 4;
  4034. } cnf95xxp2;
  4035. };
  4036. static inline u64 NIXX_AF_PSE_BP_TEST3(void)
  4037. __attribute__ ((pure, always_inline));
  4038. static inline u64 NIXX_AF_PSE_BP_TEST3(void)
  4039. {
  4040. return 0x870;
  4041. }
  4042. /**
  4043. * Register (RVU_PF_BAR0) nix#_af_pse_channel_level
  4044. *
  4045. * NIX AF PSE Channel Level Register
  4046. */
  4047. union nixx_af_pse_channel_level {
  4048. u64 u;
  4049. struct nixx_af_pse_channel_level_s {
  4050. u64 bp_level : 1;
  4051. u64 reserved_1_63 : 63;
  4052. } s;
  4053. /* struct nixx_af_pse_channel_level_s cn; */
  4054. };
  4055. static inline u64 NIXX_AF_PSE_CHANNEL_LEVEL(void)
  4056. __attribute__ ((pure, always_inline));
  4057. static inline u64 NIXX_AF_PSE_CHANNEL_LEVEL(void)
  4058. {
  4059. return 0x800;
  4060. }
  4061. /**
  4062. * Register (RVU_PF_BAR0) nix#_af_pse_const
  4063. *
  4064. * NIX AF PSE Constants Register This register contains constants for
  4065. * software discovery.
  4066. */
  4067. union nixx_af_pse_const {
  4068. u64 u;
  4069. struct nixx_af_pse_const_s {
  4070. u64 levels : 4;
  4071. u64 reserved_4_7 : 4;
  4072. u64 mark_formats : 8;
  4073. u64 reserved_16_63 : 48;
  4074. } s;
  4075. /* struct nixx_af_pse_const_s cn; */
  4076. };
  4077. static inline u64 NIXX_AF_PSE_CONST(void)
  4078. __attribute__ ((pure, always_inline));
  4079. static inline u64 NIXX_AF_PSE_CONST(void)
  4080. {
  4081. return 0x60;
  4082. }
  4083. /**
  4084. * Register (RVU_PF_BAR0) nix#_af_pse_eco
  4085. *
  4086. * INTERNAL: AF PSE ECO Register
  4087. */
  4088. union nixx_af_pse_eco {
  4089. u64 u;
  4090. struct nixx_af_pse_eco_s {
  4091. u64 eco_rw : 64;
  4092. } s;
  4093. /* struct nixx_af_pse_eco_s cn; */
  4094. };
  4095. static inline u64 NIXX_AF_PSE_ECO(void)
  4096. __attribute__ ((pure, always_inline));
  4097. static inline u64 NIXX_AF_PSE_ECO(void)
  4098. {
  4099. return 0x5d0;
  4100. }
  4101. /**
  4102. * Register (RVU_PF_BAR0) nix#_af_pse_expr_bp_test
  4103. *
  4104. * INTERNAL: NIX AF PSE Express Backpressure Test Register Internal:
  4105. * 802.3br frame preemption/express path is defeatured.
  4106. */
  4107. union nixx_af_pse_expr_bp_test {
  4108. u64 u;
  4109. struct nixx_af_pse_expr_bp_test_s {
  4110. u64 lfsr_freq : 12;
  4111. u64 reserved_12_15 : 4;
  4112. u64 bp_cfg : 32;
  4113. u64 enable : 16;
  4114. } s;
  4115. /* struct nixx_af_pse_expr_bp_test_s cn; */
  4116. };
  4117. static inline u64 NIXX_AF_PSE_EXPR_BP_TEST(void)
  4118. __attribute__ ((pure, always_inline));
  4119. static inline u64 NIXX_AF_PSE_EXPR_BP_TEST(void)
  4120. {
  4121. return 0x890;
  4122. }
  4123. /**
  4124. * Register (RVU_PF_BAR0) nix#_af_pse_norm_bp_test
  4125. *
  4126. * INTERNAL: NIX AF PSE Normal Backpressure Test Register
  4127. */
  4128. union nixx_af_pse_norm_bp_test {
  4129. u64 u;
  4130. struct nixx_af_pse_norm_bp_test_s {
  4131. u64 lfsr_freq : 12;
  4132. u64 reserved_12_15 : 4;
  4133. u64 bp_cfg : 32;
  4134. u64 reserved_48_63 : 16;
  4135. } s;
  4136. struct nixx_af_pse_norm_bp_test_cn96xxp1 {
  4137. u64 lfsr_freq : 12;
  4138. u64 reserved_12_15 : 4;
  4139. u64 bp_cfg : 32;
  4140. u64 enable : 16;
  4141. } cn96xxp1;
  4142. struct nixx_af_pse_norm_bp_test_cn96xxp3 {
  4143. u64 lfsr_freq : 12;
  4144. u64 reserved_12_15 : 4;
  4145. u64 bp_cfg : 12;
  4146. u64 reserved_28_57 : 30;
  4147. u64 enable : 6;
  4148. } cn96xxp3;
  4149. /* struct nixx_af_pse_norm_bp_test_cn96xxp1 cnf95xx; */
  4150. };
  4151. static inline u64 NIXX_AF_PSE_NORM_BP_TEST(void)
  4152. __attribute__ ((pure, always_inline));
  4153. static inline u64 NIXX_AF_PSE_NORM_BP_TEST(void)
  4154. {
  4155. return 0x880;
  4156. }
  4157. /**
  4158. * Register (RVU_PF_BAR0) nix#_af_pse_shaper_cfg
  4159. *
  4160. * NIX AF PSE Shaper Configuration Register
  4161. */
  4162. union nixx_af_pse_shaper_cfg {
  4163. u64 u;
  4164. struct nixx_af_pse_shaper_cfg_s {
  4165. u64 red_send_as_yellow : 1;
  4166. u64 color_aware : 1;
  4167. u64 reserved_2_63 : 62;
  4168. } s;
  4169. /* struct nixx_af_pse_shaper_cfg_s cn; */
  4170. };
  4171. static inline u64 NIXX_AF_PSE_SHAPER_CFG(void)
  4172. __attribute__ ((pure, always_inline));
  4173. static inline u64 NIXX_AF_PSE_SHAPER_CFG(void)
  4174. {
  4175. return 0x810;
  4176. }
  4177. /**
  4178. * Register (RVU_PF_BAR0) nix#_af_ras
  4179. *
  4180. * NIX AF RAS Interrupt Register This register is intended for delivery
  4181. * of RAS events to the SCP, so should be ignored by OS drivers.
  4182. */
  4183. union nixx_af_ras {
  4184. u64 u;
  4185. struct nixx_af_ras_s {
  4186. u64 rx_mce_poison : 1;
  4187. u64 rx_mcast_wqe_poison : 1;
  4188. u64 rx_mirror_wqe_poison : 1;
  4189. u64 rx_mcast_data_poison : 1;
  4190. u64 rx_mirror_data_poison : 1;
  4191. u64 reserved_5_31 : 27;
  4192. u64 aq_ctx_poison : 1;
  4193. u64 aq_res_poison : 1;
  4194. u64 aq_inst_poison : 1;
  4195. u64 reserved_35_63 : 29;
  4196. } s;
  4197. /* struct nixx_af_ras_s cn; */
  4198. };
  4199. static inline u64 NIXX_AF_RAS(void)
  4200. __attribute__ ((pure, always_inline));
  4201. static inline u64 NIXX_AF_RAS(void)
  4202. {
  4203. return 0x1a0;
  4204. }
  4205. /**
  4206. * Register (RVU_PF_BAR0) nix#_af_ras_ena_w1c
  4207. *
  4208. * NIX AF RAS Interrupt Enable Clear Register This register clears
  4209. * interrupt enable bits.
  4210. */
  4211. union nixx_af_ras_ena_w1c {
  4212. u64 u;
  4213. struct nixx_af_ras_ena_w1c_s {
  4214. u64 rx_mce_poison : 1;
  4215. u64 rx_mcast_wqe_poison : 1;
  4216. u64 rx_mirror_wqe_poison : 1;
  4217. u64 rx_mcast_data_poison : 1;
  4218. u64 rx_mirror_data_poison : 1;
  4219. u64 reserved_5_31 : 27;
  4220. u64 aq_ctx_poison : 1;
  4221. u64 aq_res_poison : 1;
  4222. u64 aq_inst_poison : 1;
  4223. u64 reserved_35_63 : 29;
  4224. } s;
  4225. /* struct nixx_af_ras_ena_w1c_s cn; */
  4226. };
  4227. static inline u64 NIXX_AF_RAS_ENA_W1C(void)
  4228. __attribute__ ((pure, always_inline));
  4229. static inline u64 NIXX_AF_RAS_ENA_W1C(void)
  4230. {
  4231. return 0x1b8;
  4232. }
  4233. /**
  4234. * Register (RVU_PF_BAR0) nix#_af_ras_ena_w1s
  4235. *
  4236. * NIX AF RAS Interrupt Enable Set Register This register sets interrupt
  4237. * enable bits.
  4238. */
  4239. union nixx_af_ras_ena_w1s {
  4240. u64 u;
  4241. struct nixx_af_ras_ena_w1s_s {
  4242. u64 rx_mce_poison : 1;
  4243. u64 rx_mcast_wqe_poison : 1;
  4244. u64 rx_mirror_wqe_poison : 1;
  4245. u64 rx_mcast_data_poison : 1;
  4246. u64 rx_mirror_data_poison : 1;
  4247. u64 reserved_5_31 : 27;
  4248. u64 aq_ctx_poison : 1;
  4249. u64 aq_res_poison : 1;
  4250. u64 aq_inst_poison : 1;
  4251. u64 reserved_35_63 : 29;
  4252. } s;
  4253. /* struct nixx_af_ras_ena_w1s_s cn; */
  4254. };
  4255. static inline u64 NIXX_AF_RAS_ENA_W1S(void)
  4256. __attribute__ ((pure, always_inline));
  4257. static inline u64 NIXX_AF_RAS_ENA_W1S(void)
  4258. {
  4259. return 0x1b0;
  4260. }
  4261. /**
  4262. * Register (RVU_PF_BAR0) nix#_af_ras_w1s
  4263. *
  4264. * NIX AF RAS Interrupt Set Register This register sets interrupt bits.
  4265. */
  4266. union nixx_af_ras_w1s {
  4267. u64 u;
  4268. struct nixx_af_ras_w1s_s {
  4269. u64 rx_mce_poison : 1;
  4270. u64 rx_mcast_wqe_poison : 1;
  4271. u64 rx_mirror_wqe_poison : 1;
  4272. u64 rx_mcast_data_poison : 1;
  4273. u64 rx_mirror_data_poison : 1;
  4274. u64 reserved_5_31 : 27;
  4275. u64 aq_ctx_poison : 1;
  4276. u64 aq_res_poison : 1;
  4277. u64 aq_inst_poison : 1;
  4278. u64 reserved_35_63 : 29;
  4279. } s;
  4280. /* struct nixx_af_ras_w1s_s cn; */
  4281. };
  4282. static inline u64 NIXX_AF_RAS_W1S(void)
  4283. __attribute__ ((pure, always_inline));
  4284. static inline u64 NIXX_AF_RAS_W1S(void)
  4285. {
  4286. return 0x1a8;
  4287. }
  4288. /**
  4289. * Register (RVU_PF_BAR0) nix#_af_reb_bp_test#
  4290. *
  4291. * INTERNAL: NIX AF REB Backpressure Test Registers
  4292. */
  4293. union nixx_af_reb_bp_testx {
  4294. u64 u;
  4295. struct nixx_af_reb_bp_testx_s {
  4296. u64 lfsr_freq : 12;
  4297. u64 reserved_12_15 : 4;
  4298. u64 bp_cfg : 8;
  4299. u64 reserved_24_47 : 24;
  4300. u64 enable : 4;
  4301. u64 reserved_52_63 : 12;
  4302. } s;
  4303. /* struct nixx_af_reb_bp_testx_s cn; */
  4304. };
  4305. static inline u64 NIXX_AF_REB_BP_TESTX(u64 a)
  4306. __attribute__ ((pure, always_inline));
  4307. static inline u64 NIXX_AF_REB_BP_TESTX(u64 a)
  4308. {
  4309. return 0x4840 + 0x10000 * a;
  4310. }
  4311. /**
  4312. * Register (RVU_PF_BAR0) nix#_af_rq_const
  4313. *
  4314. * NIX AF RQ Constants Register This register contains constants for
  4315. * software discovery.
  4316. */
  4317. union nixx_af_rq_const {
  4318. u64 u;
  4319. struct nixx_af_rq_const_s {
  4320. u64 queues_per_lf : 24;
  4321. u64 reserved_24_63 : 40;
  4322. } s;
  4323. /* struct nixx_af_rq_const_s cn; */
  4324. };
  4325. static inline u64 NIXX_AF_RQ_CONST(void)
  4326. __attribute__ ((pure, always_inline));
  4327. static inline u64 NIXX_AF_RQ_CONST(void)
  4328. {
  4329. return 0x50;
  4330. }
  4331. /**
  4332. * Register (RVU_PF_BAR0) nix#_af_rqm_bp_test
  4333. *
  4334. * INTERNAL: NIX AF REB Backpressure Test Registers
  4335. */
  4336. union nixx_af_rqm_bp_test {
  4337. u64 u;
  4338. struct nixx_af_rqm_bp_test_s {
  4339. u64 lfsr_freq : 12;
  4340. u64 reserved_12_15 : 4;
  4341. u64 bp_cfg : 16;
  4342. u64 reserved_32_47 : 16;
  4343. u64 enable : 8;
  4344. u64 reserved_56_63 : 8;
  4345. } s;
  4346. /* struct nixx_af_rqm_bp_test_s cn; */
  4347. };
  4348. static inline u64 NIXX_AF_RQM_BP_TEST(void)
  4349. __attribute__ ((pure, always_inline));
  4350. static inline u64 NIXX_AF_RQM_BP_TEST(void)
  4351. {
  4352. return 0x4880;
  4353. }
  4354. /**
  4355. * Register (RVU_PF_BAR0) nix#_af_rqm_eco
  4356. *
  4357. * INTERNAL: AF RQM ECO Register
  4358. */
  4359. union nixx_af_rqm_eco {
  4360. u64 u;
  4361. struct nixx_af_rqm_eco_s {
  4362. u64 eco_rw : 64;
  4363. } s;
  4364. /* struct nixx_af_rqm_eco_s cn; */
  4365. };
  4366. static inline u64 NIXX_AF_RQM_ECO(void)
  4367. __attribute__ ((pure, always_inline));
  4368. static inline u64 NIXX_AF_RQM_ECO(void)
  4369. {
  4370. return 0x5a0;
  4371. }
  4372. /**
  4373. * Register (RVU_PF_BAR0) nix#_af_rvu_int
  4374. *
  4375. * NIX AF RVU Interrupt Register This register contains RVU error
  4376. * interrupt summary bits.
  4377. */
  4378. union nixx_af_rvu_int {
  4379. u64 u;
  4380. struct nixx_af_rvu_int_s {
  4381. u64 unmapped_slot : 1;
  4382. u64 reserved_1_63 : 63;
  4383. } s;
  4384. /* struct nixx_af_rvu_int_s cn; */
  4385. };
  4386. static inline u64 NIXX_AF_RVU_INT(void)
  4387. __attribute__ ((pure, always_inline));
  4388. static inline u64 NIXX_AF_RVU_INT(void)
  4389. {
  4390. return 0x1c0;
  4391. }
  4392. /**
  4393. * Register (RVU_PF_BAR0) nix#_af_rvu_int_ena_w1c
  4394. *
  4395. * NIX AF RVU Interrupt Enable Clear Register This register clears
  4396. * interrupt enable bits.
  4397. */
  4398. union nixx_af_rvu_int_ena_w1c {
  4399. u64 u;
  4400. struct nixx_af_rvu_int_ena_w1c_s {
  4401. u64 unmapped_slot : 1;
  4402. u64 reserved_1_63 : 63;
  4403. } s;
  4404. /* struct nixx_af_rvu_int_ena_w1c_s cn; */
  4405. };
  4406. static inline u64 NIXX_AF_RVU_INT_ENA_W1C(void)
  4407. __attribute__ ((pure, always_inline));
  4408. static inline u64 NIXX_AF_RVU_INT_ENA_W1C(void)
  4409. {
  4410. return 0x1d8;
  4411. }
  4412. /**
  4413. * Register (RVU_PF_BAR0) nix#_af_rvu_int_ena_w1s
  4414. *
  4415. * NIX AF RVU Interrupt Enable Set Register This register sets interrupt
  4416. * enable bits.
  4417. */
  4418. union nixx_af_rvu_int_ena_w1s {
  4419. u64 u;
  4420. struct nixx_af_rvu_int_ena_w1s_s {
  4421. u64 unmapped_slot : 1;
  4422. u64 reserved_1_63 : 63;
  4423. } s;
  4424. /* struct nixx_af_rvu_int_ena_w1s_s cn; */
  4425. };
  4426. static inline u64 NIXX_AF_RVU_INT_ENA_W1S(void)
  4427. __attribute__ ((pure, always_inline));
  4428. static inline u64 NIXX_AF_RVU_INT_ENA_W1S(void)
  4429. {
  4430. return 0x1d0;
  4431. }
  4432. /**
  4433. * Register (RVU_PF_BAR0) nix#_af_rvu_int_w1s
  4434. *
  4435. * NIX AF RVU Interrupt Set Register This register sets interrupt bits.
  4436. */
  4437. union nixx_af_rvu_int_w1s {
  4438. u64 u;
  4439. struct nixx_af_rvu_int_w1s_s {
  4440. u64 unmapped_slot : 1;
  4441. u64 reserved_1_63 : 63;
  4442. } s;
  4443. /* struct nixx_af_rvu_int_w1s_s cn; */
  4444. };
  4445. static inline u64 NIXX_AF_RVU_INT_W1S(void)
  4446. __attribute__ ((pure, always_inline));
  4447. static inline u64 NIXX_AF_RVU_INT_W1S(void)
  4448. {
  4449. return 0x1c8;
  4450. }
  4451. /**
  4452. * Register (RVU_PF_BAR0) nix#_af_rvu_lf_cfg_debug
  4453. *
  4454. * NIX Privileged LF Configuration Debug Register This debug register
  4455. * allows software to lookup the reverse mapping from VF/PF slot to LF.
  4456. * The forward mapping is programmed with NIX_PRIV_LF()_CFG.
  4457. */
  4458. union nixx_af_rvu_lf_cfg_debug {
  4459. u64 u;
  4460. struct nixx_af_rvu_lf_cfg_debug_s {
  4461. u64 lf : 12;
  4462. u64 lf_valid : 1;
  4463. u64 exec : 1;
  4464. u64 reserved_14_15 : 2;
  4465. u64 slot : 8;
  4466. u64 pf_func : 16;
  4467. u64 reserved_40_63 : 24;
  4468. } s;
  4469. /* struct nixx_af_rvu_lf_cfg_debug_s cn; */
  4470. };
  4471. static inline u64 NIXX_AF_RVU_LF_CFG_DEBUG(void)
  4472. __attribute__ ((pure, always_inline));
  4473. static inline u64 NIXX_AF_RVU_LF_CFG_DEBUG(void)
  4474. {
  4475. return 0x8000030;
  4476. }
  4477. /**
  4478. * Register (RVU_PF_BAR0) nix#_af_rx_active_cycles_pc#
  4479. *
  4480. * NIX AF Active Cycles Register These registers are indexed by the
  4481. * conditional clock domain number.
  4482. */
  4483. union nixx_af_rx_active_cycles_pcx {
  4484. u64 u;
  4485. struct nixx_af_rx_active_cycles_pcx_s {
  4486. u64 act_cyc : 64;
  4487. } s;
  4488. /* struct nixx_af_rx_active_cycles_pcx_s cn; */
  4489. };
  4490. static inline u64 NIXX_AF_RX_ACTIVE_CYCLES_PCX(u64 a)
  4491. __attribute__ ((pure, always_inline));
  4492. static inline u64 NIXX_AF_RX_ACTIVE_CYCLES_PCX(u64 a)
  4493. {
  4494. return 0x4800 + 0x10000 * a;
  4495. }
  4496. /**
  4497. * Register (RVU_PF_BAR0) nix#_af_rx_bpid#_status
  4498. *
  4499. * NIX AF Receive Backpressure ID Status Registers
  4500. */
  4501. union nixx_af_rx_bpidx_status {
  4502. u64 u;
  4503. struct nixx_af_rx_bpidx_status_s {
  4504. u64 aura_cnt : 32;
  4505. u64 cq_cnt : 32;
  4506. } s;
  4507. /* struct nixx_af_rx_bpidx_status_s cn; */
  4508. };
  4509. static inline u64 NIXX_AF_RX_BPIDX_STATUS(u64 a)
  4510. __attribute__ ((pure, always_inline));
  4511. static inline u64 NIXX_AF_RX_BPIDX_STATUS(u64 a)
  4512. {
  4513. return 0x1a20 + 0x20000 * a;
  4514. }
  4515. /**
  4516. * Register (RVU_PF_BAR0) nix#_af_rx_cfg
  4517. *
  4518. * NIX AF Receive Configuration Register
  4519. */
  4520. union nixx_af_rx_cfg {
  4521. u64 u;
  4522. struct nixx_af_rx_cfg_s {
  4523. u64 cbp_ena : 1;
  4524. u64 reserved_1_63 : 63;
  4525. } s;
  4526. /* struct nixx_af_rx_cfg_s cn; */
  4527. };
  4528. static inline u64 NIXX_AF_RX_CFG(void)
  4529. __attribute__ ((pure, always_inline));
  4530. static inline u64 NIXX_AF_RX_CFG(void)
  4531. {
  4532. return 0xd0;
  4533. }
  4534. /**
  4535. * Register (RVU_PF_BAR0) nix#_af_rx_chan#_cfg
  4536. *
  4537. * NIX AF Receive Channel Configuration Registers
  4538. */
  4539. union nixx_af_rx_chanx_cfg {
  4540. u64 u;
  4541. struct nixx_af_rx_chanx_cfg_s {
  4542. u64 bpid : 9;
  4543. u64 reserved_9_15 : 7;
  4544. u64 bp_ena : 1;
  4545. u64 sw_xoff : 1;
  4546. u64 imp : 1;
  4547. u64 reserved_19_63 : 45;
  4548. } s;
  4549. /* struct nixx_af_rx_chanx_cfg_s cn; */
  4550. };
  4551. static inline u64 NIXX_AF_RX_CHANX_CFG(u64 a)
  4552. __attribute__ ((pure, always_inline));
  4553. static inline u64 NIXX_AF_RX_CHANX_CFG(u64 a)
  4554. {
  4555. return 0x1a30 + 0x8000 * a;
  4556. }
  4557. /**
  4558. * Register (RVU_PF_BAR0) nix#_af_rx_cpt#_credit
  4559. *
  4560. * INTERNAL: NIX AF Receive CPT Credit Register Internal: Not used; no
  4561. * IPSEC fast-path.
  4562. */
  4563. union nixx_af_rx_cptx_credit {
  4564. u64 u;
  4565. struct nixx_af_rx_cptx_credit_s {
  4566. u64 inst_cred_cnt : 22;
  4567. u64 reserved_22_63 : 42;
  4568. } s;
  4569. /* struct nixx_af_rx_cptx_credit_s cn; */
  4570. };
  4571. static inline u64 NIXX_AF_RX_CPTX_CREDIT(u64 a)
  4572. __attribute__ ((pure, always_inline));
  4573. static inline u64 NIXX_AF_RX_CPTX_CREDIT(u64 a)
  4574. {
  4575. return 0x360 + 8 * a;
  4576. }
  4577. /**
  4578. * Register (RVU_PF_BAR0) nix#_af_rx_cpt#_inst_qsel
  4579. *
  4580. * INTERNAL: NIX AF Receive CPT Instruction Queue Select Register
  4581. * Internal: Not used; no IPSEC fast-path.
  4582. */
  4583. union nixx_af_rx_cptx_inst_qsel {
  4584. u64 u;
  4585. struct nixx_af_rx_cptx_inst_qsel_s {
  4586. u64 slot : 8;
  4587. u64 pf_func : 16;
  4588. u64 reserved_24_63 : 40;
  4589. } s;
  4590. /* struct nixx_af_rx_cptx_inst_qsel_s cn; */
  4591. };
  4592. static inline u64 NIXX_AF_RX_CPTX_INST_QSEL(u64 a)
  4593. __attribute__ ((pure, always_inline));
  4594. static inline u64 NIXX_AF_RX_CPTX_INST_QSEL(u64 a)
  4595. {
  4596. return 0x320 + 8 * a;
  4597. }
  4598. /**
  4599. * Register (RVU_PF_BAR0) nix#_af_rx_def_iip4
  4600. *
  4601. * NIX AF Receive Inner IPv4 Header Definition Register Defines layer
  4602. * information in NPC_RESULT_S to identify an inner IPv4 header.
  4603. * Typically the same as NPC_AF_PCK_DEF_IIP4.
  4604. */
  4605. union nixx_af_rx_def_iip4 {
  4606. u64 u;
  4607. struct nixx_af_rx_def_iip4_s {
  4608. u64 ltype_mask : 4;
  4609. u64 ltype_match : 4;
  4610. u64 lid : 3;
  4611. u64 reserved_11_63 : 53;
  4612. } s;
  4613. /* struct nixx_af_rx_def_iip4_s cn; */
  4614. };
  4615. static inline u64 NIXX_AF_RX_DEF_IIP4(void)
  4616. __attribute__ ((pure, always_inline));
  4617. static inline u64 NIXX_AF_RX_DEF_IIP4(void)
  4618. {
  4619. return 0x220;
  4620. }
  4621. /**
  4622. * Register (RVU_PF_BAR0) nix#_af_rx_def_iip6
  4623. *
  4624. * NIX AF Receive Inner IPv6 Header Definition Register Defines layer
  4625. * information in NPC_RESULT_S to identify an inner IPv6 header.
  4626. */
  4627. union nixx_af_rx_def_iip6 {
  4628. u64 u;
  4629. struct nixx_af_rx_def_iip6_s {
  4630. u64 ltype_mask : 4;
  4631. u64 ltype_match : 4;
  4632. u64 lid : 3;
  4633. u64 reserved_11_63 : 53;
  4634. } s;
  4635. /* struct nixx_af_rx_def_iip6_s cn; */
  4636. };
  4637. static inline u64 NIXX_AF_RX_DEF_IIP6(void)
  4638. __attribute__ ((pure, always_inline));
  4639. static inline u64 NIXX_AF_RX_DEF_IIP6(void)
  4640. {
  4641. return 0x240;
  4642. }
  4643. /**
  4644. * Register (RVU_PF_BAR0) nix#_af_rx_def_ipsec#
  4645. *
  4646. * INTERNAL: NIX AF Receive IPSEC Header Definition Registers Internal:
  4647. * Not used; no IPSEC fast-path.
  4648. */
  4649. union nixx_af_rx_def_ipsecx {
  4650. u64 u;
  4651. struct nixx_af_rx_def_ipsecx_s {
  4652. u64 ltype_mask : 4;
  4653. u64 ltype_match : 4;
  4654. u64 lid : 3;
  4655. u64 reserved_11 : 1;
  4656. u64 spi_offset : 4;
  4657. u64 spi_nz : 1;
  4658. u64 reserved_17_63 : 47;
  4659. } s;
  4660. /* struct nixx_af_rx_def_ipsecx_s cn; */
  4661. };
  4662. static inline u64 NIXX_AF_RX_DEF_IPSECX(u64 a)
  4663. __attribute__ ((pure, always_inline));
  4664. static inline u64 NIXX_AF_RX_DEF_IPSECX(u64 a)
  4665. {
  4666. return 0x2b0 + 8 * a;
  4667. }
  4668. /**
  4669. * Register (RVU_PF_BAR0) nix#_af_rx_def_isctp
  4670. *
  4671. * NIX AF Receive Inner SCTP Header Definition Register Defines layer
  4672. * information in NPC_RESULT_S to identify an inner SCTP header.
  4673. */
  4674. union nixx_af_rx_def_isctp {
  4675. u64 u;
  4676. struct nixx_af_rx_def_isctp_s {
  4677. u64 ltype_mask : 4;
  4678. u64 ltype_match : 4;
  4679. u64 lid : 3;
  4680. u64 reserved_11_63 : 53;
  4681. } s;
  4682. /* struct nixx_af_rx_def_isctp_s cn; */
  4683. };
  4684. static inline u64 NIXX_AF_RX_DEF_ISCTP(void)
  4685. __attribute__ ((pure, always_inline));
  4686. static inline u64 NIXX_AF_RX_DEF_ISCTP(void)
  4687. {
  4688. return 0x2a0;
  4689. }
  4690. /**
  4691. * Register (RVU_PF_BAR0) nix#_af_rx_def_itcp
  4692. *
  4693. * NIX AF Receive Inner TCP Header Definition Register Defines layer
  4694. * information in NPC_RESULT_S to identify an inner TCP header.
  4695. */
  4696. union nixx_af_rx_def_itcp {
  4697. u64 u;
  4698. struct nixx_af_rx_def_itcp_s {
  4699. u64 ltype_mask : 4;
  4700. u64 ltype_match : 4;
  4701. u64 lid : 3;
  4702. u64 reserved_11_63 : 53;
  4703. } s;
  4704. /* struct nixx_af_rx_def_itcp_s cn; */
  4705. };
  4706. static inline u64 NIXX_AF_RX_DEF_ITCP(void)
  4707. __attribute__ ((pure, always_inline));
  4708. static inline u64 NIXX_AF_RX_DEF_ITCP(void)
  4709. {
  4710. return 0x260;
  4711. }
  4712. /**
  4713. * Register (RVU_PF_BAR0) nix#_af_rx_def_iudp
  4714. *
  4715. * NIX AF Receive Inner UDP Header Definition Register Defines layer
  4716. * information in NPC_RESULT_S to identify an inner UDP header.
  4717. */
  4718. union nixx_af_rx_def_iudp {
  4719. u64 u;
  4720. struct nixx_af_rx_def_iudp_s {
  4721. u64 ltype_mask : 4;
  4722. u64 ltype_match : 4;
  4723. u64 lid : 3;
  4724. u64 reserved_11_63 : 53;
  4725. } s;
  4726. /* struct nixx_af_rx_def_iudp_s cn; */
  4727. };
  4728. static inline u64 NIXX_AF_RX_DEF_IUDP(void)
  4729. __attribute__ ((pure, always_inline));
  4730. static inline u64 NIXX_AF_RX_DEF_IUDP(void)
  4731. {
  4732. return 0x280;
  4733. }
  4734. /**
  4735. * Register (RVU_PF_BAR0) nix#_af_rx_def_oip4
  4736. *
  4737. * NIX AF Receive Outer IPv4 Header Definition Register Defines layer
  4738. * information in NPC_RESULT_S to identify an outer IPv4 L3 header.
  4739. * Typically the same as NPC_AF_PCK_DEF_OIP4.
  4740. */
  4741. union nixx_af_rx_def_oip4 {
  4742. u64 u;
  4743. struct nixx_af_rx_def_oip4_s {
  4744. u64 ltype_mask : 4;
  4745. u64 ltype_match : 4;
  4746. u64 lid : 3;
  4747. u64 reserved_11_63 : 53;
  4748. } s;
  4749. /* struct nixx_af_rx_def_oip4_s cn; */
  4750. };
  4751. static inline u64 NIXX_AF_RX_DEF_OIP4(void)
  4752. __attribute__ ((pure, always_inline));
  4753. static inline u64 NIXX_AF_RX_DEF_OIP4(void)
  4754. {
  4755. return 0x210;
  4756. }
  4757. /**
  4758. * Register (RVU_PF_BAR0) nix#_af_rx_def_oip6
  4759. *
  4760. * NIX AF Receive Outer IPv6 Header Definition Register Defines layer
  4761. * information in NPC_RESULT_S to identify an outer IPv6 header.
  4762. * Typically the same as NPC_AF_PCK_DEF_OIP6.
  4763. */
  4764. union nixx_af_rx_def_oip6 {
  4765. u64 u;
  4766. struct nixx_af_rx_def_oip6_s {
  4767. u64 ltype_mask : 4;
  4768. u64 ltype_match : 4;
  4769. u64 lid : 3;
  4770. u64 reserved_11_63 : 53;
  4771. } s;
  4772. /* struct nixx_af_rx_def_oip6_s cn; */
  4773. };
  4774. static inline u64 NIXX_AF_RX_DEF_OIP6(void)
  4775. __attribute__ ((pure, always_inline));
  4776. static inline u64 NIXX_AF_RX_DEF_OIP6(void)
  4777. {
  4778. return 0x230;
  4779. }
  4780. /**
  4781. * Register (RVU_PF_BAR0) nix#_af_rx_def_ol2
  4782. *
  4783. * NIX AF Receive Outer L2 Header Definition Register Defines layer
  4784. * information in NPC_RESULT_S to identify an outer L2/Ethernet header.
  4785. * Typically the same as NPC_AF_PCK_DEF_OL2.
  4786. */
  4787. union nixx_af_rx_def_ol2 {
  4788. u64 u;
  4789. struct nixx_af_rx_def_ol2_s {
  4790. u64 ltype_mask : 4;
  4791. u64 ltype_match : 4;
  4792. u64 lid : 3;
  4793. u64 reserved_11_63 : 53;
  4794. } s;
  4795. /* struct nixx_af_rx_def_ol2_s cn; */
  4796. };
  4797. static inline u64 NIXX_AF_RX_DEF_OL2(void)
  4798. __attribute__ ((pure, always_inline));
  4799. static inline u64 NIXX_AF_RX_DEF_OL2(void)
  4800. {
  4801. return 0x200;
  4802. }
  4803. /**
  4804. * Register (RVU_PF_BAR0) nix#_af_rx_def_osctp
  4805. *
  4806. * NIX AF Receive Outer SCTP Header Definition Register Defines layer
  4807. * information in NPC_RESULT_S to identify an outer SCTP header.
  4808. */
  4809. union nixx_af_rx_def_osctp {
  4810. u64 u;
  4811. struct nixx_af_rx_def_osctp_s {
  4812. u64 ltype_mask : 4;
  4813. u64 ltype_match : 4;
  4814. u64 lid : 3;
  4815. u64 reserved_11_63 : 53;
  4816. } s;
  4817. /* struct nixx_af_rx_def_osctp_s cn; */
  4818. };
  4819. static inline u64 NIXX_AF_RX_DEF_OSCTP(void)
  4820. __attribute__ ((pure, always_inline));
  4821. static inline u64 NIXX_AF_RX_DEF_OSCTP(void)
  4822. {
  4823. return 0x290;
  4824. }
  4825. /**
  4826. * Register (RVU_PF_BAR0) nix#_af_rx_def_otcp
  4827. *
  4828. * NIX AF Receive Outer TCP Header Definition Register Defines layer
  4829. * information in NPC_RESULT_S to identify an outer TCP header.
  4830. */
  4831. union nixx_af_rx_def_otcp {
  4832. u64 u;
  4833. struct nixx_af_rx_def_otcp_s {
  4834. u64 ltype_mask : 4;
  4835. u64 ltype_match : 4;
  4836. u64 lid : 3;
  4837. u64 reserved_11_63 : 53;
  4838. } s;
  4839. /* struct nixx_af_rx_def_otcp_s cn; */
  4840. };
  4841. static inline u64 NIXX_AF_RX_DEF_OTCP(void)
  4842. __attribute__ ((pure, always_inline));
  4843. static inline u64 NIXX_AF_RX_DEF_OTCP(void)
  4844. {
  4845. return 0x250;
  4846. }
  4847. /**
  4848. * Register (RVU_PF_BAR0) nix#_af_rx_def_oudp
  4849. *
  4850. * NIX AF Receive Outer UDP Header Definition Register Defines layer
  4851. * information in NPC_RESULT_S to identify an outer UDP header.
  4852. */
  4853. union nixx_af_rx_def_oudp {
  4854. u64 u;
  4855. struct nixx_af_rx_def_oudp_s {
  4856. u64 ltype_mask : 4;
  4857. u64 ltype_match : 4;
  4858. u64 lid : 3;
  4859. u64 reserved_11_63 : 53;
  4860. } s;
  4861. /* struct nixx_af_rx_def_oudp_s cn; */
  4862. };
  4863. static inline u64 NIXX_AF_RX_DEF_OUDP(void)
  4864. __attribute__ ((pure, always_inline));
  4865. static inline u64 NIXX_AF_RX_DEF_OUDP(void)
  4866. {
  4867. return 0x270;
  4868. }
  4869. /**
  4870. * Register (RVU_PF_BAR0) nix#_af_rx_flow_key_alg#_field#
  4871. *
  4872. * NIX AF Receive Flow Key Algorithm Field Registers A flow key algorithm
  4873. * defines how the 40-byte FLOW_KEY is formed from the received packet
  4874. * header. FLOW_KEY is formed using up to five header fields (this
  4875. * register's last index) with up to 16 bytes per field. Header fields
  4876. * must not overlap in FLOW_KEY. The algorithm (index {a} (ALG) of these
  4877. * registers) is selected by NIX_RX_ACTION_S[FLOW_KEY_ALG] from the
  4878. * packet's NPC_RESULT_S[ACTION]. Internal: 40-byte FLOW_KEY is wide
  4879. * enough to support an IPv6 5-tuple that includes a VXLAN/GENEVE/NVGRE
  4880. * tunnel ID, e.g: _ Source IP: 16B. _ Dest IP: 16B. _ Source port: 2B. _
  4881. * Dest port: 2B. _ Tunnel VNI/VSI: 3B. _ Total: 39B.
  4882. */
  4883. union nixx_af_rx_flow_key_algx_fieldx {
  4884. u64 u;
  4885. struct nixx_af_rx_flow_key_algx_fieldx_s {
  4886. u64 key_offset : 6;
  4887. u64 ln_mask : 1;
  4888. u64 fn_mask : 1;
  4889. u64 hdr_offset : 8;
  4890. u64 bytesm1 : 5;
  4891. u64 lid : 3;
  4892. u64 reserved_24 : 1;
  4893. u64 ena : 1;
  4894. u64 sel_chan : 1;
  4895. u64 ltype_mask : 4;
  4896. u64 ltype_match : 4;
  4897. u64 reserved_35_63 : 29;
  4898. } s;
  4899. /* struct nixx_af_rx_flow_key_algx_fieldx_s cn; */
  4900. };
  4901. static inline u64 NIXX_AF_RX_FLOW_KEY_ALGX_FIELDX(u64 a, u64 b)
  4902. __attribute__ ((pure, always_inline));
  4903. static inline u64 NIXX_AF_RX_FLOW_KEY_ALGX_FIELDX(u64 a, u64 b)
  4904. {
  4905. return 0x1800 + 0x40000 * a + 8 * b;
  4906. }
  4907. /**
  4908. * Register (RVU_PF_BAR0) nix#_af_rx_ipsec_gen_cfg
  4909. *
  4910. * INTERNAL: NIX AF Receive IPSEC General Configuration Register
  4911. * Internal: Not used; no IPSEC fast-path.
  4912. */
  4913. union nixx_af_rx_ipsec_gen_cfg {
  4914. u64 u;
  4915. struct nixx_af_rx_ipsec_gen_cfg_s {
  4916. u64 param2 : 16;
  4917. u64 param1 : 16;
  4918. u64 opcode : 16;
  4919. u64 egrp : 3;
  4920. u64 reserved_51_63 : 13;
  4921. } s;
  4922. /* struct nixx_af_rx_ipsec_gen_cfg_s cn; */
  4923. };
  4924. static inline u64 NIXX_AF_RX_IPSEC_GEN_CFG(void)
  4925. __attribute__ ((pure, always_inline));
  4926. static inline u64 NIXX_AF_RX_IPSEC_GEN_CFG(void)
  4927. {
  4928. return 0x300;
  4929. }
  4930. /**
  4931. * Register (RVU_PF_BAR0) nix#_af_rx_link#_cfg
  4932. *
  4933. * NIX AF Receive Link Configuration Registers Index enumerated by
  4934. * NIX_LINK_E.
  4935. */
  4936. union nixx_af_rx_linkx_cfg {
  4937. u64 u;
  4938. struct nixx_af_rx_linkx_cfg_s {
  4939. u64 minlen : 16;
  4940. u64 maxlen : 16;
  4941. u64 reserved_32_63 : 32;
  4942. } s;
  4943. /* struct nixx_af_rx_linkx_cfg_s cn; */
  4944. };
  4945. static inline u64 NIXX_AF_RX_LINKX_CFG(u64 a)
  4946. __attribute__ ((pure, always_inline));
  4947. static inline u64 NIXX_AF_RX_LINKX_CFG(u64 a)
  4948. {
  4949. return 0x540 + 0x10000 * a;
  4950. }
  4951. /**
  4952. * Register (RVU_PF_BAR0) nix#_af_rx_link#_sl#_spkt_cnt
  4953. *
  4954. * INTERNAL: NIX Receive Software Sync Link Packet Count Registers For
  4955. * diagnostic use only for debug of NIX_AF_RX_SW_SYNC[ENA] function. LINK
  4956. * index is enumerated by NIX_LINK_E. For the internal multicast/mirror
  4957. * link (NIX_LINK_E::MC), SL index is zero for multicast replay, one for
  4958. * mirror replay. SL index one is reserved for all other links.
  4959. * Internal: 802.3br frame preemption/express path is defeatured. Old
  4960. * definition of SL index: SL index is zero for non-express packets, one
  4961. * for express packets. For the internal NIX_LINK_E::MC, SL index is zero
  4962. * for multicast replay, one for mirror replay.
  4963. */
  4964. union nixx_af_rx_linkx_slx_spkt_cnt {
  4965. u64 u;
  4966. struct nixx_af_rx_linkx_slx_spkt_cnt_s {
  4967. u64 in_cnt : 20;
  4968. u64 reserved_20_31 : 12;
  4969. u64 out_cnt : 20;
  4970. u64 reserved_52_63 : 12;
  4971. } s;
  4972. /* struct nixx_af_rx_linkx_slx_spkt_cnt_s cn; */
  4973. };
  4974. static inline u64 NIXX_AF_RX_LINKX_SLX_SPKT_CNT(u64 a, u64 b)
  4975. __attribute__ ((pure, always_inline));
  4976. static inline u64 NIXX_AF_RX_LINKX_SLX_SPKT_CNT(u64 a, u64 b)
  4977. {
  4978. return 0x500 + 0x10000 * a + 8 * b;
  4979. }
  4980. /**
  4981. * Register (RVU_PF_BAR0) nix#_af_rx_link#_wrr_cfg
  4982. *
  4983. * NIX AF Receive Link Weighted Round Robin Configuration Registers Index
  4984. * enumerated by NIX_LINK_E.
  4985. */
  4986. union nixx_af_rx_linkx_wrr_cfg {
  4987. u64 u;
  4988. struct nixx_af_rx_linkx_wrr_cfg_s {
  4989. u64 weight : 8;
  4990. u64 reserved_8_63 : 56;
  4991. } s;
  4992. /* struct nixx_af_rx_linkx_wrr_cfg_s cn; */
  4993. };
  4994. static inline u64 NIXX_AF_RX_LINKX_WRR_CFG(u64 a)
  4995. __attribute__ ((pure, always_inline));
  4996. static inline u64 NIXX_AF_RX_LINKX_WRR_CFG(u64 a)
  4997. {
  4998. return 0x560 + 0x10000 * a;
  4999. }
  5000. /**
  5001. * Register (RVU_PF_BAR0) nix#_af_rx_mcast_base
  5002. *
  5003. * NIX AF Receive Multicast/Mirror Table Base Address Register This
  5004. * register specifies the base AF IOVA of the receive multicast/mirror
  5005. * table in NDC/LLC/DRAM. The table consists of 1 \<\<
  5006. * (NIX_AF_RX_MCAST_CFG[SIZE] + 8) contiguous NIX_RX_MCE_S structures.
  5007. * The size of each structure is 1 \<\< NIX_AF_CONST3[MCE_LOG2BYTES].
  5008. * The table contains multicast/mirror replication lists. Each list
  5009. * consists of linked entries with NIX_RX_MCE_S[EOL] = 1 in the last
  5010. * entry. All lists must reside within the table size specified by
  5011. * NIX_AF_RX_MCAST_CFG[SIZE]. A mirror replication list will typically
  5012. * consist of two entries, but that is not checked or enforced by
  5013. * hardware. A receive packet is multicast when the action returned by
  5014. * NPC has NIX_RX_ACTION_S[OP] = NIX_RX_ACTIONOP_E::MCAST. A receive
  5015. * packet is mirrored when the action returned by NPC has
  5016. * NIX_RX_ACTION_S[OP] = NIX_RX_ACTIONOP_E::MIRROR. In both cases,
  5017. * NIX_RX_ACTION_S[INDEX] specifies the index of the replication list's
  5018. * first NIX_RX_MCE_S in the table, and a linked entry with
  5019. * NIX_RX_MCE_S[EOL] = 1 indicates the end of list. If a mirrored flow
  5020. * is part of a multicast replication list, software should include the
  5021. * two mirror entries in that list. Internal: A multicast list may have
  5022. * multiple entries for the same LF (e.g. for future RoCE/IB multicast).
  5023. */
  5024. union nixx_af_rx_mcast_base {
  5025. u64 u;
  5026. struct nixx_af_rx_mcast_base_s {
  5027. u64 reserved_0_6 : 7;
  5028. u64 addr : 46;
  5029. u64 reserved_53_63 : 11;
  5030. } s;
  5031. /* struct nixx_af_rx_mcast_base_s cn; */
  5032. };
  5033. static inline u64 NIXX_AF_RX_MCAST_BASE(void)
  5034. __attribute__ ((pure, always_inline));
  5035. static inline u64 NIXX_AF_RX_MCAST_BASE(void)
  5036. {
  5037. return 0x100;
  5038. }
  5039. /**
  5040. * Register (RVU_PF_BAR0) nix#_af_rx_mcast_buf_base
  5041. *
  5042. * NIX AF Receive Multicast Buffer Base Address Register This register
  5043. * specifies the base AF IOVA of the receive multicast buffers in
  5044. * NDC/LLC/DRAM. These buffers are used to temporarily store packets
  5045. * whose action returned by NPC has NIX_RX_ACTION_S[OP] =
  5046. * NIX_RX_ACTIONOP_E::MCAST. The number of buffers is configured by
  5047. * NIX_AF_RX_MCAST_BUF_CFG[SIZE]. If the number of free buffers is
  5048. * insufficient for a received multicast packet, hardware tail drops the
  5049. * packet and sets NIX_AF_GEN_INT[RX_MCAST_DROP]. Hardware prioritizes
  5050. * the processing of RX mirror packets over RX multicast packets.
  5051. */
  5052. union nixx_af_rx_mcast_buf_base {
  5053. u64 u;
  5054. struct nixx_af_rx_mcast_buf_base_s {
  5055. u64 reserved_0_6 : 7;
  5056. u64 addr : 46;
  5057. u64 reserved_53_63 : 11;
  5058. } s;
  5059. /* struct nixx_af_rx_mcast_buf_base_s cn; */
  5060. };
  5061. static inline u64 NIXX_AF_RX_MCAST_BUF_BASE(void)
  5062. __attribute__ ((pure, always_inline));
  5063. static inline u64 NIXX_AF_RX_MCAST_BUF_BASE(void)
  5064. {
  5065. return 0x120;
  5066. }
  5067. /**
  5068. * Register (RVU_PF_BAR0) nix#_af_rx_mcast_buf_cfg
  5069. *
  5070. * NIX AF Receive Multicast Buffer Configuration Register See
  5071. * NIX_AF_RX_MCAST_BUF_BASE.
  5072. */
  5073. union nixx_af_rx_mcast_buf_cfg {
  5074. u64 u;
  5075. struct nixx_af_rx_mcast_buf_cfg_s {
  5076. u64 size : 4;
  5077. u64 way_mask : 16;
  5078. u64 caching : 1;
  5079. u64 reserved_21_23 : 3;
  5080. u64 npc_replay_pkind : 6;
  5081. u64 reserved_30_31 : 2;
  5082. u64 free_buf_level : 11;
  5083. u64 reserved_43_61 : 19;
  5084. u64 busy : 1;
  5085. u64 ena : 1;
  5086. } s;
  5087. struct nixx_af_rx_mcast_buf_cfg_cn96xxp1 {
  5088. u64 size : 4;
  5089. u64 way_mask : 16;
  5090. u64 caching : 1;
  5091. u64 reserved_21_23 : 3;
  5092. u64 npc_replay_pkind : 6;
  5093. u64 reserved_30_31 : 2;
  5094. u64 free_buf_level : 11;
  5095. u64 reserved_43_61 : 19;
  5096. u64 reserved_62 : 1;
  5097. u64 ena : 1;
  5098. } cn96xxp1;
  5099. /* struct nixx_af_rx_mcast_buf_cfg_s cn96xxp3; */
  5100. struct nixx_af_rx_mcast_buf_cfg_cnf95xxp1 {
  5101. u64 size : 4;
  5102. u64 way_mask : 16;
  5103. u64 caching : 1;
  5104. u64 reserved_21_23 : 3;
  5105. u64 npc_replay_pkind : 6;
  5106. u64 reserved_30_31 : 2;
  5107. u64 free_buf_level : 11;
  5108. u64 reserved_43_62 : 20;
  5109. u64 ena : 1;
  5110. } cnf95xxp1;
  5111. /* struct nixx_af_rx_mcast_buf_cfg_s cnf95xxp2; */
  5112. };
  5113. static inline u64 NIXX_AF_RX_MCAST_BUF_CFG(void)
  5114. __attribute__ ((pure, always_inline));
  5115. static inline u64 NIXX_AF_RX_MCAST_BUF_CFG(void)
  5116. {
  5117. return 0x130;
  5118. }
  5119. /**
  5120. * Register (RVU_PF_BAR0) nix#_af_rx_mcast_cfg
  5121. *
  5122. * NIX AF Receive Multicast/Mirror Table Configuration Register See
  5123. * NIX_AF_RX_MCAST_BASE.
  5124. */
  5125. union nixx_af_rx_mcast_cfg {
  5126. u64 u;
  5127. struct nixx_af_rx_mcast_cfg_s {
  5128. u64 size : 4;
  5129. u64 max_list_lenm1 : 8;
  5130. u64 reserved_12_19 : 8;
  5131. u64 way_mask : 16;
  5132. u64 caching : 1;
  5133. u64 reserved_37_63 : 27;
  5134. } s;
  5135. /* struct nixx_af_rx_mcast_cfg_s cn; */
  5136. };
  5137. static inline u64 NIXX_AF_RX_MCAST_CFG(void)
  5138. __attribute__ ((pure, always_inline));
  5139. static inline u64 NIXX_AF_RX_MCAST_CFG(void)
  5140. {
  5141. return 0x110;
  5142. }
  5143. /**
  5144. * Register (RVU_PF_BAR0) nix#_af_rx_mirror_buf_base
  5145. *
  5146. * NIX AF Receive Mirror Buffer Base Address Register This register
  5147. * specifies the base AF IOVA of the receive mirror buffers in
  5148. * NDC/LLC/DRAM. These buffers are used to temporarily store packets
  5149. * whose action returned by NPC has NIX_RX_ACTION_S[OP] =
  5150. * NIX_RX_ACTIONOP_E::MIRROR. The number of buffers is configured by
  5151. * NIX_AF_RX_MIRROR_BUF_CFG[SIZE]. If the number of free buffers is
  5152. * insufficient for a received multicast packet, hardware tail drops the
  5153. * packet and sets NIX_AF_GEN_INT[RX_MIRROR_DROP]. Hardware prioritizes
  5154. * the processing of RX mirror packets over RX multicast packets.
  5155. */
  5156. union nixx_af_rx_mirror_buf_base {
  5157. u64 u;
  5158. struct nixx_af_rx_mirror_buf_base_s {
  5159. u64 reserved_0_6 : 7;
  5160. u64 addr : 46;
  5161. u64 reserved_53_63 : 11;
  5162. } s;
  5163. /* struct nixx_af_rx_mirror_buf_base_s cn; */
  5164. };
  5165. static inline u64 NIXX_AF_RX_MIRROR_BUF_BASE(void)
  5166. __attribute__ ((pure, always_inline));
  5167. static inline u64 NIXX_AF_RX_MIRROR_BUF_BASE(void)
  5168. {
  5169. return 0x140;
  5170. }
  5171. /**
  5172. * Register (RVU_PF_BAR0) nix#_af_rx_mirror_buf_cfg
  5173. *
  5174. * NIX AF Receive Mirror Buffer Configuration Register See
  5175. * NIX_AF_RX_MIRROR_BUF_BASE.
  5176. */
  5177. union nixx_af_rx_mirror_buf_cfg {
  5178. u64 u;
  5179. struct nixx_af_rx_mirror_buf_cfg_s {
  5180. u64 size : 4;
  5181. u64 way_mask : 16;
  5182. u64 caching : 1;
  5183. u64 reserved_21_23 : 3;
  5184. u64 npc_replay_pkind : 6;
  5185. u64 reserved_30_31 : 2;
  5186. u64 free_buf_level : 11;
  5187. u64 reserved_43_61 : 19;
  5188. u64 busy : 1;
  5189. u64 ena : 1;
  5190. } s;
  5191. struct nixx_af_rx_mirror_buf_cfg_cn96xxp1 {
  5192. u64 size : 4;
  5193. u64 way_mask : 16;
  5194. u64 caching : 1;
  5195. u64 reserved_21_23 : 3;
  5196. u64 npc_replay_pkind : 6;
  5197. u64 reserved_30_31 : 2;
  5198. u64 free_buf_level : 11;
  5199. u64 reserved_43_61 : 19;
  5200. u64 reserved_62 : 1;
  5201. u64 ena : 1;
  5202. } cn96xxp1;
  5203. /* struct nixx_af_rx_mirror_buf_cfg_s cn96xxp3; */
  5204. struct nixx_af_rx_mirror_buf_cfg_cnf95xxp1 {
  5205. u64 size : 4;
  5206. u64 way_mask : 16;
  5207. u64 caching : 1;
  5208. u64 reserved_21_23 : 3;
  5209. u64 npc_replay_pkind : 6;
  5210. u64 reserved_30_31 : 2;
  5211. u64 free_buf_level : 11;
  5212. u64 reserved_43_62 : 20;
  5213. u64 ena : 1;
  5214. } cnf95xxp1;
  5215. /* struct nixx_af_rx_mirror_buf_cfg_s cnf95xxp2; */
  5216. };
  5217. static inline u64 NIXX_AF_RX_MIRROR_BUF_CFG(void)
  5218. __attribute__ ((pure, always_inline));
  5219. static inline u64 NIXX_AF_RX_MIRROR_BUF_CFG(void)
  5220. {
  5221. return 0x148;
  5222. }
  5223. /**
  5224. * Register (RVU_PF_BAR0) nix#_af_rx_npc_mc_drop
  5225. *
  5226. * NIX AF Multicast Drop Statistics Register The counter increments for
  5227. * every dropped MC packet marked by the NPC.
  5228. */
  5229. union nixx_af_rx_npc_mc_drop {
  5230. u64 u;
  5231. struct nixx_af_rx_npc_mc_drop_s {
  5232. u64 stat : 48;
  5233. u64 reserved_48_63 : 16;
  5234. } s;
  5235. /* struct nixx_af_rx_npc_mc_drop_s cn; */
  5236. };
  5237. static inline u64 NIXX_AF_RX_NPC_MC_DROP(void)
  5238. __attribute__ ((pure, always_inline));
  5239. static inline u64 NIXX_AF_RX_NPC_MC_DROP(void)
  5240. {
  5241. return 0x4710;
  5242. }
  5243. /**
  5244. * Register (RVU_PF_BAR0) nix#_af_rx_npc_mc_rcv
  5245. *
  5246. * NIX AF Multicast Receive Statistics Register The counter increments
  5247. * for every received MC packet marked by the NPC.
  5248. */
  5249. union nixx_af_rx_npc_mc_rcv {
  5250. u64 u;
  5251. struct nixx_af_rx_npc_mc_rcv_s {
  5252. u64 stat : 48;
  5253. u64 reserved_48_63 : 16;
  5254. } s;
  5255. /* struct nixx_af_rx_npc_mc_rcv_s cn; */
  5256. };
  5257. static inline u64 NIXX_AF_RX_NPC_MC_RCV(void)
  5258. __attribute__ ((pure, always_inline));
  5259. static inline u64 NIXX_AF_RX_NPC_MC_RCV(void)
  5260. {
  5261. return 0x4700;
  5262. }
  5263. /**
  5264. * Register (RVU_PF_BAR0) nix#_af_rx_npc_mirror_drop
  5265. *
  5266. * NIX AF Mirror Drop Statistics Register The counter increments for
  5267. * every dropped MIRROR packet marked by the NPC.
  5268. */
  5269. union nixx_af_rx_npc_mirror_drop {
  5270. u64 u;
  5271. struct nixx_af_rx_npc_mirror_drop_s {
  5272. u64 stat : 48;
  5273. u64 reserved_48_63 : 16;
  5274. } s;
  5275. /* struct nixx_af_rx_npc_mirror_drop_s cn; */
  5276. };
  5277. static inline u64 NIXX_AF_RX_NPC_MIRROR_DROP(void)
  5278. __attribute__ ((pure, always_inline));
  5279. static inline u64 NIXX_AF_RX_NPC_MIRROR_DROP(void)
  5280. {
  5281. return 0x4730;
  5282. }
  5283. /**
  5284. * Register (RVU_PF_BAR0) nix#_af_rx_npc_mirror_rcv
  5285. *
  5286. * NIX AF Mirror Receive Statistics Register The counter increments for
  5287. * every received MIRROR packet marked by the NPC.
  5288. */
  5289. union nixx_af_rx_npc_mirror_rcv {
  5290. u64 u;
  5291. struct nixx_af_rx_npc_mirror_rcv_s {
  5292. u64 stat : 48;
  5293. u64 reserved_48_63 : 16;
  5294. } s;
  5295. /* struct nixx_af_rx_npc_mirror_rcv_s cn; */
  5296. };
  5297. static inline u64 NIXX_AF_RX_NPC_MIRROR_RCV(void)
  5298. __attribute__ ((pure, always_inline));
  5299. static inline u64 NIXX_AF_RX_NPC_MIRROR_RCV(void)
  5300. {
  5301. return 0x4720;
  5302. }
  5303. /**
  5304. * Register (RVU_PF_BAR0) nix#_af_rx_sw_sync
  5305. *
  5306. * NIX AF Receive Software Sync Register
  5307. */
  5308. union nixx_af_rx_sw_sync {
  5309. u64 u;
  5310. struct nixx_af_rx_sw_sync_s {
  5311. u64 ena : 1;
  5312. u64 reserved_1_63 : 63;
  5313. } s;
  5314. /* struct nixx_af_rx_sw_sync_s cn; */
  5315. };
  5316. static inline u64 NIXX_AF_RX_SW_SYNC(void)
  5317. __attribute__ ((pure, always_inline));
  5318. static inline u64 NIXX_AF_RX_SW_SYNC(void)
  5319. {
  5320. return 0x550;
  5321. }
  5322. /**
  5323. * Register (RVU_PF_BAR0) nix#_af_sdp_hw_xoff#
  5324. *
  5325. * NIX AF SDP Transmit Link Hardware Controlled XOFF Registers .
  5326. */
  5327. union nixx_af_sdp_hw_xoffx {
  5328. u64 u;
  5329. struct nixx_af_sdp_hw_xoffx_s {
  5330. u64 chan_xoff : 64;
  5331. } s;
  5332. /* struct nixx_af_sdp_hw_xoffx_s cn; */
  5333. };
  5334. static inline u64 NIXX_AF_SDP_HW_XOFFX(u64 a)
  5335. __attribute__ ((pure, always_inline));
  5336. static inline u64 NIXX_AF_SDP_HW_XOFFX(u64 a)
  5337. {
  5338. return 0xac0 + 8 * a;
  5339. }
  5340. /**
  5341. * Register (RVU_PF_BAR0) nix#_af_sdp_link_credit
  5342. *
  5343. * NIX AF Transmit Link SDP Credit Register This register tracks SDP link
  5344. * credits.
  5345. */
  5346. union nixx_af_sdp_link_credit {
  5347. u64 u;
  5348. struct nixx_af_sdp_link_credit_s {
  5349. u64 reserved_0 : 1;
  5350. u64 cc_enable : 1;
  5351. u64 cc_packet_cnt : 10;
  5352. u64 cc_unit_cnt : 20;
  5353. u64 reserved_32_62 : 31;
  5354. u64 pse_pkt_id_lmt : 1;
  5355. } s;
  5356. struct nixx_af_sdp_link_credit_cn96xx {
  5357. u64 reserved_0 : 1;
  5358. u64 cc_enable : 1;
  5359. u64 cc_packet_cnt : 10;
  5360. u64 cc_unit_cnt : 20;
  5361. u64 reserved_32_62 : 31;
  5362. u64 reserved_63 : 1;
  5363. } cn96xx;
  5364. /* struct nixx_af_sdp_link_credit_s cnf95xx; */
  5365. };
  5366. static inline u64 NIXX_AF_SDP_LINK_CREDIT(void)
  5367. __attribute__ ((pure, always_inline));
  5368. static inline u64 NIXX_AF_SDP_LINK_CREDIT(void)
  5369. {
  5370. return 0xa40;
  5371. }
  5372. /**
  5373. * Register (RVU_PF_BAR0) nix#_af_sdp_sw_xoff#
  5374. *
  5375. * INTERNAL: NIX AF SDP Transmit Link Software Controlled XOFF Registers
  5376. * Internal: Defeatured registers. Software should use
  5377. * NIX_AF_TL4()_SW_XOFF registers instead.
  5378. */
  5379. union nixx_af_sdp_sw_xoffx {
  5380. u64 u;
  5381. struct nixx_af_sdp_sw_xoffx_s {
  5382. u64 chan_xoff : 64;
  5383. } s;
  5384. /* struct nixx_af_sdp_sw_xoffx_s cn; */
  5385. };
  5386. static inline u64 NIXX_AF_SDP_SW_XOFFX(u64 a)
  5387. __attribute__ ((pure, always_inline));
  5388. static inline u64 NIXX_AF_SDP_SW_XOFFX(u64 a)
  5389. {
  5390. return 0xa60 + 8 * a;
  5391. }
  5392. /**
  5393. * Register (RVU_PF_BAR0) nix#_af_sdp_tx_fifo_status
  5394. *
  5395. * NIX AF SDP Transmit FIFO Status Register Status of FIFO which
  5396. * transmits packets to SDP.
  5397. */
  5398. union nixx_af_sdp_tx_fifo_status {
  5399. u64 u;
  5400. struct nixx_af_sdp_tx_fifo_status_s {
  5401. u64 count : 12;
  5402. u64 reserved_12_63 : 52;
  5403. } s;
  5404. /* struct nixx_af_sdp_tx_fifo_status_s cn; */
  5405. };
  5406. static inline u64 NIXX_AF_SDP_TX_FIFO_STATUS(void)
  5407. __attribute__ ((pure, always_inline));
  5408. static inline u64 NIXX_AF_SDP_TX_FIFO_STATUS(void)
  5409. {
  5410. return 0x650;
  5411. }
  5412. /**
  5413. * Register (RVU_PF_BAR0) nix#_af_seb_active_cycles_pc#
  5414. *
  5415. * NIX AF Active Cycles Register These registers are indexed by the
  5416. * conditional clock domain number.
  5417. */
  5418. union nixx_af_seb_active_cycles_pcx {
  5419. u64 u;
  5420. struct nixx_af_seb_active_cycles_pcx_s {
  5421. u64 act_cyc : 64;
  5422. } s;
  5423. /* struct nixx_af_seb_active_cycles_pcx_s cn; */
  5424. };
  5425. static inline u64 NIXX_AF_SEB_ACTIVE_CYCLES_PCX(u64 a)
  5426. __attribute__ ((pure, always_inline));
  5427. static inline u64 NIXX_AF_SEB_ACTIVE_CYCLES_PCX(u64 a)
  5428. {
  5429. return 0x6c0 + 8 * a;
  5430. }
  5431. /**
  5432. * Register (RVU_PF_BAR0) nix#_af_seb_bp_test
  5433. *
  5434. * INTERNAL: NIX AF SEB Backpressure Test Register
  5435. */
  5436. union nixx_af_seb_bp_test {
  5437. u64 u;
  5438. struct nixx_af_seb_bp_test_s {
  5439. u64 lfsr_freq : 12;
  5440. u64 reserved_12_15 : 4;
  5441. u64 bp_cfg : 14;
  5442. u64 reserved_30_47 : 18;
  5443. u64 enable : 7;
  5444. u64 reserved_55_63 : 9;
  5445. } s;
  5446. /* struct nixx_af_seb_bp_test_s cn; */
  5447. };
  5448. static inline u64 NIXX_AF_SEB_BP_TEST(void)
  5449. __attribute__ ((pure, always_inline));
  5450. static inline u64 NIXX_AF_SEB_BP_TEST(void)
  5451. {
  5452. return 0x630;
  5453. }
  5454. /**
  5455. * Register (RVU_PF_BAR0) nix#_af_seb_cfg
  5456. *
  5457. * NIX SEB Configuration Register
  5458. */
  5459. union nixx_af_seb_cfg {
  5460. u64 u;
  5461. struct nixx_af_seb_cfg_s {
  5462. u64 sg_ndc_sel : 1;
  5463. u64 reserved_1_63 : 63;
  5464. } s;
  5465. /* struct nixx_af_seb_cfg_s cn; */
  5466. };
  5467. static inline u64 NIXX_AF_SEB_CFG(void)
  5468. __attribute__ ((pure, always_inline));
  5469. static inline u64 NIXX_AF_SEB_CFG(void)
  5470. {
  5471. return 0x5f0;
  5472. }
  5473. /**
  5474. * Register (RVU_PF_BAR0) nix#_af_seb_eco
  5475. *
  5476. * INTERNAL: AF SEB ECO Register
  5477. */
  5478. union nixx_af_seb_eco {
  5479. u64 u;
  5480. struct nixx_af_seb_eco_s {
  5481. u64 eco_rw : 64;
  5482. } s;
  5483. /* struct nixx_af_seb_eco_s cn; */
  5484. };
  5485. static inline u64 NIXX_AF_SEB_ECO(void)
  5486. __attribute__ ((pure, always_inline));
  5487. static inline u64 NIXX_AF_SEB_ECO(void)
  5488. {
  5489. return 0x5c0;
  5490. }
  5491. /**
  5492. * Register (RVU_PF_BAR0) nix#_af_seb_pipe_bp_test#
  5493. *
  5494. * INTERNAL: NIX AF SEB Pipe Backpressure Test Registers
  5495. */
  5496. union nixx_af_seb_pipe_bp_testx {
  5497. u64 u;
  5498. struct nixx_af_seb_pipe_bp_testx_s {
  5499. u64 lfsr_freq : 12;
  5500. u64 reserved_12_15 : 4;
  5501. u64 bp_cfg : 24;
  5502. u64 reserved_40_47 : 8;
  5503. u64 enable : 12;
  5504. u64 reserved_60_63 : 4;
  5505. } s;
  5506. /* struct nixx_af_seb_pipe_bp_testx_s cn; */
  5507. };
  5508. static inline u64 NIXX_AF_SEB_PIPE_BP_TESTX(u64 a)
  5509. __attribute__ ((pure, always_inline));
  5510. static inline u64 NIXX_AF_SEB_PIPE_BP_TESTX(u64 a)
  5511. {
  5512. return 0x600 + 0x10 * a;
  5513. }
  5514. /**
  5515. * Register (RVU_PF_BAR0) nix#_af_seb_pipeb_bp_test#
  5516. *
  5517. * INTERNAL: NIX AF SEB Pipe Backpressure Test Registers
  5518. */
  5519. union nixx_af_seb_pipeb_bp_testx {
  5520. u64 u;
  5521. struct nixx_af_seb_pipeb_bp_testx_s {
  5522. u64 lfsr_freq : 12;
  5523. u64 reserved_12_15 : 4;
  5524. u64 bp_cfg : 18;
  5525. u64 reserved_34_47 : 14;
  5526. u64 enable : 9;
  5527. u64 reserved_57_63 : 7;
  5528. } s;
  5529. /* struct nixx_af_seb_pipeb_bp_testx_s cn; */
  5530. };
  5531. static inline u64 NIXX_AF_SEB_PIPEB_BP_TESTX(u64 a)
  5532. __attribute__ ((pure, always_inline));
  5533. static inline u64 NIXX_AF_SEB_PIPEB_BP_TESTX(u64 a)
  5534. {
  5535. return 0x608 + 0x10 * a;
  5536. }
  5537. /**
  5538. * Register (RVU_PF_BAR0) nix#_af_seb_wd_tick_divider
  5539. *
  5540. * INTERNAL: NIX AF SEB TSTMP Watchdog Tick Divider Register
  5541. */
  5542. union nixx_af_seb_wd_tick_divider {
  5543. u64 u;
  5544. struct nixx_af_seb_wd_tick_divider_s {
  5545. u64 tick_div_cfg : 7;
  5546. u64 reserved_7_63 : 57;
  5547. } s;
  5548. /* struct nixx_af_seb_wd_tick_divider_s cn; */
  5549. };
  5550. static inline u64 NIXX_AF_SEB_WD_TICK_DIVIDER(void)
  5551. __attribute__ ((pure, always_inline));
  5552. static inline u64 NIXX_AF_SEB_WD_TICK_DIVIDER(void)
  5553. {
  5554. return 0x6f0;
  5555. }
  5556. /**
  5557. * Register (RVU_PF_BAR0) nix#_af_smq#_cfg
  5558. *
  5559. * NIX AF SQM PSE Queue Configuration Registers
  5560. */
  5561. union nixx_af_smqx_cfg {
  5562. u64 u;
  5563. struct nixx_af_smqx_cfg_s {
  5564. u64 minlen : 7;
  5565. u64 desc_shp_ctl_dis : 1;
  5566. u64 maxlen : 16;
  5567. u64 lf : 7;
  5568. u64 reserved_31_35 : 5;
  5569. u64 max_vtag_ins : 3;
  5570. u64 rr_minlen : 9;
  5571. u64 express : 1;
  5572. u64 flush : 1;
  5573. u64 enq_xoff : 1;
  5574. u64 pri_thr : 6;
  5575. u64 reserved_57_63 : 7;
  5576. } s;
  5577. /* struct nixx_af_smqx_cfg_s cn; */
  5578. };
  5579. static inline u64 NIXX_AF_SMQX_CFG(u64 a)
  5580. __attribute__ ((pure, always_inline));
  5581. static inline u64 NIXX_AF_SMQX_CFG(u64 a)
  5582. {
  5583. return 0x700 + 0x10000 * a;
  5584. }
  5585. /**
  5586. * Register (RVU_PF_BAR0) nix#_af_smq#_head
  5587. *
  5588. * NIX AF SQM SMQ Head Register These registers track the head of the SMQ
  5589. * linked list.
  5590. */
  5591. union nixx_af_smqx_head {
  5592. u64 u;
  5593. struct nixx_af_smqx_head_s {
  5594. u64 sq_idx : 20;
  5595. u64 valid : 1;
  5596. u64 reserved_21_63 : 43;
  5597. } s;
  5598. /* struct nixx_af_smqx_head_s cn; */
  5599. };
  5600. static inline u64 NIXX_AF_SMQX_HEAD(u64 a)
  5601. __attribute__ ((pure, always_inline));
  5602. static inline u64 NIXX_AF_SMQX_HEAD(u64 a)
  5603. {
  5604. return 0x710 + 0x10000 * a;
  5605. }
  5606. /**
  5607. * Register (RVU_PF_BAR0) nix#_af_smq#_nxt_head
  5608. *
  5609. * NIX AF SQM SMQ Next Head Register These registers track the next head
  5610. * of the SMQ linked list.
  5611. */
  5612. union nixx_af_smqx_nxt_head {
  5613. u64 u;
  5614. struct nixx_af_smqx_nxt_head_s {
  5615. u64 sq_idx : 20;
  5616. u64 valid : 1;
  5617. u64 reserved_21_63 : 43;
  5618. } s;
  5619. /* struct nixx_af_smqx_nxt_head_s cn; */
  5620. };
  5621. static inline u64 NIXX_AF_SMQX_NXT_HEAD(u64 a)
  5622. __attribute__ ((pure, always_inline));
  5623. static inline u64 NIXX_AF_SMQX_NXT_HEAD(u64 a)
  5624. {
  5625. return 0x740 + 0x10000 * a;
  5626. }
  5627. /**
  5628. * Register (RVU_PF_BAR0) nix#_af_smq#_status
  5629. *
  5630. * NIX AF SQM SMQ Status Register These registers track the status of the
  5631. * SMQ FIFO.
  5632. */
  5633. union nixx_af_smqx_status {
  5634. u64 u;
  5635. struct nixx_af_smqx_status_s {
  5636. u64 level : 7;
  5637. u64 reserved_7_63 : 57;
  5638. } s;
  5639. /* struct nixx_af_smqx_status_s cn; */
  5640. };
  5641. static inline u64 NIXX_AF_SMQX_STATUS(u64 a)
  5642. __attribute__ ((pure, always_inline));
  5643. static inline u64 NIXX_AF_SMQX_STATUS(u64 a)
  5644. {
  5645. return 0x730 + 0x10000 * a;
  5646. }
  5647. /**
  5648. * Register (RVU_PF_BAR0) nix#_af_smq#_tail
  5649. *
  5650. * NIX AF SQM SMQ Head Register These registers track the tail of SMQ
  5651. * linked list.
  5652. */
  5653. union nixx_af_smqx_tail {
  5654. u64 u;
  5655. struct nixx_af_smqx_tail_s {
  5656. u64 sq_idx : 20;
  5657. u64 valid : 1;
  5658. u64 reserved_21_63 : 43;
  5659. } s;
  5660. /* struct nixx_af_smqx_tail_s cn; */
  5661. };
  5662. static inline u64 NIXX_AF_SMQX_TAIL(u64 a)
  5663. __attribute__ ((pure, always_inline));
  5664. static inline u64 NIXX_AF_SMQX_TAIL(u64 a)
  5665. {
  5666. return 0x720 + 0x10000 * a;
  5667. }
  5668. /**
  5669. * Register (RVU_PF_BAR0) nix#_af_sq_const
  5670. *
  5671. * NIX AF SQ Constants Register This register contains constants for
  5672. * software discovery.
  5673. */
  5674. union nixx_af_sq_const {
  5675. u64 u;
  5676. struct nixx_af_sq_const_s {
  5677. u64 queues_per_lf : 24;
  5678. u64 smq_depth : 10;
  5679. u64 sqb_size : 16;
  5680. u64 reserved_50_63 : 14;
  5681. } s;
  5682. /* struct nixx_af_sq_const_s cn; */
  5683. };
  5684. static inline u64 NIXX_AF_SQ_CONST(void)
  5685. __attribute__ ((pure, always_inline));
  5686. static inline u64 NIXX_AF_SQ_CONST(void)
  5687. {
  5688. return 0x40;
  5689. }
  5690. /**
  5691. * Register (RVU_PF_BAR0) nix#_af_sqm_active_cycles_pc
  5692. *
  5693. * NIX AF SQM Active Cycles Register These registers are indexed by the
  5694. * conditional clock domain number.
  5695. */
  5696. union nixx_af_sqm_active_cycles_pc {
  5697. u64 u;
  5698. struct nixx_af_sqm_active_cycles_pc_s {
  5699. u64 act_cyc : 64;
  5700. } s;
  5701. /* struct nixx_af_sqm_active_cycles_pc_s cn; */
  5702. };
  5703. static inline u64 NIXX_AF_SQM_ACTIVE_CYCLES_PC(void)
  5704. __attribute__ ((pure, always_inline));
  5705. static inline u64 NIXX_AF_SQM_ACTIVE_CYCLES_PC(void)
  5706. {
  5707. return 0x770;
  5708. }
  5709. /**
  5710. * Register (RVU_PF_BAR0) nix#_af_sqm_bp_test#
  5711. *
  5712. * INTERNAL: NIX AF SQM Backpressure Test Register
  5713. */
  5714. union nixx_af_sqm_bp_testx {
  5715. u64 u;
  5716. struct nixx_af_sqm_bp_testx_s {
  5717. u64 lfsr_freq : 12;
  5718. u64 reserved_12_15 : 4;
  5719. u64 bp_cfg : 8;
  5720. u64 reserved_24_59 : 36;
  5721. u64 enable : 4;
  5722. } s;
  5723. /* struct nixx_af_sqm_bp_testx_s cn; */
  5724. };
  5725. static inline u64 NIXX_AF_SQM_BP_TESTX(u64 a)
  5726. __attribute__ ((pure, always_inline));
  5727. static inline u64 NIXX_AF_SQM_BP_TESTX(u64 a)
  5728. {
  5729. return 0x760 + 0x10000 * a;
  5730. }
  5731. /**
  5732. * Register (RVU_PF_BAR0) nix#_af_sqm_dbg_ctl_status
  5733. *
  5734. * NIX AF SQM Debug Register This register is for SQM diagnostic use
  5735. * only.
  5736. */
  5737. union nixx_af_sqm_dbg_ctl_status {
  5738. u64 u;
  5739. struct nixx_af_sqm_dbg_ctl_status_s {
  5740. u64 tm1 : 8;
  5741. u64 tm2 : 1;
  5742. u64 tm3 : 4;
  5743. u64 tm4 : 1;
  5744. u64 tm5 : 1;
  5745. u64 tm6 : 1;
  5746. u64 tm7 : 4;
  5747. u64 tm8 : 1;
  5748. u64 tm9 : 1;
  5749. u64 tm10 : 1;
  5750. u64 tm11 : 1;
  5751. u64 tm12 : 1;
  5752. u64 tm13 : 1;
  5753. u64 reserved_26_63 : 38;
  5754. } s;
  5755. struct nixx_af_sqm_dbg_ctl_status_cn96xxp1 {
  5756. u64 tm1 : 8;
  5757. u64 tm2 : 1;
  5758. u64 tm3 : 4;
  5759. u64 tm4 : 1;
  5760. u64 tm5 : 1;
  5761. u64 tm6 : 1;
  5762. u64 tm7 : 4;
  5763. u64 tm8 : 1;
  5764. u64 tm9 : 1;
  5765. u64 reserved_22_63 : 42;
  5766. } cn96xxp1;
  5767. /* struct nixx_af_sqm_dbg_ctl_status_s cn96xxp3; */
  5768. /* struct nixx_af_sqm_dbg_ctl_status_cn96xxp1 cnf95xxp1; */
  5769. struct nixx_af_sqm_dbg_ctl_status_cnf95xxp2 {
  5770. u64 tm1 : 8;
  5771. u64 tm2 : 1;
  5772. u64 tm3 : 4;
  5773. u64 tm4 : 1;
  5774. u64 tm5 : 1;
  5775. u64 tm6 : 1;
  5776. u64 tm7 : 4;
  5777. u64 tm8 : 1;
  5778. u64 tm9 : 1;
  5779. u64 reserved_22 : 1;
  5780. u64 reserved_23 : 1;
  5781. u64 reserved_24 : 1;
  5782. u64 reserved_25 : 1;
  5783. u64 reserved_26_63 : 38;
  5784. } cnf95xxp2;
  5785. };
  5786. static inline u64 NIXX_AF_SQM_DBG_CTL_STATUS(void)
  5787. __attribute__ ((pure, always_inline));
  5788. static inline u64 NIXX_AF_SQM_DBG_CTL_STATUS(void)
  5789. {
  5790. return 0x750;
  5791. }
  5792. /**
  5793. * Register (RVU_PF_BAR0) nix#_af_sqm_eco
  5794. *
  5795. * INTERNAL: AF SQM ECO Register
  5796. */
  5797. union nixx_af_sqm_eco {
  5798. u64 u;
  5799. struct nixx_af_sqm_eco_s {
  5800. u64 eco_rw : 64;
  5801. } s;
  5802. /* struct nixx_af_sqm_eco_s cn; */
  5803. };
  5804. static inline u64 NIXX_AF_SQM_ECO(void)
  5805. __attribute__ ((pure, always_inline));
  5806. static inline u64 NIXX_AF_SQM_ECO(void)
  5807. {
  5808. return 0x5b0;
  5809. }
  5810. /**
  5811. * Register (RVU_PF_BAR0) nix#_af_status
  5812. *
  5813. * NIX AF General Status Register
  5814. */
  5815. union nixx_af_status {
  5816. u64 u;
  5817. struct nixx_af_status_s {
  5818. u64 blk_busy : 10;
  5819. u64 calibrate_done : 1;
  5820. u64 reserved_11_15 : 5;
  5821. u64 calibrate_status : 15;
  5822. u64 reserved_31_63 : 33;
  5823. } s;
  5824. /* struct nixx_af_status_s cn; */
  5825. };
  5826. static inline u64 NIXX_AF_STATUS(void)
  5827. __attribute__ ((pure, always_inline));
  5828. static inline u64 NIXX_AF_STATUS(void)
  5829. {
  5830. return 0x10;
  5831. }
  5832. /**
  5833. * Register (RVU_PF_BAR0) nix#_af_tcp_timer
  5834. *
  5835. * NIX TCP Timer Register
  5836. */
  5837. union nixx_af_tcp_timer {
  5838. u64 u;
  5839. struct nixx_af_tcp_timer_s {
  5840. u64 dur_counter : 16;
  5841. u64 lf_counter : 8;
  5842. u64 reserved_24_31 : 8;
  5843. u64 duration : 16;
  5844. u64 reserved_48_62 : 15;
  5845. u64 ena : 1;
  5846. } s;
  5847. /* struct nixx_af_tcp_timer_s cn; */
  5848. };
  5849. static inline u64 NIXX_AF_TCP_TIMER(void)
  5850. __attribute__ ((pure, always_inline));
  5851. static inline u64 NIXX_AF_TCP_TIMER(void)
  5852. {
  5853. return 0x1e0;
  5854. }
  5855. /**
  5856. * Register (RVU_PF_BAR0) nix#_af_tl1#_cir
  5857. *
  5858. * NIX AF Transmit Level 1 Committed Information Rate Register
  5859. */
  5860. union nixx_af_tl1x_cir {
  5861. u64 u;
  5862. struct nixx_af_tl1x_cir_s {
  5863. u64 enable : 1;
  5864. u64 rate_mantissa : 8;
  5865. u64 rate_exponent : 4;
  5866. u64 rate_divider_exponent : 4;
  5867. u64 reserved_17_28 : 12;
  5868. u64 burst_mantissa : 8;
  5869. u64 burst_exponent : 4;
  5870. u64 reserved_41_63 : 23;
  5871. } s;
  5872. /* struct nixx_af_tl1x_cir_s cn; */
  5873. };
  5874. static inline u64 NIXX_AF_TL1X_CIR(u64 a)
  5875. __attribute__ ((pure, always_inline));
  5876. static inline u64 NIXX_AF_TL1X_CIR(u64 a)
  5877. {
  5878. return 0xc20 + 0x10000 * a;
  5879. }
  5880. /**
  5881. * Register (RVU_PF_BAR0) nix#_af_tl1#_dropped_bytes
  5882. *
  5883. * NIX AF Transmit Level 1 Dropped Bytes Registers This register has the
  5884. * same bit fields as NIX_AF_TL1()_GREEN_BYTES.
  5885. */
  5886. union nixx_af_tl1x_dropped_bytes {
  5887. u64 u;
  5888. struct nixx_af_tl1x_dropped_bytes_s {
  5889. u64 count : 48;
  5890. u64 reserved_48_63 : 16;
  5891. } s;
  5892. /* struct nixx_af_tl1x_dropped_bytes_s cn; */
  5893. };
  5894. static inline u64 NIXX_AF_TL1X_DROPPED_BYTES(u64 a)
  5895. __attribute__ ((pure, always_inline));
  5896. static inline u64 NIXX_AF_TL1X_DROPPED_BYTES(u64 a)
  5897. {
  5898. return 0xd30 + 0x10000 * a;
  5899. }
  5900. /**
  5901. * Register (RVU_PF_BAR0) nix#_af_tl1#_dropped_packets
  5902. *
  5903. * NIX AF Transmit Level 1 Dropped Packets Registers This register has
  5904. * the same bit fields as NIX_AF_TL1()_GREEN_PACKETS.
  5905. */
  5906. union nixx_af_tl1x_dropped_packets {
  5907. u64 u;
  5908. struct nixx_af_tl1x_dropped_packets_s {
  5909. u64 count : 40;
  5910. u64 reserved_40_63 : 24;
  5911. } s;
  5912. /* struct nixx_af_tl1x_dropped_packets_s cn; */
  5913. };
  5914. static inline u64 NIXX_AF_TL1X_DROPPED_PACKETS(u64 a)
  5915. __attribute__ ((pure, always_inline));
  5916. static inline u64 NIXX_AF_TL1X_DROPPED_PACKETS(u64 a)
  5917. {
  5918. return 0xd20 + 0x10000 * a;
  5919. }
  5920. /**
  5921. * Register (RVU_PF_BAR0) nix#_af_tl1#_green
  5922. *
  5923. * INTERNAL: NIX Transmit Level 1 Green State Debug Register
  5924. */
  5925. union nixx_af_tl1x_green {
  5926. u64 u;
  5927. struct nixx_af_tl1x_green_s {
  5928. u64 tail : 8;
  5929. u64 reserved_8_9 : 2;
  5930. u64 head : 8;
  5931. u64 reserved_18_19 : 2;
  5932. u64 active_vec : 20;
  5933. u64 rr_active : 1;
  5934. u64 reserved_41_63 : 23;
  5935. } s;
  5936. /* struct nixx_af_tl1x_green_s cn; */
  5937. };
  5938. static inline u64 NIXX_AF_TL1X_GREEN(u64 a)
  5939. __attribute__ ((pure, always_inline));
  5940. static inline u64 NIXX_AF_TL1X_GREEN(u64 a)
  5941. {
  5942. return 0xc90 + 0x10000 * a;
  5943. }
  5944. /**
  5945. * Register (RVU_PF_BAR0) nix#_af_tl1#_green_bytes
  5946. *
  5947. * NIX AF Transmit Level 1 Green Sent Bytes Registers
  5948. */
  5949. union nixx_af_tl1x_green_bytes {
  5950. u64 u;
  5951. struct nixx_af_tl1x_green_bytes_s {
  5952. u64 count : 48;
  5953. u64 reserved_48_63 : 16;
  5954. } s;
  5955. /* struct nixx_af_tl1x_green_bytes_s cn; */
  5956. };
  5957. static inline u64 NIXX_AF_TL1X_GREEN_BYTES(u64 a)
  5958. __attribute__ ((pure, always_inline));
  5959. static inline u64 NIXX_AF_TL1X_GREEN_BYTES(u64 a)
  5960. {
  5961. return 0xd90 + 0x10000 * a;
  5962. }
  5963. /**
  5964. * Register (RVU_PF_BAR0) nix#_af_tl1#_green_packets
  5965. *
  5966. * NIX AF Transmit Level 1 Green Sent Packets Registers
  5967. */
  5968. union nixx_af_tl1x_green_packets {
  5969. u64 u;
  5970. struct nixx_af_tl1x_green_packets_s {
  5971. u64 count : 40;
  5972. u64 reserved_40_63 : 24;
  5973. } s;
  5974. /* struct nixx_af_tl1x_green_packets_s cn; */
  5975. };
  5976. static inline u64 NIXX_AF_TL1X_GREEN_PACKETS(u64 a)
  5977. __attribute__ ((pure, always_inline));
  5978. static inline u64 NIXX_AF_TL1X_GREEN_PACKETS(u64 a)
  5979. {
  5980. return 0xd80 + 0x10000 * a;
  5981. }
  5982. /**
  5983. * Register (RVU_PF_BAR0) nix#_af_tl1#_md_debug0
  5984. *
  5985. * NIX AF Transmit Level 1 Meta Descriptor Debug 0 Registers
  5986. * NIX_AF_TL1()_MD_DEBUG0, NIX_AF_TL1()_MD_DEBUG1, NIX_AF_TL1()_MD_DEBUG2
  5987. * and NIX_AF_TL1()_MD_DEBUG3 provide access to the TLn queue meta
  5988. * descriptor. A TLn queue can hold up to two packet meta descriptors
  5989. * (PMD) and one flush meta descriptor (FMD): * PMD0 state is accessed
  5990. * with [PMD0_VLD], [PMD0_LENGTH] and NIX_AF_TL1()_MD_DEBUG1. * PMD1 is
  5991. * accessed with [PMD1_VLD], [PMD1_LENGTH] and NIX_AF_TL1()_MD_DEBUG2. *
  5992. * FMD is accessed with NIX_AF_TL1()_MD_DEBUG3.
  5993. */
  5994. union nixx_af_tl1x_md_debug0 {
  5995. u64 u;
  5996. struct nixx_af_tl1x_md_debug0_s {
  5997. u64 pmd0_length : 16;
  5998. u64 pmd1_length : 16;
  5999. u64 pmd0_vld : 1;
  6000. u64 pmd1_vld : 1;
  6001. u64 reserved_34_45 : 12;
  6002. u64 drain_pri : 1;
  6003. u64 drain : 1;
  6004. u64 c_con : 1;
  6005. u64 p_con : 1;
  6006. u64 reserved_50_51 : 2;
  6007. u64 child : 10;
  6008. u64 reserved_62 : 1;
  6009. u64 pmd_count : 1;
  6010. } s;
  6011. /* struct nixx_af_tl1x_md_debug0_s cn96xxp1; */
  6012. struct nixx_af_tl1x_md_debug0_cn96xxp3 {
  6013. u64 pmd0_length : 16;
  6014. u64 reserved_16_31 : 16;
  6015. u64 pmd0_vld : 1;
  6016. u64 reserved_33 : 1;
  6017. u64 reserved_34_45 : 12;
  6018. u64 reserved_46 : 1;
  6019. u64 reserved_47 : 1;
  6020. u64 c_con : 1;
  6021. u64 p_con : 1;
  6022. u64 reserved_50_51 : 2;
  6023. u64 child : 10;
  6024. u64 reserved_62 : 1;
  6025. u64 reserved_63 : 1;
  6026. } cn96xxp3;
  6027. /* struct nixx_af_tl1x_md_debug0_s cnf95xx; */
  6028. };
  6029. static inline u64 NIXX_AF_TL1X_MD_DEBUG0(u64 a)
  6030. __attribute__ ((pure, always_inline));
  6031. static inline u64 NIXX_AF_TL1X_MD_DEBUG0(u64 a)
  6032. {
  6033. return 0xcc0 + 0x10000 * a;
  6034. }
  6035. /**
  6036. * Register (RVU_PF_BAR0) nix#_af_tl1#_md_debug1
  6037. *
  6038. * NIX AF Transmit Level 1 Meta Descriptor Debug 1 Registers Packet meta
  6039. * descriptor 0 debug. See NIX_AF_TL1()_MD_DEBUG0.
  6040. */
  6041. union nixx_af_tl1x_md_debug1 {
  6042. u64 u;
  6043. struct nixx_af_tl1x_md_debug1_s {
  6044. u64 reserved_0_5 : 6;
  6045. u64 red_algo_override : 2;
  6046. u64 cir_dis : 1;
  6047. u64 pir_dis : 1;
  6048. u64 adjust : 9;
  6049. u64 uid : 4;
  6050. u64 reserved_23 : 1;
  6051. u64 bubble : 1;
  6052. u64 color : 2;
  6053. u64 pse_pkt_id : 9;
  6054. u64 reserved_36 : 1;
  6055. u64 tx_pkt_p2x : 2;
  6056. u64 sqm_pkt_id : 13;
  6057. u64 mdq_idx : 10;
  6058. u64 reserved_62 : 1;
  6059. u64 vld : 1;
  6060. } s;
  6061. struct nixx_af_tl1x_md_debug1_cn96xxp1 {
  6062. u64 reserved_0_5 : 6;
  6063. u64 red_algo_override : 2;
  6064. u64 cir_dis : 1;
  6065. u64 pir_dis : 1;
  6066. u64 adjust : 9;
  6067. u64 uid : 4;
  6068. u64 drain : 1;
  6069. u64 bubble : 1;
  6070. u64 color : 2;
  6071. u64 pse_pkt_id : 9;
  6072. u64 reserved_36 : 1;
  6073. u64 tx_pkt_p2x : 2;
  6074. u64 sqm_pkt_id : 13;
  6075. u64 mdq_idx : 10;
  6076. u64 reserved_62 : 1;
  6077. u64 vld : 1;
  6078. } cn96xxp1;
  6079. struct nixx_af_tl1x_md_debug1_cn96xxp3 {
  6080. u64 reserved_0_5 : 6;
  6081. u64 red_algo_override : 2;
  6082. u64 cir_dis : 1;
  6083. u64 pir_dis : 1;
  6084. u64 adjust : 9;
  6085. u64 reserved_19_22 : 4;
  6086. u64 flush : 1;
  6087. u64 bubble : 1;
  6088. u64 color : 2;
  6089. u64 pse_pkt_id : 9;
  6090. u64 reserved_36 : 1;
  6091. u64 tx_pkt_p2x : 2;
  6092. u64 sqm_pkt_id : 13;
  6093. u64 mdq_idx : 10;
  6094. u64 reserved_62 : 1;
  6095. u64 vld : 1;
  6096. } cn96xxp3;
  6097. /* struct nixx_af_tl1x_md_debug1_cn96xxp1 cnf95xx; */
  6098. };
  6099. static inline u64 NIXX_AF_TL1X_MD_DEBUG1(u64 a)
  6100. __attribute__ ((pure, always_inline));
  6101. static inline u64 NIXX_AF_TL1X_MD_DEBUG1(u64 a)
  6102. {
  6103. return 0xcc8 + 0x10000 * a;
  6104. }
  6105. /**
  6106. * Register (RVU_PF_BAR0) nix#_af_tl1#_md_debug2
  6107. *
  6108. * NIX AF Transmit Level 1 Meta Descriptor Debug 2 Registers Packet meta
  6109. * descriptor 1 debug. See NIX_AF_TL1()_MD_DEBUG0.
  6110. */
  6111. union nixx_af_tl1x_md_debug2 {
  6112. u64 u;
  6113. struct nixx_af_tl1x_md_debug2_s {
  6114. u64 reserved_0_5 : 6;
  6115. u64 red_algo_override : 2;
  6116. u64 cir_dis : 1;
  6117. u64 pir_dis : 1;
  6118. u64 adjust : 9;
  6119. u64 uid : 4;
  6120. u64 reserved_23 : 1;
  6121. u64 bubble : 1;
  6122. u64 color : 2;
  6123. u64 pse_pkt_id : 9;
  6124. u64 reserved_36 : 1;
  6125. u64 tx_pkt_p2x : 2;
  6126. u64 sqm_pkt_id : 13;
  6127. u64 mdq_idx : 10;
  6128. u64 reserved_62 : 1;
  6129. u64 vld : 1;
  6130. } s;
  6131. struct nixx_af_tl1x_md_debug2_cn96xxp1 {
  6132. u64 reserved_0_5 : 6;
  6133. u64 red_algo_override : 2;
  6134. u64 cir_dis : 1;
  6135. u64 pir_dis : 1;
  6136. u64 adjust : 9;
  6137. u64 uid : 4;
  6138. u64 drain : 1;
  6139. u64 bubble : 1;
  6140. u64 color : 2;
  6141. u64 pse_pkt_id : 9;
  6142. u64 reserved_36 : 1;
  6143. u64 tx_pkt_p2x : 2;
  6144. u64 sqm_pkt_id : 13;
  6145. u64 mdq_idx : 10;
  6146. u64 reserved_62 : 1;
  6147. u64 vld : 1;
  6148. } cn96xxp1;
  6149. struct nixx_af_tl1x_md_debug2_cn96xxp3 {
  6150. u64 reserved_0_5 : 6;
  6151. u64 red_algo_override : 2;
  6152. u64 cir_dis : 1;
  6153. u64 pir_dis : 1;
  6154. u64 adjust : 9;
  6155. u64 reserved_19_22 : 4;
  6156. u64 flush : 1;
  6157. u64 bubble : 1;
  6158. u64 color : 2;
  6159. u64 pse_pkt_id : 9;
  6160. u64 reserved_36 : 1;
  6161. u64 tx_pkt_p2x : 2;
  6162. u64 sqm_pkt_id : 13;
  6163. u64 mdq_idx : 10;
  6164. u64 reserved_62 : 1;
  6165. u64 vld : 1;
  6166. } cn96xxp3;
  6167. /* struct nixx_af_tl1x_md_debug2_cn96xxp1 cnf95xx; */
  6168. };
  6169. static inline u64 NIXX_AF_TL1X_MD_DEBUG2(u64 a)
  6170. __attribute__ ((pure, always_inline));
  6171. static inline u64 NIXX_AF_TL1X_MD_DEBUG2(u64 a)
  6172. {
  6173. return 0xcd0 + 0x10000 * a;
  6174. }
  6175. /**
  6176. * Register (RVU_PF_BAR0) nix#_af_tl1#_md_debug3
  6177. *
  6178. * NIX AF Transmit Level 1 Meta Descriptor Debug 3 Registers Flush meta
  6179. * descriptor debug. See NIX_AF_TL1()_MD_DEBUG0.
  6180. */
  6181. union nixx_af_tl1x_md_debug3 {
  6182. u64 u;
  6183. struct nixx_af_tl1x_md_debug3_s {
  6184. u64 reserved_0_36 : 37;
  6185. u64 tx_pkt_p2x : 2;
  6186. u64 sqm_pkt_id : 13;
  6187. u64 mdq_idx : 10;
  6188. u64 reserved_62 : 1;
  6189. u64 vld : 1;
  6190. } s;
  6191. /* struct nixx_af_tl1x_md_debug3_s cn96xxp1; */
  6192. struct nixx_af_tl1x_md_debug3_cn96xxp3 {
  6193. u64 reserved_0_36 : 37;
  6194. u64 reserved_37_38 : 2;
  6195. u64 reserved_39_51 : 13;
  6196. u64 reserved_52_61 : 10;
  6197. u64 reserved_62 : 1;
  6198. u64 reserved_63 : 1;
  6199. } cn96xxp3;
  6200. /* struct nixx_af_tl1x_md_debug3_s cnf95xx; */
  6201. };
  6202. static inline u64 NIXX_AF_TL1X_MD_DEBUG3(u64 a)
  6203. __attribute__ ((pure, always_inline));
  6204. static inline u64 NIXX_AF_TL1X_MD_DEBUG3(u64 a)
  6205. {
  6206. return 0xcd8 + 0x10000 * a;
  6207. }
  6208. /**
  6209. * Register (RVU_PF_BAR0) nix#_af_tl1#_red
  6210. *
  6211. * INTERNAL: NIX Transmit Level 1 Red State Debug Register This register
  6212. * has the same bit fields as NIX_AF_TL1()_YELLOW.
  6213. */
  6214. union nixx_af_tl1x_red {
  6215. u64 u;
  6216. struct nixx_af_tl1x_red_s {
  6217. u64 tail : 8;
  6218. u64 reserved_8_9 : 2;
  6219. u64 head : 8;
  6220. u64 reserved_18_63 : 46;
  6221. } s;
  6222. /* struct nixx_af_tl1x_red_s cn; */
  6223. };
  6224. static inline u64 NIXX_AF_TL1X_RED(u64 a)
  6225. __attribute__ ((pure, always_inline));
  6226. static inline u64 NIXX_AF_TL1X_RED(u64 a)
  6227. {
  6228. return 0xcb0 + 0x10000 * a;
  6229. }
  6230. /**
  6231. * Register (RVU_PF_BAR0) nix#_af_tl1#_red_bytes
  6232. *
  6233. * NIX AF Transmit Level 1 Red Sent Bytes Registers This register has the
  6234. * same bit fields as NIX_AF_TL1()_GREEN_BYTES.
  6235. */
  6236. union nixx_af_tl1x_red_bytes {
  6237. u64 u;
  6238. struct nixx_af_tl1x_red_bytes_s {
  6239. u64 count : 48;
  6240. u64 reserved_48_63 : 16;
  6241. } s;
  6242. /* struct nixx_af_tl1x_red_bytes_s cn; */
  6243. };
  6244. static inline u64 NIXX_AF_TL1X_RED_BYTES(u64 a)
  6245. __attribute__ ((pure, always_inline));
  6246. static inline u64 NIXX_AF_TL1X_RED_BYTES(u64 a)
  6247. {
  6248. return 0xd50 + 0x10000 * a;
  6249. }
  6250. /**
  6251. * Register (RVU_PF_BAR0) nix#_af_tl1#_red_packets
  6252. *
  6253. * NIX AF Transmit Level 1 Red Sent Packets Registers This register has
  6254. * the same bit fields as NIX_AF_TL1()_GREEN_PACKETS.
  6255. */
  6256. union nixx_af_tl1x_red_packets {
  6257. u64 u;
  6258. struct nixx_af_tl1x_red_packets_s {
  6259. u64 count : 40;
  6260. u64 reserved_40_63 : 24;
  6261. } s;
  6262. /* struct nixx_af_tl1x_red_packets_s cn; */
  6263. };
  6264. static inline u64 NIXX_AF_TL1X_RED_PACKETS(u64 a)
  6265. __attribute__ ((pure, always_inline));
  6266. static inline u64 NIXX_AF_TL1X_RED_PACKETS(u64 a)
  6267. {
  6268. return 0xd40 + 0x10000 * a;
  6269. }
  6270. /**
  6271. * Register (RVU_PF_BAR0) nix#_af_tl1#_schedule
  6272. *
  6273. * NIX AF Transmit Level 1 Scheduling Control Register
  6274. */
  6275. union nixx_af_tl1x_schedule {
  6276. u64 u;
  6277. struct nixx_af_tl1x_schedule_s {
  6278. u64 rr_quantum : 24;
  6279. u64 reserved_24_63 : 40;
  6280. } s;
  6281. /* struct nixx_af_tl1x_schedule_s cn; */
  6282. };
  6283. static inline u64 NIXX_AF_TL1X_SCHEDULE(u64 a)
  6284. __attribute__ ((pure, always_inline));
  6285. static inline u64 NIXX_AF_TL1X_SCHEDULE(u64 a)
  6286. {
  6287. return 0xc00 + 0x10000 * a;
  6288. }
  6289. /**
  6290. * Register (RVU_PF_BAR0) nix#_af_tl1#_shape
  6291. *
  6292. * NIX AF Transmit Level 1 Shaping Control Register
  6293. */
  6294. union nixx_af_tl1x_shape {
  6295. u64 u;
  6296. struct nixx_af_tl1x_shape_s {
  6297. u64 adjust : 9;
  6298. u64 reserved_9_23 : 15;
  6299. u64 length_disable : 1;
  6300. u64 reserved_25_63 : 39;
  6301. } s;
  6302. struct nixx_af_tl1x_shape_cn {
  6303. u64 adjust : 9;
  6304. u64 reserved_9_17 : 9;
  6305. u64 reserved_18_23 : 6;
  6306. u64 length_disable : 1;
  6307. u64 reserved_25_63 : 39;
  6308. } cn;
  6309. };
  6310. static inline u64 NIXX_AF_TL1X_SHAPE(u64 a)
  6311. __attribute__ ((pure, always_inline));
  6312. static inline u64 NIXX_AF_TL1X_SHAPE(u64 a)
  6313. {
  6314. return 0xc10 + 0x10000 * a;
  6315. }
  6316. /**
  6317. * Register (RVU_PF_BAR0) nix#_af_tl1#_shape_state
  6318. *
  6319. * NIX AF Transmit Level 1 Shape State Register This register must not be
  6320. * written during normal operation.
  6321. */
  6322. union nixx_af_tl1x_shape_state {
  6323. u64 u;
  6324. struct nixx_af_tl1x_shape_state_s {
  6325. u64 cir_accum : 26;
  6326. u64 reserved_26_51 : 26;
  6327. u64 color : 1;
  6328. u64 reserved_53_63 : 11;
  6329. } s;
  6330. /* struct nixx_af_tl1x_shape_state_s cn; */
  6331. };
  6332. static inline u64 NIXX_AF_TL1X_SHAPE_STATE(u64 a)
  6333. __attribute__ ((pure, always_inline));
  6334. static inline u64 NIXX_AF_TL1X_SHAPE_STATE(u64 a)
  6335. {
  6336. return 0xc50 + 0x10000 * a;
  6337. }
  6338. /**
  6339. * Register (RVU_PF_BAR0) nix#_af_tl1#_sw_xoff
  6340. *
  6341. * NIX AF Transmit Level 1 Software Controlled XOFF Registers
  6342. */
  6343. union nixx_af_tl1x_sw_xoff {
  6344. u64 u;
  6345. struct nixx_af_tl1x_sw_xoff_s {
  6346. u64 xoff : 1;
  6347. u64 drain : 1;
  6348. u64 reserved_2 : 1;
  6349. u64 drain_irq : 1;
  6350. u64 reserved_4_63 : 60;
  6351. } s;
  6352. /* struct nixx_af_tl1x_sw_xoff_s cn; */
  6353. };
  6354. static inline u64 NIXX_AF_TL1X_SW_XOFF(u64 a)
  6355. __attribute__ ((pure, always_inline));
  6356. static inline u64 NIXX_AF_TL1X_SW_XOFF(u64 a)
  6357. {
  6358. return 0xc70 + 0x10000 * a;
  6359. }
  6360. /**
  6361. * Register (RVU_PF_BAR0) nix#_af_tl1#_topology
  6362. *
  6363. * NIX AF Transmit Level 1 Topology Registers
  6364. */
  6365. union nixx_af_tl1x_topology {
  6366. u64 u;
  6367. struct nixx_af_tl1x_topology_s {
  6368. u64 reserved_0 : 1;
  6369. u64 rr_prio : 4;
  6370. u64 reserved_5_31 : 27;
  6371. u64 prio_anchor : 8;
  6372. u64 reserved_40_63 : 24;
  6373. } s;
  6374. /* struct nixx_af_tl1x_topology_s cn; */
  6375. };
  6376. static inline u64 NIXX_AF_TL1X_TOPOLOGY(u64 a)
  6377. __attribute__ ((pure, always_inline));
  6378. static inline u64 NIXX_AF_TL1X_TOPOLOGY(u64 a)
  6379. {
  6380. return 0xc80 + 0x10000 * a;
  6381. }
  6382. /**
  6383. * Register (RVU_PF_BAR0) nix#_af_tl1#_yellow
  6384. *
  6385. * INTERNAL: NIX Transmit Level 1 Yellow State Debug Register
  6386. */
  6387. union nixx_af_tl1x_yellow {
  6388. u64 u;
  6389. struct nixx_af_tl1x_yellow_s {
  6390. u64 tail : 8;
  6391. u64 reserved_8_9 : 2;
  6392. u64 head : 8;
  6393. u64 reserved_18_63 : 46;
  6394. } s;
  6395. /* struct nixx_af_tl1x_yellow_s cn; */
  6396. };
  6397. static inline u64 NIXX_AF_TL1X_YELLOW(u64 a)
  6398. __attribute__ ((pure, always_inline));
  6399. static inline u64 NIXX_AF_TL1X_YELLOW(u64 a)
  6400. {
  6401. return 0xca0 + 0x10000 * a;
  6402. }
  6403. /**
  6404. * Register (RVU_PF_BAR0) nix#_af_tl1#_yellow_bytes
  6405. *
  6406. * NIX AF Transmit Level 1 Yellow Sent Bytes Registers This register has
  6407. * the same bit fields as NIX_AF_TL1()_GREEN_BYTES.
  6408. */
  6409. union nixx_af_tl1x_yellow_bytes {
  6410. u64 u;
  6411. struct nixx_af_tl1x_yellow_bytes_s {
  6412. u64 count : 48;
  6413. u64 reserved_48_63 : 16;
  6414. } s;
  6415. /* struct nixx_af_tl1x_yellow_bytes_s cn; */
  6416. };
  6417. static inline u64 NIXX_AF_TL1X_YELLOW_BYTES(u64 a)
  6418. __attribute__ ((pure, always_inline));
  6419. static inline u64 NIXX_AF_TL1X_YELLOW_BYTES(u64 a)
  6420. {
  6421. return 0xd70 + 0x10000 * a;
  6422. }
  6423. /**
  6424. * Register (RVU_PF_BAR0) nix#_af_tl1#_yellow_packets
  6425. *
  6426. * NIX AF Transmit Level 1 Yellow Sent Packets Registers This register
  6427. * has the same bit fields as NIX_AF_TL1()_GREEN_PACKETS.
  6428. */
  6429. union nixx_af_tl1x_yellow_packets {
  6430. u64 u;
  6431. struct nixx_af_tl1x_yellow_packets_s {
  6432. u64 count : 40;
  6433. u64 reserved_40_63 : 24;
  6434. } s;
  6435. /* struct nixx_af_tl1x_yellow_packets_s cn; */
  6436. };
  6437. static inline u64 NIXX_AF_TL1X_YELLOW_PACKETS(u64 a)
  6438. __attribute__ ((pure, always_inline));
  6439. static inline u64 NIXX_AF_TL1X_YELLOW_PACKETS(u64 a)
  6440. {
  6441. return 0xd60 + 0x10000 * a;
  6442. }
  6443. /**
  6444. * Register (RVU_PF_BAR0) nix#_af_tl1_const
  6445. *
  6446. * NIX AF Transmit Level 1 Constants Register This register contains
  6447. * constants for software discovery.
  6448. */
  6449. union nixx_af_tl1_const {
  6450. u64 u;
  6451. struct nixx_af_tl1_const_s {
  6452. u64 count : 16;
  6453. u64 reserved_16_63 : 48;
  6454. } s;
  6455. /* struct nixx_af_tl1_const_s cn; */
  6456. };
  6457. static inline u64 NIXX_AF_TL1_CONST(void)
  6458. __attribute__ ((pure, always_inline));
  6459. static inline u64 NIXX_AF_TL1_CONST(void)
  6460. {
  6461. return 0x70;
  6462. }
  6463. /**
  6464. * Register (RVU_PF_BAR0) nix#_af_tl2#_cir
  6465. *
  6466. * NIX AF Transmit Level 2 Committed Information Rate Registers This
  6467. * register has the same bit fields as NIX_AF_TL1()_CIR.
  6468. */
  6469. union nixx_af_tl2x_cir {
  6470. u64 u;
  6471. struct nixx_af_tl2x_cir_s {
  6472. u64 enable : 1;
  6473. u64 rate_mantissa : 8;
  6474. u64 rate_exponent : 4;
  6475. u64 rate_divider_exponent : 4;
  6476. u64 reserved_17_28 : 12;
  6477. u64 burst_mantissa : 8;
  6478. u64 burst_exponent : 4;
  6479. u64 reserved_41_63 : 23;
  6480. } s;
  6481. /* struct nixx_af_tl2x_cir_s cn; */
  6482. };
  6483. static inline u64 NIXX_AF_TL2X_CIR(u64 a)
  6484. __attribute__ ((pure, always_inline));
  6485. static inline u64 NIXX_AF_TL2X_CIR(u64 a)
  6486. {
  6487. return 0xe20 + 0x10000 * a;
  6488. }
  6489. /**
  6490. * Register (RVU_PF_BAR0) nix#_af_tl2#_green
  6491. *
  6492. * INTERNAL: NIX Transmit Level 2 Green State Debug Register This
  6493. * register has the same bit fields as NIX_AF_TL1()_GREEN.
  6494. */
  6495. union nixx_af_tl2x_green {
  6496. u64 u;
  6497. struct nixx_af_tl2x_green_s {
  6498. u64 tail : 8;
  6499. u64 reserved_8_9 : 2;
  6500. u64 head : 8;
  6501. u64 reserved_18_19 : 2;
  6502. u64 active_vec : 20;
  6503. u64 rr_active : 1;
  6504. u64 reserved_41_63 : 23;
  6505. } s;
  6506. /* struct nixx_af_tl2x_green_s cn; */
  6507. };
  6508. static inline u64 NIXX_AF_TL2X_GREEN(u64 a)
  6509. __attribute__ ((pure, always_inline));
  6510. static inline u64 NIXX_AF_TL2X_GREEN(u64 a)
  6511. {
  6512. return 0xe90 + 0x10000 * a;
  6513. }
  6514. /**
  6515. * Register (RVU_PF_BAR0) nix#_af_tl2#_md_debug0
  6516. *
  6517. * NIX AF Transmit Level 2 Meta Descriptor Debug 0 Registers See
  6518. * NIX_AF_TL1()_MD_DEBUG0
  6519. */
  6520. union nixx_af_tl2x_md_debug0 {
  6521. u64 u;
  6522. struct nixx_af_tl2x_md_debug0_s {
  6523. u64 pmd0_length : 16;
  6524. u64 pmd1_length : 16;
  6525. u64 pmd0_vld : 1;
  6526. u64 pmd1_vld : 1;
  6527. u64 reserved_34_45 : 12;
  6528. u64 drain_pri : 1;
  6529. u64 drain : 1;
  6530. u64 c_con : 1;
  6531. u64 p_con : 1;
  6532. u64 reserved_50_51 : 2;
  6533. u64 child : 10;
  6534. u64 reserved_62 : 1;
  6535. u64 pmd_count : 1;
  6536. } s;
  6537. /* struct nixx_af_tl2x_md_debug0_s cn96xxp1; */
  6538. struct nixx_af_tl2x_md_debug0_cn96xxp3 {
  6539. u64 pmd0_length : 16;
  6540. u64 reserved_16_31 : 16;
  6541. u64 pmd0_vld : 1;
  6542. u64 reserved_33 : 1;
  6543. u64 reserved_34_45 : 12;
  6544. u64 reserved_46 : 1;
  6545. u64 reserved_47 : 1;
  6546. u64 c_con : 1;
  6547. u64 p_con : 1;
  6548. u64 reserved_50_51 : 2;
  6549. u64 child : 10;
  6550. u64 reserved_62 : 1;
  6551. u64 reserved_63 : 1;
  6552. } cn96xxp3;
  6553. /* struct nixx_af_tl2x_md_debug0_s cnf95xx; */
  6554. };
  6555. static inline u64 NIXX_AF_TL2X_MD_DEBUG0(u64 a)
  6556. __attribute__ ((pure, always_inline));
  6557. static inline u64 NIXX_AF_TL2X_MD_DEBUG0(u64 a)
  6558. {
  6559. return 0xec0 + 0x10000 * a;
  6560. }
  6561. /**
  6562. * Register (RVU_PF_BAR0) nix#_af_tl2#_md_debug1
  6563. *
  6564. * NIX AF Transmit Level 2 Meta Descriptor Debug 1 Registers Packet meta
  6565. * descriptor 0 debug. See NIX_AF_TL1()_MD_DEBUG0.
  6566. */
  6567. union nixx_af_tl2x_md_debug1 {
  6568. u64 u;
  6569. struct nixx_af_tl2x_md_debug1_s {
  6570. u64 reserved_0_5 : 6;
  6571. u64 red_algo_override : 2;
  6572. u64 cir_dis : 1;
  6573. u64 pir_dis : 1;
  6574. u64 adjust : 9;
  6575. u64 uid : 4;
  6576. u64 reserved_23 : 1;
  6577. u64 bubble : 1;
  6578. u64 color : 2;
  6579. u64 pse_pkt_id : 9;
  6580. u64 reserved_36 : 1;
  6581. u64 tx_pkt_p2x : 2;
  6582. u64 sqm_pkt_id : 13;
  6583. u64 mdq_idx : 10;
  6584. u64 reserved_62 : 1;
  6585. u64 vld : 1;
  6586. } s;
  6587. struct nixx_af_tl2x_md_debug1_cn96xxp1 {
  6588. u64 reserved_0_5 : 6;
  6589. u64 red_algo_override : 2;
  6590. u64 cir_dis : 1;
  6591. u64 pir_dis : 1;
  6592. u64 adjust : 9;
  6593. u64 uid : 4;
  6594. u64 drain : 1;
  6595. u64 bubble : 1;
  6596. u64 color : 2;
  6597. u64 pse_pkt_id : 9;
  6598. u64 reserved_36 : 1;
  6599. u64 tx_pkt_p2x : 2;
  6600. u64 sqm_pkt_id : 13;
  6601. u64 mdq_idx : 10;
  6602. u64 reserved_62 : 1;
  6603. u64 vld : 1;
  6604. } cn96xxp1;
  6605. struct nixx_af_tl2x_md_debug1_cn96xxp3 {
  6606. u64 reserved_0_5 : 6;
  6607. u64 red_algo_override : 2;
  6608. u64 cir_dis : 1;
  6609. u64 pir_dis : 1;
  6610. u64 adjust : 9;
  6611. u64 reserved_19_22 : 4;
  6612. u64 flush : 1;
  6613. u64 bubble : 1;
  6614. u64 color : 2;
  6615. u64 pse_pkt_id : 9;
  6616. u64 reserved_36 : 1;
  6617. u64 tx_pkt_p2x : 2;
  6618. u64 sqm_pkt_id : 13;
  6619. u64 mdq_idx : 10;
  6620. u64 reserved_62 : 1;
  6621. u64 vld : 1;
  6622. } cn96xxp3;
  6623. /* struct nixx_af_tl2x_md_debug1_cn96xxp1 cnf95xx; */
  6624. };
  6625. static inline u64 NIXX_AF_TL2X_MD_DEBUG1(u64 a)
  6626. __attribute__ ((pure, always_inline));
  6627. static inline u64 NIXX_AF_TL2X_MD_DEBUG1(u64 a)
  6628. {
  6629. return 0xec8 + 0x10000 * a;
  6630. }
  6631. /**
  6632. * Register (RVU_PF_BAR0) nix#_af_tl2#_md_debug2
  6633. *
  6634. * NIX AF Transmit Level 2 Meta Descriptor Debug 2 Registers Packet meta
  6635. * descriptor 1 debug. See NIX_AF_TL1()_MD_DEBUG0.
  6636. */
  6637. union nixx_af_tl2x_md_debug2 {
  6638. u64 u;
  6639. struct nixx_af_tl2x_md_debug2_s {
  6640. u64 reserved_0_5 : 6;
  6641. u64 red_algo_override : 2;
  6642. u64 cir_dis : 1;
  6643. u64 pir_dis : 1;
  6644. u64 adjust : 9;
  6645. u64 uid : 4;
  6646. u64 reserved_23 : 1;
  6647. u64 bubble : 1;
  6648. u64 color : 2;
  6649. u64 pse_pkt_id : 9;
  6650. u64 reserved_36 : 1;
  6651. u64 tx_pkt_p2x : 2;
  6652. u64 sqm_pkt_id : 13;
  6653. u64 mdq_idx : 10;
  6654. u64 reserved_62 : 1;
  6655. u64 vld : 1;
  6656. } s;
  6657. struct nixx_af_tl2x_md_debug2_cn96xxp1 {
  6658. u64 reserved_0_5 : 6;
  6659. u64 red_algo_override : 2;
  6660. u64 cir_dis : 1;
  6661. u64 pir_dis : 1;
  6662. u64 adjust : 9;
  6663. u64 uid : 4;
  6664. u64 drain : 1;
  6665. u64 bubble : 1;
  6666. u64 color : 2;
  6667. u64 pse_pkt_id : 9;
  6668. u64 reserved_36 : 1;
  6669. u64 tx_pkt_p2x : 2;
  6670. u64 sqm_pkt_id : 13;
  6671. u64 mdq_idx : 10;
  6672. u64 reserved_62 : 1;
  6673. u64 vld : 1;
  6674. } cn96xxp1;
  6675. struct nixx_af_tl2x_md_debug2_cn96xxp3 {
  6676. u64 reserved_0_5 : 6;
  6677. u64 red_algo_override : 2;
  6678. u64 cir_dis : 1;
  6679. u64 pir_dis : 1;
  6680. u64 adjust : 9;
  6681. u64 reserved_19_22 : 4;
  6682. u64 flush : 1;
  6683. u64 bubble : 1;
  6684. u64 color : 2;
  6685. u64 pse_pkt_id : 9;
  6686. u64 reserved_36 : 1;
  6687. u64 tx_pkt_p2x : 2;
  6688. u64 sqm_pkt_id : 13;
  6689. u64 mdq_idx : 10;
  6690. u64 reserved_62 : 1;
  6691. u64 vld : 1;
  6692. } cn96xxp3;
  6693. /* struct nixx_af_tl2x_md_debug2_cn96xxp1 cnf95xx; */
  6694. };
  6695. static inline u64 NIXX_AF_TL2X_MD_DEBUG2(u64 a)
  6696. __attribute__ ((pure, always_inline));
  6697. static inline u64 NIXX_AF_TL2X_MD_DEBUG2(u64 a)
  6698. {
  6699. return 0xed0 + 0x10000 * a;
  6700. }
  6701. /**
  6702. * Register (RVU_PF_BAR0) nix#_af_tl2#_md_debug3
  6703. *
  6704. * NIX AF Transmit Level 2 Meta Descriptor Debug 3 Registers Flush meta
  6705. * descriptor debug. See NIX_AF_TL1()_MD_DEBUG0.
  6706. */
  6707. union nixx_af_tl2x_md_debug3 {
  6708. u64 u;
  6709. struct nixx_af_tl2x_md_debug3_s {
  6710. u64 reserved_0_36 : 37;
  6711. u64 tx_pkt_p2x : 2;
  6712. u64 sqm_pkt_id : 13;
  6713. u64 mdq_idx : 10;
  6714. u64 reserved_62 : 1;
  6715. u64 vld : 1;
  6716. } s;
  6717. /* struct nixx_af_tl2x_md_debug3_s cn96xxp1; */
  6718. struct nixx_af_tl2x_md_debug3_cn96xxp3 {
  6719. u64 reserved_0_36 : 37;
  6720. u64 reserved_37_38 : 2;
  6721. u64 reserved_39_51 : 13;
  6722. u64 reserved_52_61 : 10;
  6723. u64 reserved_62 : 1;
  6724. u64 reserved_63 : 1;
  6725. } cn96xxp3;
  6726. /* struct nixx_af_tl2x_md_debug3_s cnf95xx; */
  6727. };
  6728. static inline u64 NIXX_AF_TL2X_MD_DEBUG3(u64 a)
  6729. __attribute__ ((pure, always_inline));
  6730. static inline u64 NIXX_AF_TL2X_MD_DEBUG3(u64 a)
  6731. {
  6732. return 0xed8 + 0x10000 * a;
  6733. }
  6734. /**
  6735. * Register (RVU_PF_BAR0) nix#_af_tl2#_parent
  6736. *
  6737. * NIX AF Transmit Level 2 Parent Registers
  6738. */
  6739. union nixx_af_tl2x_parent {
  6740. u64 u;
  6741. struct nixx_af_tl2x_parent_s {
  6742. u64 reserved_0_15 : 16;
  6743. u64 parent : 5;
  6744. u64 reserved_21_63 : 43;
  6745. } s;
  6746. /* struct nixx_af_tl2x_parent_s cn; */
  6747. };
  6748. static inline u64 NIXX_AF_TL2X_PARENT(u64 a)
  6749. __attribute__ ((pure, always_inline));
  6750. static inline u64 NIXX_AF_TL2X_PARENT(u64 a)
  6751. {
  6752. return 0xe88 + 0x10000 * a;
  6753. }
  6754. /**
  6755. * Register (RVU_PF_BAR0) nix#_af_tl2#_pir
  6756. *
  6757. * NIX AF Transmit Level 2 Peak Information Rate Registers This register
  6758. * has the same bit fields as NIX_AF_TL1()_CIR.
  6759. */
  6760. union nixx_af_tl2x_pir {
  6761. u64 u;
  6762. struct nixx_af_tl2x_pir_s {
  6763. u64 enable : 1;
  6764. u64 rate_mantissa : 8;
  6765. u64 rate_exponent : 4;
  6766. u64 rate_divider_exponent : 4;
  6767. u64 reserved_17_28 : 12;
  6768. u64 burst_mantissa : 8;
  6769. u64 burst_exponent : 4;
  6770. u64 reserved_41_63 : 23;
  6771. } s;
  6772. /* struct nixx_af_tl2x_pir_s cn; */
  6773. };
  6774. static inline u64 NIXX_AF_TL2X_PIR(u64 a)
  6775. __attribute__ ((pure, always_inline));
  6776. static inline u64 NIXX_AF_TL2X_PIR(u64 a)
  6777. {
  6778. return 0xe30 + 0x10000 * a;
  6779. }
  6780. /**
  6781. * Register (RVU_PF_BAR0) nix#_af_tl2#_pointers
  6782. *
  6783. * INTERNAL: NIX Transmit Level 2 Linked List Pointers Debug Register
  6784. */
  6785. union nixx_af_tl2x_pointers {
  6786. u64 u;
  6787. struct nixx_af_tl2x_pointers_s {
  6788. u64 next : 8;
  6789. u64 reserved_8_15 : 8;
  6790. u64 prev : 8;
  6791. u64 reserved_24_63 : 40;
  6792. } s;
  6793. /* struct nixx_af_tl2x_pointers_s cn; */
  6794. };
  6795. static inline u64 NIXX_AF_TL2X_POINTERS(u64 a)
  6796. __attribute__ ((pure, always_inline));
  6797. static inline u64 NIXX_AF_TL2X_POINTERS(u64 a)
  6798. {
  6799. return 0xe60 + 0x10000 * a;
  6800. }
  6801. /**
  6802. * Register (RVU_PF_BAR0) nix#_af_tl2#_red
  6803. *
  6804. * INTERNAL: NIX Transmit Level 2 Red State Debug Register This register
  6805. * has the same bit fields as NIX_AF_TL1()_RED.
  6806. */
  6807. union nixx_af_tl2x_red {
  6808. u64 u;
  6809. struct nixx_af_tl2x_red_s {
  6810. u64 tail : 8;
  6811. u64 reserved_8_9 : 2;
  6812. u64 head : 8;
  6813. u64 reserved_18_63 : 46;
  6814. } s;
  6815. /* struct nixx_af_tl2x_red_s cn; */
  6816. };
  6817. static inline u64 NIXX_AF_TL2X_RED(u64 a)
  6818. __attribute__ ((pure, always_inline));
  6819. static inline u64 NIXX_AF_TL2X_RED(u64 a)
  6820. {
  6821. return 0xeb0 + 0x10000 * a;
  6822. }
  6823. /**
  6824. * Register (RVU_PF_BAR0) nix#_af_tl2#_sched_state
  6825. *
  6826. * NIX AF Transmit Level 2 Scheduling Control State Registers
  6827. */
  6828. union nixx_af_tl2x_sched_state {
  6829. u64 u;
  6830. struct nixx_af_tl2x_sched_state_s {
  6831. u64 rr_count : 25;
  6832. u64 reserved_25_63 : 39;
  6833. } s;
  6834. /* struct nixx_af_tl2x_sched_state_s cn; */
  6835. };
  6836. static inline u64 NIXX_AF_TL2X_SCHED_STATE(u64 a)
  6837. __attribute__ ((pure, always_inline));
  6838. static inline u64 NIXX_AF_TL2X_SCHED_STATE(u64 a)
  6839. {
  6840. return 0xe40 + 0x10000 * a;
  6841. }
  6842. /**
  6843. * Register (RVU_PF_BAR0) nix#_af_tl2#_schedule
  6844. *
  6845. * NIX AF Transmit Level 2 Scheduling Control Registers
  6846. */
  6847. union nixx_af_tl2x_schedule {
  6848. u64 u;
  6849. struct nixx_af_tl2x_schedule_s {
  6850. u64 rr_quantum : 24;
  6851. u64 prio : 4;
  6852. u64 reserved_28_63 : 36;
  6853. } s;
  6854. /* struct nixx_af_tl2x_schedule_s cn; */
  6855. };
  6856. static inline u64 NIXX_AF_TL2X_SCHEDULE(u64 a)
  6857. __attribute__ ((pure, always_inline));
  6858. static inline u64 NIXX_AF_TL2X_SCHEDULE(u64 a)
  6859. {
  6860. return 0xe00 + 0x10000 * a;
  6861. }
  6862. /**
  6863. * Register (RVU_PF_BAR0) nix#_af_tl2#_shape
  6864. *
  6865. * NIX AF Transmit Level 2 Shaping Control Registers
  6866. */
  6867. union nixx_af_tl2x_shape {
  6868. u64 u;
  6869. struct nixx_af_tl2x_shape_s {
  6870. u64 adjust : 9;
  6871. u64 red_algo : 2;
  6872. u64 red_disable : 1;
  6873. u64 yellow_disable : 1;
  6874. u64 reserved_13_23 : 11;
  6875. u64 length_disable : 1;
  6876. u64 schedule_list : 2;
  6877. u64 reserved_27_63 : 37;
  6878. } s;
  6879. /* struct nixx_af_tl2x_shape_s cn; */
  6880. };
  6881. static inline u64 NIXX_AF_TL2X_SHAPE(u64 a)
  6882. __attribute__ ((pure, always_inline));
  6883. static inline u64 NIXX_AF_TL2X_SHAPE(u64 a)
  6884. {
  6885. return 0xe10 + 0x10000 * a;
  6886. }
  6887. /**
  6888. * Register (RVU_PF_BAR0) nix#_af_tl2#_shape_state
  6889. *
  6890. * NIX AF Transmit Level 2 Shape State Registers This register must not
  6891. * be written during normal operation.
  6892. */
  6893. union nixx_af_tl2x_shape_state {
  6894. u64 u;
  6895. struct nixx_af_tl2x_shape_state_s {
  6896. u64 cir_accum : 26;
  6897. u64 pir_accum : 26;
  6898. u64 color : 2;
  6899. u64 reserved_54_63 : 10;
  6900. } s;
  6901. /* struct nixx_af_tl2x_shape_state_s cn; */
  6902. };
  6903. static inline u64 NIXX_AF_TL2X_SHAPE_STATE(u64 a)
  6904. __attribute__ ((pure, always_inline));
  6905. static inline u64 NIXX_AF_TL2X_SHAPE_STATE(u64 a)
  6906. {
  6907. return 0xe50 + 0x10000 * a;
  6908. }
  6909. /**
  6910. * Register (RVU_PF_BAR0) nix#_af_tl2#_sw_xoff
  6911. *
  6912. * NIX AF Transmit Level 2 Software Controlled XOFF Registers This
  6913. * register has the same bit fields as NIX_AF_TL1()_SW_XOFF.
  6914. */
  6915. union nixx_af_tl2x_sw_xoff {
  6916. u64 u;
  6917. struct nixx_af_tl2x_sw_xoff_s {
  6918. u64 xoff : 1;
  6919. u64 drain : 1;
  6920. u64 reserved_2 : 1;
  6921. u64 drain_irq : 1;
  6922. u64 reserved_4_63 : 60;
  6923. } s;
  6924. /* struct nixx_af_tl2x_sw_xoff_s cn; */
  6925. };
  6926. static inline u64 NIXX_AF_TL2X_SW_XOFF(u64 a)
  6927. __attribute__ ((pure, always_inline));
  6928. static inline u64 NIXX_AF_TL2X_SW_XOFF(u64 a)
  6929. {
  6930. return 0xe70 + 0x10000 * a;
  6931. }
  6932. /**
  6933. * Register (RVU_PF_BAR0) nix#_af_tl2#_topology
  6934. *
  6935. * NIX AF Transmit Level 2 Topology Registers
  6936. */
  6937. union nixx_af_tl2x_topology {
  6938. u64 u;
  6939. struct nixx_af_tl2x_topology_s {
  6940. u64 reserved_0 : 1;
  6941. u64 rr_prio : 4;
  6942. u64 reserved_5_31 : 27;
  6943. u64 prio_anchor : 8;
  6944. u64 reserved_40_63 : 24;
  6945. } s;
  6946. /* struct nixx_af_tl2x_topology_s cn; */
  6947. };
  6948. static inline u64 NIXX_AF_TL2X_TOPOLOGY(u64 a)
  6949. __attribute__ ((pure, always_inline));
  6950. static inline u64 NIXX_AF_TL2X_TOPOLOGY(u64 a)
  6951. {
  6952. return 0xe80 + 0x10000 * a;
  6953. }
  6954. /**
  6955. * Register (RVU_PF_BAR0) nix#_af_tl2#_yellow
  6956. *
  6957. * INTERNAL: NIX Transmit Level 2 Yellow State Debug Register This
  6958. * register has the same bit fields as NIX_AF_TL1()_YELLOW.
  6959. */
  6960. union nixx_af_tl2x_yellow {
  6961. u64 u;
  6962. struct nixx_af_tl2x_yellow_s {
  6963. u64 tail : 8;
  6964. u64 reserved_8_9 : 2;
  6965. u64 head : 8;
  6966. u64 reserved_18_63 : 46;
  6967. } s;
  6968. /* struct nixx_af_tl2x_yellow_s cn; */
  6969. };
  6970. static inline u64 NIXX_AF_TL2X_YELLOW(u64 a)
  6971. __attribute__ ((pure, always_inline));
  6972. static inline u64 NIXX_AF_TL2X_YELLOW(u64 a)
  6973. {
  6974. return 0xea0 + 0x10000 * a;
  6975. }
  6976. /**
  6977. * Register (RVU_PF_BAR0) nix#_af_tl2_const
  6978. *
  6979. * NIX AF Transmit Level 2 Constants Register This register contains
  6980. * constants for software discovery.
  6981. */
  6982. union nixx_af_tl2_const {
  6983. u64 u;
  6984. struct nixx_af_tl2_const_s {
  6985. u64 count : 16;
  6986. u64 reserved_16_63 : 48;
  6987. } s;
  6988. /* struct nixx_af_tl2_const_s cn; */
  6989. };
  6990. static inline u64 NIXX_AF_TL2_CONST(void)
  6991. __attribute__ ((pure, always_inline));
  6992. static inline u64 NIXX_AF_TL2_CONST(void)
  6993. {
  6994. return 0x78;
  6995. }
  6996. /**
  6997. * Register (RVU_PF_BAR0) nix#_af_tl3#_cir
  6998. *
  6999. * NIX AF Transmit Level 3 Committed Information Rate Registers This
  7000. * register has the same bit fields as NIX_AF_TL1()_CIR.
  7001. */
  7002. union nixx_af_tl3x_cir {
  7003. u64 u;
  7004. struct nixx_af_tl3x_cir_s {
  7005. u64 enable : 1;
  7006. u64 rate_mantissa : 8;
  7007. u64 rate_exponent : 4;
  7008. u64 rate_divider_exponent : 4;
  7009. u64 reserved_17_28 : 12;
  7010. u64 burst_mantissa : 8;
  7011. u64 burst_exponent : 4;
  7012. u64 reserved_41_63 : 23;
  7013. } s;
  7014. /* struct nixx_af_tl3x_cir_s cn; */
  7015. };
  7016. static inline u64 NIXX_AF_TL3X_CIR(u64 a)
  7017. __attribute__ ((pure, always_inline));
  7018. static inline u64 NIXX_AF_TL3X_CIR(u64 a)
  7019. {
  7020. return 0x1020 + 0x10000 * a;
  7021. }
  7022. /**
  7023. * Register (RVU_PF_BAR0) nix#_af_tl3#_green
  7024. *
  7025. * INTERNAL: NIX Transmit Level 3 Green State Debug Register
  7026. */
  7027. union nixx_af_tl3x_green {
  7028. u64 u;
  7029. struct nixx_af_tl3x_green_s {
  7030. u64 tail : 9;
  7031. u64 reserved_9 : 1;
  7032. u64 head : 9;
  7033. u64 reserved_19 : 1;
  7034. u64 active_vec : 20;
  7035. u64 rr_active : 1;
  7036. u64 reserved_41_63 : 23;
  7037. } s;
  7038. /* struct nixx_af_tl3x_green_s cn; */
  7039. };
  7040. static inline u64 NIXX_AF_TL3X_GREEN(u64 a)
  7041. __attribute__ ((pure, always_inline));
  7042. static inline u64 NIXX_AF_TL3X_GREEN(u64 a)
  7043. {
  7044. return 0x1090 + 0x10000 * a;
  7045. }
  7046. /**
  7047. * Register (RVU_PF_BAR0) nix#_af_tl3#_md_debug0
  7048. *
  7049. * NIX AF Transmit Level 3 Meta Descriptor Debug 0 Registers See
  7050. * NIX_AF_TL1()_MD_DEBUG0.
  7051. */
  7052. union nixx_af_tl3x_md_debug0 {
  7053. u64 u;
  7054. struct nixx_af_tl3x_md_debug0_s {
  7055. u64 pmd0_length : 16;
  7056. u64 pmd1_length : 16;
  7057. u64 pmd0_vld : 1;
  7058. u64 pmd1_vld : 1;
  7059. u64 reserved_34_45 : 12;
  7060. u64 drain_pri : 1;
  7061. u64 drain : 1;
  7062. u64 c_con : 1;
  7063. u64 p_con : 1;
  7064. u64 reserved_50_51 : 2;
  7065. u64 child : 10;
  7066. u64 reserved_62 : 1;
  7067. u64 pmd_count : 1;
  7068. } s;
  7069. /* struct nixx_af_tl3x_md_debug0_s cn96xxp1; */
  7070. struct nixx_af_tl3x_md_debug0_cn96xxp3 {
  7071. u64 pmd0_length : 16;
  7072. u64 reserved_16_31 : 16;
  7073. u64 pmd0_vld : 1;
  7074. u64 reserved_33 : 1;
  7075. u64 reserved_34_45 : 12;
  7076. u64 reserved_46 : 1;
  7077. u64 reserved_47 : 1;
  7078. u64 c_con : 1;
  7079. u64 p_con : 1;
  7080. u64 reserved_50_51 : 2;
  7081. u64 child : 10;
  7082. u64 reserved_62 : 1;
  7083. u64 reserved_63 : 1;
  7084. } cn96xxp3;
  7085. /* struct nixx_af_tl3x_md_debug0_s cnf95xx; */
  7086. };
  7087. static inline u64 NIXX_AF_TL3X_MD_DEBUG0(u64 a)
  7088. __attribute__ ((pure, always_inline));
  7089. static inline u64 NIXX_AF_TL3X_MD_DEBUG0(u64 a)
  7090. {
  7091. return 0x10c0 + 0x10000 * a;
  7092. }
  7093. /**
  7094. * Register (RVU_PF_BAR0) nix#_af_tl3#_md_debug1
  7095. *
  7096. * NIX AF Transmit Level 3 Meta Descriptor Debug 1 Registers Packet meta
  7097. * descriptor 0 debug. See NIX_AF_TL1()_MD_DEBUG0.
  7098. */
  7099. union nixx_af_tl3x_md_debug1 {
  7100. u64 u;
  7101. struct nixx_af_tl3x_md_debug1_s {
  7102. u64 reserved_0_5 : 6;
  7103. u64 red_algo_override : 2;
  7104. u64 cir_dis : 1;
  7105. u64 pir_dis : 1;
  7106. u64 adjust : 9;
  7107. u64 uid : 4;
  7108. u64 reserved_23 : 1;
  7109. u64 bubble : 1;
  7110. u64 color : 2;
  7111. u64 pse_pkt_id : 9;
  7112. u64 reserved_36 : 1;
  7113. u64 tx_pkt_p2x : 2;
  7114. u64 sqm_pkt_id : 13;
  7115. u64 mdq_idx : 10;
  7116. u64 reserved_62 : 1;
  7117. u64 vld : 1;
  7118. } s;
  7119. struct nixx_af_tl3x_md_debug1_cn96xxp1 {
  7120. u64 reserved_0_5 : 6;
  7121. u64 red_algo_override : 2;
  7122. u64 cir_dis : 1;
  7123. u64 pir_dis : 1;
  7124. u64 adjust : 9;
  7125. u64 uid : 4;
  7126. u64 drain : 1;
  7127. u64 bubble : 1;
  7128. u64 color : 2;
  7129. u64 pse_pkt_id : 9;
  7130. u64 reserved_36 : 1;
  7131. u64 tx_pkt_p2x : 2;
  7132. u64 sqm_pkt_id : 13;
  7133. u64 mdq_idx : 10;
  7134. u64 reserved_62 : 1;
  7135. u64 vld : 1;
  7136. } cn96xxp1;
  7137. struct nixx_af_tl3x_md_debug1_cn96xxp3 {
  7138. u64 reserved_0_5 : 6;
  7139. u64 red_algo_override : 2;
  7140. u64 cir_dis : 1;
  7141. u64 pir_dis : 1;
  7142. u64 adjust : 9;
  7143. u64 reserved_19_22 : 4;
  7144. u64 flush : 1;
  7145. u64 bubble : 1;
  7146. u64 color : 2;
  7147. u64 pse_pkt_id : 9;
  7148. u64 reserved_36 : 1;
  7149. u64 tx_pkt_p2x : 2;
  7150. u64 sqm_pkt_id : 13;
  7151. u64 mdq_idx : 10;
  7152. u64 reserved_62 : 1;
  7153. u64 vld : 1;
  7154. } cn96xxp3;
  7155. /* struct nixx_af_tl3x_md_debug1_cn96xxp1 cnf95xx; */
  7156. };
  7157. static inline u64 NIXX_AF_TL3X_MD_DEBUG1(u64 a)
  7158. __attribute__ ((pure, always_inline));
  7159. static inline u64 NIXX_AF_TL3X_MD_DEBUG1(u64 a)
  7160. {
  7161. return 0x10c8 + 0x10000 * a;
  7162. }
  7163. /**
  7164. * Register (RVU_PF_BAR0) nix#_af_tl3#_md_debug2
  7165. *
  7166. * NIX AF Transmit Level 3 Meta Descriptor Debug 2 Registers Packet meta
  7167. * descriptor 1 debug. See NIX_AF_TL1()_MD_DEBUG0.
  7168. */
  7169. union nixx_af_tl3x_md_debug2 {
  7170. u64 u;
  7171. struct nixx_af_tl3x_md_debug2_s {
  7172. u64 reserved_0_5 : 6;
  7173. u64 red_algo_override : 2;
  7174. u64 cir_dis : 1;
  7175. u64 pir_dis : 1;
  7176. u64 adjust : 9;
  7177. u64 uid : 4;
  7178. u64 reserved_23 : 1;
  7179. u64 bubble : 1;
  7180. u64 color : 2;
  7181. u64 pse_pkt_id : 9;
  7182. u64 reserved_36 : 1;
  7183. u64 tx_pkt_p2x : 2;
  7184. u64 sqm_pkt_id : 13;
  7185. u64 mdq_idx : 10;
  7186. u64 reserved_62 : 1;
  7187. u64 vld : 1;
  7188. } s;
  7189. struct nixx_af_tl3x_md_debug2_cn96xxp1 {
  7190. u64 reserved_0_5 : 6;
  7191. u64 red_algo_override : 2;
  7192. u64 cir_dis : 1;
  7193. u64 pir_dis : 1;
  7194. u64 adjust : 9;
  7195. u64 uid : 4;
  7196. u64 drain : 1;
  7197. u64 bubble : 1;
  7198. u64 color : 2;
  7199. u64 pse_pkt_id : 9;
  7200. u64 reserved_36 : 1;
  7201. u64 tx_pkt_p2x : 2;
  7202. u64 sqm_pkt_id : 13;
  7203. u64 mdq_idx : 10;
  7204. u64 reserved_62 : 1;
  7205. u64 vld : 1;
  7206. } cn96xxp1;
  7207. struct nixx_af_tl3x_md_debug2_cn96xxp3 {
  7208. u64 reserved_0_5 : 6;
  7209. u64 red_algo_override : 2;
  7210. u64 cir_dis : 1;
  7211. u64 pir_dis : 1;
  7212. u64 adjust : 9;
  7213. u64 reserved_19_22 : 4;
  7214. u64 flush : 1;
  7215. u64 bubble : 1;
  7216. u64 color : 2;
  7217. u64 pse_pkt_id : 9;
  7218. u64 reserved_36 : 1;
  7219. u64 tx_pkt_p2x : 2;
  7220. u64 sqm_pkt_id : 13;
  7221. u64 mdq_idx : 10;
  7222. u64 reserved_62 : 1;
  7223. u64 vld : 1;
  7224. } cn96xxp3;
  7225. /* struct nixx_af_tl3x_md_debug2_cn96xxp1 cnf95xx; */
  7226. };
  7227. static inline u64 NIXX_AF_TL3X_MD_DEBUG2(u64 a)
  7228. __attribute__ ((pure, always_inline));
  7229. static inline u64 NIXX_AF_TL3X_MD_DEBUG2(u64 a)
  7230. {
  7231. return 0x10d0 + 0x10000 * a;
  7232. }
  7233. /**
  7234. * Register (RVU_PF_BAR0) nix#_af_tl3#_md_debug3
  7235. *
  7236. * NIX AF Transmit Level 3 Meta Descriptor Debug 3 Registers Flush meta
  7237. * descriptor debug. See NIX_AF_TL1()_MD_DEBUG0.
  7238. */
  7239. union nixx_af_tl3x_md_debug3 {
  7240. u64 u;
  7241. struct nixx_af_tl3x_md_debug3_s {
  7242. u64 reserved_0_36 : 37;
  7243. u64 tx_pkt_p2x : 2;
  7244. u64 sqm_pkt_id : 13;
  7245. u64 mdq_idx : 10;
  7246. u64 reserved_62 : 1;
  7247. u64 vld : 1;
  7248. } s;
  7249. /* struct nixx_af_tl3x_md_debug3_s cn96xxp1; */
  7250. struct nixx_af_tl3x_md_debug3_cn96xxp3 {
  7251. u64 reserved_0_36 : 37;
  7252. u64 reserved_37_38 : 2;
  7253. u64 reserved_39_51 : 13;
  7254. u64 reserved_52_61 : 10;
  7255. u64 reserved_62 : 1;
  7256. u64 reserved_63 : 1;
  7257. } cn96xxp3;
  7258. /* struct nixx_af_tl3x_md_debug3_s cnf95xx; */
  7259. };
  7260. static inline u64 NIXX_AF_TL3X_MD_DEBUG3(u64 a)
  7261. __attribute__ ((pure, always_inline));
  7262. static inline u64 NIXX_AF_TL3X_MD_DEBUG3(u64 a)
  7263. {
  7264. return 0x10d8 + 0x10000 * a;
  7265. }
  7266. /**
  7267. * Register (RVU_PF_BAR0) nix#_af_tl3#_parent
  7268. *
  7269. * NIX AF Transmit Level 3 Parent Registers
  7270. */
  7271. union nixx_af_tl3x_parent {
  7272. u64 u;
  7273. struct nixx_af_tl3x_parent_s {
  7274. u64 reserved_0_15 : 16;
  7275. u64 parent : 8;
  7276. u64 reserved_24_63 : 40;
  7277. } s;
  7278. /* struct nixx_af_tl3x_parent_s cn; */
  7279. };
  7280. static inline u64 NIXX_AF_TL3X_PARENT(u64 a)
  7281. __attribute__ ((pure, always_inline));
  7282. static inline u64 NIXX_AF_TL3X_PARENT(u64 a)
  7283. {
  7284. return 0x1088 + 0x10000 * a;
  7285. }
  7286. /**
  7287. * Register (RVU_PF_BAR0) nix#_af_tl3#_pir
  7288. *
  7289. * NIX AF Transmit Level 3 Peak Information Rate Registers This register
  7290. * has the same bit fields as NIX_AF_TL1()_CIR.
  7291. */
  7292. union nixx_af_tl3x_pir {
  7293. u64 u;
  7294. struct nixx_af_tl3x_pir_s {
  7295. u64 enable : 1;
  7296. u64 rate_mantissa : 8;
  7297. u64 rate_exponent : 4;
  7298. u64 rate_divider_exponent : 4;
  7299. u64 reserved_17_28 : 12;
  7300. u64 burst_mantissa : 8;
  7301. u64 burst_exponent : 4;
  7302. u64 reserved_41_63 : 23;
  7303. } s;
  7304. /* struct nixx_af_tl3x_pir_s cn; */
  7305. };
  7306. static inline u64 NIXX_AF_TL3X_PIR(u64 a)
  7307. __attribute__ ((pure, always_inline));
  7308. static inline u64 NIXX_AF_TL3X_PIR(u64 a)
  7309. {
  7310. return 0x1030 + 0x10000 * a;
  7311. }
  7312. /**
  7313. * Register (RVU_PF_BAR0) nix#_af_tl3#_pointers
  7314. *
  7315. * INTERNAL: NIX Transmit Level 3 Linked List Pointers Debug Register
  7316. * This register has the same bit fields as NIX_AF_TL2()_POINTERS.
  7317. */
  7318. union nixx_af_tl3x_pointers {
  7319. u64 u;
  7320. struct nixx_af_tl3x_pointers_s {
  7321. u64 next : 8;
  7322. u64 reserved_8_15 : 8;
  7323. u64 prev : 8;
  7324. u64 reserved_24_63 : 40;
  7325. } s;
  7326. /* struct nixx_af_tl3x_pointers_s cn; */
  7327. };
  7328. static inline u64 NIXX_AF_TL3X_POINTERS(u64 a)
  7329. __attribute__ ((pure, always_inline));
  7330. static inline u64 NIXX_AF_TL3X_POINTERS(u64 a)
  7331. {
  7332. return 0x1060 + 0x10000 * a;
  7333. }
  7334. /**
  7335. * Register (RVU_PF_BAR0) nix#_af_tl3#_red
  7336. *
  7337. * INTERNAL: NIX Transmit Level 3 Red State Debug Register This register
  7338. * has the same bit fields as NIX_AF_TL3()_YELLOW.
  7339. */
  7340. union nixx_af_tl3x_red {
  7341. u64 u;
  7342. struct nixx_af_tl3x_red_s {
  7343. u64 tail : 9;
  7344. u64 reserved_9 : 1;
  7345. u64 head : 9;
  7346. u64 reserved_19_63 : 45;
  7347. } s;
  7348. /* struct nixx_af_tl3x_red_s cn; */
  7349. };
  7350. static inline u64 NIXX_AF_TL3X_RED(u64 a)
  7351. __attribute__ ((pure, always_inline));
  7352. static inline u64 NIXX_AF_TL3X_RED(u64 a)
  7353. {
  7354. return 0x10b0 + 0x10000 * a;
  7355. }
  7356. /**
  7357. * Register (RVU_PF_BAR0) nix#_af_tl3#_sched_state
  7358. *
  7359. * NIX AF Transmit Level 3 Scheduling Control State Registers This
  7360. * register has the same bit fields as NIX_AF_TL2()_SCHED_STATE.
  7361. */
  7362. union nixx_af_tl3x_sched_state {
  7363. u64 u;
  7364. struct nixx_af_tl3x_sched_state_s {
  7365. u64 rr_count : 25;
  7366. u64 reserved_25_63 : 39;
  7367. } s;
  7368. /* struct nixx_af_tl3x_sched_state_s cn; */
  7369. };
  7370. static inline u64 NIXX_AF_TL3X_SCHED_STATE(u64 a)
  7371. __attribute__ ((pure, always_inline));
  7372. static inline u64 NIXX_AF_TL3X_SCHED_STATE(u64 a)
  7373. {
  7374. return 0x1040 + 0x10000 * a;
  7375. }
  7376. /**
  7377. * Register (RVU_PF_BAR0) nix#_af_tl3#_schedule
  7378. *
  7379. * NIX AF Transmit Level 3 Scheduling Control Registers This register has
  7380. * the same bit fields as NIX_AF_TL2()_SCHEDULE.
  7381. */
  7382. union nixx_af_tl3x_schedule {
  7383. u64 u;
  7384. struct nixx_af_tl3x_schedule_s {
  7385. u64 rr_quantum : 24;
  7386. u64 prio : 4;
  7387. u64 reserved_28_63 : 36;
  7388. } s;
  7389. /* struct nixx_af_tl3x_schedule_s cn; */
  7390. };
  7391. static inline u64 NIXX_AF_TL3X_SCHEDULE(u64 a)
  7392. __attribute__ ((pure, always_inline));
  7393. static inline u64 NIXX_AF_TL3X_SCHEDULE(u64 a)
  7394. {
  7395. return 0x1000 + 0x10000 * a;
  7396. }
  7397. /**
  7398. * Register (RVU_PF_BAR0) nix#_af_tl3#_shape
  7399. *
  7400. * NIX AF Transmit Level 3 Shaping Control Registers
  7401. */
  7402. union nixx_af_tl3x_shape {
  7403. u64 u;
  7404. struct nixx_af_tl3x_shape_s {
  7405. u64 adjust : 9;
  7406. u64 red_algo : 2;
  7407. u64 red_disable : 1;
  7408. u64 yellow_disable : 1;
  7409. u64 reserved_13_23 : 11;
  7410. u64 length_disable : 1;
  7411. u64 schedule_list : 2;
  7412. u64 reserved_27_63 : 37;
  7413. } s;
  7414. /* struct nixx_af_tl3x_shape_s cn; */
  7415. };
  7416. static inline u64 NIXX_AF_TL3X_SHAPE(u64 a)
  7417. __attribute__ ((pure, always_inline));
  7418. static inline u64 NIXX_AF_TL3X_SHAPE(u64 a)
  7419. {
  7420. return 0x1010 + 0x10000 * a;
  7421. }
  7422. /**
  7423. * Register (RVU_PF_BAR0) nix#_af_tl3#_shape_state
  7424. *
  7425. * NIX AF Transmit Level 3 Shaping State Registers This register has the
  7426. * same bit fields as NIX_AF_TL2()_SHAPE_STATE. This register must not be
  7427. * written during normal operation.
  7428. */
  7429. union nixx_af_tl3x_shape_state {
  7430. u64 u;
  7431. struct nixx_af_tl3x_shape_state_s {
  7432. u64 cir_accum : 26;
  7433. u64 pir_accum : 26;
  7434. u64 color : 2;
  7435. u64 reserved_54_63 : 10;
  7436. } s;
  7437. /* struct nixx_af_tl3x_shape_state_s cn; */
  7438. };
  7439. static inline u64 NIXX_AF_TL3X_SHAPE_STATE(u64 a)
  7440. __attribute__ ((pure, always_inline));
  7441. static inline u64 NIXX_AF_TL3X_SHAPE_STATE(u64 a)
  7442. {
  7443. return 0x1050 + 0x10000 * a;
  7444. }
  7445. /**
  7446. * Register (RVU_PF_BAR0) nix#_af_tl3#_sw_xoff
  7447. *
  7448. * NIX AF Transmit Level 3 Software Controlled XOFF Registers This
  7449. * register has the same bit fields as NIX_AF_TL1()_SW_XOFF
  7450. */
  7451. union nixx_af_tl3x_sw_xoff {
  7452. u64 u;
  7453. struct nixx_af_tl3x_sw_xoff_s {
  7454. u64 xoff : 1;
  7455. u64 drain : 1;
  7456. u64 reserved_2 : 1;
  7457. u64 drain_irq : 1;
  7458. u64 reserved_4_63 : 60;
  7459. } s;
  7460. /* struct nixx_af_tl3x_sw_xoff_s cn; */
  7461. };
  7462. static inline u64 NIXX_AF_TL3X_SW_XOFF(u64 a)
  7463. __attribute__ ((pure, always_inline));
  7464. static inline u64 NIXX_AF_TL3X_SW_XOFF(u64 a)
  7465. {
  7466. return 0x1070 + 0x10000 * a;
  7467. }
  7468. /**
  7469. * Register (RVU_PF_BAR0) nix#_af_tl3#_topology
  7470. *
  7471. * NIX AF Transmit Level 3 Topology Registers
  7472. */
  7473. union nixx_af_tl3x_topology {
  7474. u64 u;
  7475. struct nixx_af_tl3x_topology_s {
  7476. u64 reserved_0 : 1;
  7477. u64 rr_prio : 4;
  7478. u64 reserved_5_31 : 27;
  7479. u64 prio_anchor : 9;
  7480. u64 reserved_41_63 : 23;
  7481. } s;
  7482. /* struct nixx_af_tl3x_topology_s cn; */
  7483. };
  7484. static inline u64 NIXX_AF_TL3X_TOPOLOGY(u64 a)
  7485. __attribute__ ((pure, always_inline));
  7486. static inline u64 NIXX_AF_TL3X_TOPOLOGY(u64 a)
  7487. {
  7488. return 0x1080 + 0x10000 * a;
  7489. }
  7490. /**
  7491. * Register (RVU_PF_BAR0) nix#_af_tl3#_yellow
  7492. *
  7493. * INTERNAL: NIX Transmit Level 3 Yellow State Debug Register
  7494. */
  7495. union nixx_af_tl3x_yellow {
  7496. u64 u;
  7497. struct nixx_af_tl3x_yellow_s {
  7498. u64 tail : 9;
  7499. u64 reserved_9 : 1;
  7500. u64 head : 9;
  7501. u64 reserved_19_63 : 45;
  7502. } s;
  7503. /* struct nixx_af_tl3x_yellow_s cn; */
  7504. };
  7505. static inline u64 NIXX_AF_TL3X_YELLOW(u64 a)
  7506. __attribute__ ((pure, always_inline));
  7507. static inline u64 NIXX_AF_TL3X_YELLOW(u64 a)
  7508. {
  7509. return 0x10a0 + 0x10000 * a;
  7510. }
  7511. /**
  7512. * Register (RVU_PF_BAR0) nix#_af_tl3_const
  7513. *
  7514. * NIX AF Transmit Level 3 Constants Register This register contains
  7515. * constants for software discovery.
  7516. */
  7517. union nixx_af_tl3_const {
  7518. u64 u;
  7519. struct nixx_af_tl3_const_s {
  7520. u64 count : 16;
  7521. u64 reserved_16_63 : 48;
  7522. } s;
  7523. /* struct nixx_af_tl3_const_s cn; */
  7524. };
  7525. static inline u64 NIXX_AF_TL3_CONST(void)
  7526. __attribute__ ((pure, always_inline));
  7527. static inline u64 NIXX_AF_TL3_CONST(void)
  7528. {
  7529. return 0x80;
  7530. }
  7531. /**
  7532. * Register (RVU_PF_BAR0) nix#_af_tl3_tl2#_bp_status
  7533. *
  7534. * NIX AF Transmit Level 3/2 Backpressure Status Registers
  7535. */
  7536. union nixx_af_tl3_tl2x_bp_status {
  7537. u64 u;
  7538. struct nixx_af_tl3_tl2x_bp_status_s {
  7539. u64 hw_xoff : 1;
  7540. u64 reserved_1_63 : 63;
  7541. } s;
  7542. /* struct nixx_af_tl3_tl2x_bp_status_s cn; */
  7543. };
  7544. static inline u64 NIXX_AF_TL3_TL2X_BP_STATUS(u64 a)
  7545. __attribute__ ((pure, always_inline));
  7546. static inline u64 NIXX_AF_TL3_TL2X_BP_STATUS(u64 a)
  7547. {
  7548. return 0x1610 + 0x10000 * a;
  7549. }
  7550. /**
  7551. * Register (RVU_PF_BAR0) nix#_af_tl3_tl2#_cfg
  7552. *
  7553. * NIX AF Transmit Level 3/2 Configuration Registers
  7554. */
  7555. union nixx_af_tl3_tl2x_cfg {
  7556. u64 u;
  7557. struct nixx_af_tl3_tl2x_cfg_s {
  7558. u64 express : 1;
  7559. u64 reserved_1_63 : 63;
  7560. } s;
  7561. /* struct nixx_af_tl3_tl2x_cfg_s cn; */
  7562. };
  7563. static inline u64 NIXX_AF_TL3_TL2X_CFG(u64 a)
  7564. __attribute__ ((pure, always_inline));
  7565. static inline u64 NIXX_AF_TL3_TL2X_CFG(u64 a)
  7566. {
  7567. return 0x1600 + 0x10000 * a;
  7568. }
  7569. /**
  7570. * Register (RVU_PF_BAR0) nix#_af_tl3_tl2#_link#_cfg
  7571. *
  7572. * NIX AF Transmit Level 3/2 Link Configuration Registers These registers
  7573. * specify the links and associated channels that a given TL3 or TL2
  7574. * queue (depending on NIX_AF_PSE_CHANNEL_LEVEL[BP_LEVEL]) can transmit
  7575. * on. Each TL3/TL2 queue can be enabled to transmit on and be
  7576. * backpressured by one or more links and associated channels. The last
  7577. * index (LINK) is enumerated by NIX_LINK_E.
  7578. */
  7579. union nixx_af_tl3_tl2x_linkx_cfg {
  7580. u64 u;
  7581. struct nixx_af_tl3_tl2x_linkx_cfg_s {
  7582. u64 relchan : 8;
  7583. u64 reserved_8_11 : 4;
  7584. u64 ena : 1;
  7585. u64 bp_ena : 1;
  7586. u64 reserved_14_63 : 50;
  7587. } s;
  7588. /* struct nixx_af_tl3_tl2x_linkx_cfg_s cn; */
  7589. };
  7590. static inline u64 NIXX_AF_TL3_TL2X_LINKX_CFG(u64 a, u64 b)
  7591. __attribute__ ((pure, always_inline));
  7592. static inline u64 NIXX_AF_TL3_TL2X_LINKX_CFG(u64 a, u64 b)
  7593. {
  7594. return 0x1700 + 0x10000 * a + 8 * b;
  7595. }
  7596. /**
  7597. * Register (RVU_PF_BAR0) nix#_af_tl4#_bp_status
  7598. *
  7599. * NIX AF Transmit Level 4 Backpressure Status Registers
  7600. */
  7601. union nixx_af_tl4x_bp_status {
  7602. u64 u;
  7603. struct nixx_af_tl4x_bp_status_s {
  7604. u64 hw_xoff : 1;
  7605. u64 reserved_1_63 : 63;
  7606. } s;
  7607. /* struct nixx_af_tl4x_bp_status_s cn; */
  7608. };
  7609. static inline u64 NIXX_AF_TL4X_BP_STATUS(u64 a)
  7610. __attribute__ ((pure, always_inline));
  7611. static inline u64 NIXX_AF_TL4X_BP_STATUS(u64 a)
  7612. {
  7613. return 0xb00 + 0x10000 * a;
  7614. }
  7615. /**
  7616. * Register (RVU_PF_BAR0) nix#_af_tl4#_cir
  7617. *
  7618. * NIX AF Transmit Level 4 Committed Information Rate Registers This
  7619. * register has the same bit fields as NIX_AF_TL1()_CIR.
  7620. */
  7621. union nixx_af_tl4x_cir {
  7622. u64 u;
  7623. struct nixx_af_tl4x_cir_s {
  7624. u64 enable : 1;
  7625. u64 rate_mantissa : 8;
  7626. u64 rate_exponent : 4;
  7627. u64 rate_divider_exponent : 4;
  7628. u64 reserved_17_28 : 12;
  7629. u64 burst_mantissa : 8;
  7630. u64 burst_exponent : 4;
  7631. u64 reserved_41_63 : 23;
  7632. } s;
  7633. /* struct nixx_af_tl4x_cir_s cn; */
  7634. };
  7635. static inline u64 NIXX_AF_TL4X_CIR(u64 a)
  7636. __attribute__ ((pure, always_inline));
  7637. static inline u64 NIXX_AF_TL4X_CIR(u64 a)
  7638. {
  7639. return 0x1220 + 0x10000 * a;
  7640. }
  7641. /**
  7642. * Register (RVU_PF_BAR0) nix#_af_tl4#_green
  7643. *
  7644. * INTERNAL: NIX Transmit Level 4 Green State Debug Register This
  7645. * register has the same bit fields as NIX_AF_TL3()_GREEN.
  7646. */
  7647. union nixx_af_tl4x_green {
  7648. u64 u;
  7649. struct nixx_af_tl4x_green_s {
  7650. u64 tail : 9;
  7651. u64 reserved_9 : 1;
  7652. u64 head : 9;
  7653. u64 reserved_19 : 1;
  7654. u64 active_vec : 20;
  7655. u64 rr_active : 1;
  7656. u64 reserved_41_63 : 23;
  7657. } s;
  7658. /* struct nixx_af_tl4x_green_s cn; */
  7659. };
  7660. static inline u64 NIXX_AF_TL4X_GREEN(u64 a)
  7661. __attribute__ ((pure, always_inline));
  7662. static inline u64 NIXX_AF_TL4X_GREEN(u64 a)
  7663. {
  7664. return 0x1290 + 0x10000 * a;
  7665. }
  7666. /**
  7667. * Register (RVU_PF_BAR0) nix#_af_tl4#_md_debug0
  7668. *
  7669. * NIX AF Transmit Level 4 Meta Descriptor Debug 0 Registers See
  7670. * NIX_AF_TL1()_MD_DEBUG0.
  7671. */
  7672. union nixx_af_tl4x_md_debug0 {
  7673. u64 u;
  7674. struct nixx_af_tl4x_md_debug0_s {
  7675. u64 pmd0_length : 16;
  7676. u64 pmd1_length : 16;
  7677. u64 pmd0_vld : 1;
  7678. u64 pmd1_vld : 1;
  7679. u64 reserved_34_45 : 12;
  7680. u64 drain_pri : 1;
  7681. u64 drain : 1;
  7682. u64 c_con : 1;
  7683. u64 p_con : 1;
  7684. u64 reserved_50_51 : 2;
  7685. u64 child : 10;
  7686. u64 reserved_62 : 1;
  7687. u64 pmd_count : 1;
  7688. } s;
  7689. /* struct nixx_af_tl4x_md_debug0_s cn96xxp1; */
  7690. struct nixx_af_tl4x_md_debug0_cn96xxp3 {
  7691. u64 pmd0_length : 16;
  7692. u64 reserved_16_31 : 16;
  7693. u64 pmd0_vld : 1;
  7694. u64 reserved_33 : 1;
  7695. u64 reserved_34_45 : 12;
  7696. u64 reserved_46 : 1;
  7697. u64 reserved_47 : 1;
  7698. u64 c_con : 1;
  7699. u64 p_con : 1;
  7700. u64 reserved_50_51 : 2;
  7701. u64 child : 10;
  7702. u64 reserved_62 : 1;
  7703. u64 reserved_63 : 1;
  7704. } cn96xxp3;
  7705. /* struct nixx_af_tl4x_md_debug0_s cnf95xx; */
  7706. };
  7707. static inline u64 NIXX_AF_TL4X_MD_DEBUG0(u64 a)
  7708. __attribute__ ((pure, always_inline));
  7709. static inline u64 NIXX_AF_TL4X_MD_DEBUG0(u64 a)
  7710. {
  7711. return 0x12c0 + 0x10000 * a;
  7712. }
  7713. /**
  7714. * Register (RVU_PF_BAR0) nix#_af_tl4#_md_debug1
  7715. *
  7716. * NIX AF Transmit Level 4 Meta Descriptor Debug 1 Registers Packet meta
  7717. * descriptor 0 debug. See NIX_AF_TL1()_MD_DEBUG0.
  7718. */
  7719. union nixx_af_tl4x_md_debug1 {
  7720. u64 u;
  7721. struct nixx_af_tl4x_md_debug1_s {
  7722. u64 reserved_0_5 : 6;
  7723. u64 red_algo_override : 2;
  7724. u64 cir_dis : 1;
  7725. u64 pir_dis : 1;
  7726. u64 adjust : 9;
  7727. u64 uid : 4;
  7728. u64 reserved_23 : 1;
  7729. u64 bubble : 1;
  7730. u64 color : 2;
  7731. u64 pse_pkt_id : 9;
  7732. u64 reserved_36 : 1;
  7733. u64 tx_pkt_p2x : 2;
  7734. u64 sqm_pkt_id : 13;
  7735. u64 mdq_idx : 10;
  7736. u64 reserved_62 : 1;
  7737. u64 vld : 1;
  7738. } s;
  7739. struct nixx_af_tl4x_md_debug1_cn96xxp1 {
  7740. u64 reserved_0_5 : 6;
  7741. u64 red_algo_override : 2;
  7742. u64 cir_dis : 1;
  7743. u64 pir_dis : 1;
  7744. u64 adjust : 9;
  7745. u64 uid : 4;
  7746. u64 drain : 1;
  7747. u64 bubble : 1;
  7748. u64 color : 2;
  7749. u64 pse_pkt_id : 9;
  7750. u64 reserved_36 : 1;
  7751. u64 tx_pkt_p2x : 2;
  7752. u64 sqm_pkt_id : 13;
  7753. u64 mdq_idx : 10;
  7754. u64 reserved_62 : 1;
  7755. u64 vld : 1;
  7756. } cn96xxp1;
  7757. struct nixx_af_tl4x_md_debug1_cn96xxp3 {
  7758. u64 reserved_0_5 : 6;
  7759. u64 red_algo_override : 2;
  7760. u64 cir_dis : 1;
  7761. u64 pir_dis : 1;
  7762. u64 adjust : 9;
  7763. u64 reserved_19_22 : 4;
  7764. u64 flush : 1;
  7765. u64 bubble : 1;
  7766. u64 color : 2;
  7767. u64 pse_pkt_id : 9;
  7768. u64 reserved_36 : 1;
  7769. u64 tx_pkt_p2x : 2;
  7770. u64 sqm_pkt_id : 13;
  7771. u64 mdq_idx : 10;
  7772. u64 reserved_62 : 1;
  7773. u64 vld : 1;
  7774. } cn96xxp3;
  7775. /* struct nixx_af_tl4x_md_debug1_cn96xxp1 cnf95xx; */
  7776. };
  7777. static inline u64 NIXX_AF_TL4X_MD_DEBUG1(u64 a)
  7778. __attribute__ ((pure, always_inline));
  7779. static inline u64 NIXX_AF_TL4X_MD_DEBUG1(u64 a)
  7780. {
  7781. return 0x12c8 + 0x10000 * a;
  7782. }
  7783. /**
  7784. * Register (RVU_PF_BAR0) nix#_af_tl4#_md_debug2
  7785. *
  7786. * NIX AF Transmit Level 4 Meta Descriptor Debug 2 Registers Packet meta
  7787. * descriptor 1 debug. See NIX_AF_TL1()_MD_DEBUG0.
  7788. */
  7789. union nixx_af_tl4x_md_debug2 {
  7790. u64 u;
  7791. struct nixx_af_tl4x_md_debug2_s {
  7792. u64 reserved_0_5 : 6;
  7793. u64 red_algo_override : 2;
  7794. u64 cir_dis : 1;
  7795. u64 pir_dis : 1;
  7796. u64 adjust : 9;
  7797. u64 uid : 4;
  7798. u64 reserved_23 : 1;
  7799. u64 bubble : 1;
  7800. u64 color : 2;
  7801. u64 pse_pkt_id : 9;
  7802. u64 reserved_36 : 1;
  7803. u64 tx_pkt_p2x : 2;
  7804. u64 sqm_pkt_id : 13;
  7805. u64 mdq_idx : 10;
  7806. u64 reserved_62 : 1;
  7807. u64 vld : 1;
  7808. } s;
  7809. struct nixx_af_tl4x_md_debug2_cn96xxp1 {
  7810. u64 reserved_0_5 : 6;
  7811. u64 red_algo_override : 2;
  7812. u64 cir_dis : 1;
  7813. u64 pir_dis : 1;
  7814. u64 adjust : 9;
  7815. u64 uid : 4;
  7816. u64 drain : 1;
  7817. u64 bubble : 1;
  7818. u64 color : 2;
  7819. u64 pse_pkt_id : 9;
  7820. u64 reserved_36 : 1;
  7821. u64 tx_pkt_p2x : 2;
  7822. u64 sqm_pkt_id : 13;
  7823. u64 mdq_idx : 10;
  7824. u64 reserved_62 : 1;
  7825. u64 vld : 1;
  7826. } cn96xxp1;
  7827. struct nixx_af_tl4x_md_debug2_cn96xxp3 {
  7828. u64 reserved_0_5 : 6;
  7829. u64 red_algo_override : 2;
  7830. u64 cir_dis : 1;
  7831. u64 pir_dis : 1;
  7832. u64 adjust : 9;
  7833. u64 reserved_19_22 : 4;
  7834. u64 flush : 1;
  7835. u64 bubble : 1;
  7836. u64 color : 2;
  7837. u64 pse_pkt_id : 9;
  7838. u64 reserved_36 : 1;
  7839. u64 tx_pkt_p2x : 2;
  7840. u64 sqm_pkt_id : 13;
  7841. u64 mdq_idx : 10;
  7842. u64 reserved_62 : 1;
  7843. u64 vld : 1;
  7844. } cn96xxp3;
  7845. /* struct nixx_af_tl4x_md_debug2_cn96xxp1 cnf95xx; */
  7846. };
  7847. static inline u64 NIXX_AF_TL4X_MD_DEBUG2(u64 a)
  7848. __attribute__ ((pure, always_inline));
  7849. static inline u64 NIXX_AF_TL4X_MD_DEBUG2(u64 a)
  7850. {
  7851. return 0x12d0 + 0x10000 * a;
  7852. }
  7853. /**
  7854. * Register (RVU_PF_BAR0) nix#_af_tl4#_md_debug3
  7855. *
  7856. * NIX AF Transmit Level 4 Meta Descriptor Debug 3 Registers Flush meta
  7857. * descriptor debug. See NIX_AF_TL1()_MD_DEBUG0.
  7858. */
  7859. union nixx_af_tl4x_md_debug3 {
  7860. u64 u;
  7861. struct nixx_af_tl4x_md_debug3_s {
  7862. u64 reserved_0_36 : 37;
  7863. u64 tx_pkt_p2x : 2;
  7864. u64 sqm_pkt_id : 13;
  7865. u64 mdq_idx : 10;
  7866. u64 reserved_62 : 1;
  7867. u64 vld : 1;
  7868. } s;
  7869. /* struct nixx_af_tl4x_md_debug3_s cn96xxp1; */
  7870. struct nixx_af_tl4x_md_debug3_cn96xxp3 {
  7871. u64 reserved_0_36 : 37;
  7872. u64 reserved_37_38 : 2;
  7873. u64 reserved_39_51 : 13;
  7874. u64 reserved_52_61 : 10;
  7875. u64 reserved_62 : 1;
  7876. u64 reserved_63 : 1;
  7877. } cn96xxp3;
  7878. /* struct nixx_af_tl4x_md_debug3_s cnf95xx; */
  7879. };
  7880. static inline u64 NIXX_AF_TL4X_MD_DEBUG3(u64 a)
  7881. __attribute__ ((pure, always_inline));
  7882. static inline u64 NIXX_AF_TL4X_MD_DEBUG3(u64 a)
  7883. {
  7884. return 0x12d8 + 0x10000 * a;
  7885. }
  7886. /**
  7887. * Register (RVU_PF_BAR0) nix#_af_tl4#_parent
  7888. *
  7889. * NIX AF Transmit Level 4 Parent Registers
  7890. */
  7891. union nixx_af_tl4x_parent {
  7892. u64 u;
  7893. struct nixx_af_tl4x_parent_s {
  7894. u64 reserved_0_15 : 16;
  7895. u64 parent : 8;
  7896. u64 reserved_24_63 : 40;
  7897. } s;
  7898. /* struct nixx_af_tl4x_parent_s cn; */
  7899. };
  7900. static inline u64 NIXX_AF_TL4X_PARENT(u64 a)
  7901. __attribute__ ((pure, always_inline));
  7902. static inline u64 NIXX_AF_TL4X_PARENT(u64 a)
  7903. {
  7904. return 0x1288 + 0x10000 * a;
  7905. }
  7906. /**
  7907. * Register (RVU_PF_BAR0) nix#_af_tl4#_pir
  7908. *
  7909. * NIX AF Transmit Level 4 Peak Information Rate Registers This register
  7910. * has the same bit fields as NIX_AF_TL1()_CIR.
  7911. */
  7912. union nixx_af_tl4x_pir {
  7913. u64 u;
  7914. struct nixx_af_tl4x_pir_s {
  7915. u64 enable : 1;
  7916. u64 rate_mantissa : 8;
  7917. u64 rate_exponent : 4;
  7918. u64 rate_divider_exponent : 4;
  7919. u64 reserved_17_28 : 12;
  7920. u64 burst_mantissa : 8;
  7921. u64 burst_exponent : 4;
  7922. u64 reserved_41_63 : 23;
  7923. } s;
  7924. /* struct nixx_af_tl4x_pir_s cn; */
  7925. };
  7926. static inline u64 NIXX_AF_TL4X_PIR(u64 a)
  7927. __attribute__ ((pure, always_inline));
  7928. static inline u64 NIXX_AF_TL4X_PIR(u64 a)
  7929. {
  7930. return 0x1230 + 0x10000 * a;
  7931. }
  7932. /**
  7933. * Register (RVU_PF_BAR0) nix#_af_tl4#_pointers
  7934. *
  7935. * INTERNAL: NIX Transmit Level 4 Linked List Pointers Debug Register
  7936. * This register has the same bit fields as NIX_AF_TL2()_POINTERS.
  7937. */
  7938. union nixx_af_tl4x_pointers {
  7939. u64 u;
  7940. struct nixx_af_tl4x_pointers_s {
  7941. u64 next : 9;
  7942. u64 reserved_9_15 : 7;
  7943. u64 prev : 9;
  7944. u64 reserved_25_63 : 39;
  7945. } s;
  7946. /* struct nixx_af_tl4x_pointers_s cn; */
  7947. };
  7948. static inline u64 NIXX_AF_TL4X_POINTERS(u64 a)
  7949. __attribute__ ((pure, always_inline));
  7950. static inline u64 NIXX_AF_TL4X_POINTERS(u64 a)
  7951. {
  7952. return 0x1260 + 0x10000 * a;
  7953. }
  7954. /**
  7955. * Register (RVU_PF_BAR0) nix#_af_tl4#_red
  7956. *
  7957. * INTERNAL: NIX Transmit Level 4 Red State Debug Register This register
  7958. * has the same bit fields as NIX_AF_TL3()_YELLOW.
  7959. */
  7960. union nixx_af_tl4x_red {
  7961. u64 u;
  7962. struct nixx_af_tl4x_red_s {
  7963. u64 tail : 9;
  7964. u64 reserved_9 : 1;
  7965. u64 head : 9;
  7966. u64 reserved_19_63 : 45;
  7967. } s;
  7968. /* struct nixx_af_tl4x_red_s cn; */
  7969. };
  7970. static inline u64 NIXX_AF_TL4X_RED(u64 a)
  7971. __attribute__ ((pure, always_inline));
  7972. static inline u64 NIXX_AF_TL4X_RED(u64 a)
  7973. {
  7974. return 0x12b0 + 0x10000 * a;
  7975. }
  7976. /**
  7977. * Register (RVU_PF_BAR0) nix#_af_tl4#_sched_state
  7978. *
  7979. * NIX AF Transmit Level 4 Scheduling Control State Registers This
  7980. * register has the same bit fields as NIX_AF_TL2()_SCHED_STATE.
  7981. */
  7982. union nixx_af_tl4x_sched_state {
  7983. u64 u;
  7984. struct nixx_af_tl4x_sched_state_s {
  7985. u64 rr_count : 25;
  7986. u64 reserved_25_63 : 39;
  7987. } s;
  7988. /* struct nixx_af_tl4x_sched_state_s cn; */
  7989. };
  7990. static inline u64 NIXX_AF_TL4X_SCHED_STATE(u64 a)
  7991. __attribute__ ((pure, always_inline));
  7992. static inline u64 NIXX_AF_TL4X_SCHED_STATE(u64 a)
  7993. {
  7994. return 0x1240 + 0x10000 * a;
  7995. }
  7996. /**
  7997. * Register (RVU_PF_BAR0) nix#_af_tl4#_schedule
  7998. *
  7999. * NIX AF Transmit Level 4 Scheduling Control Registers This register has
  8000. * the same bit fields as NIX_AF_TL2()_SCHEDULE.
  8001. */
  8002. union nixx_af_tl4x_schedule {
  8003. u64 u;
  8004. struct nixx_af_tl4x_schedule_s {
  8005. u64 rr_quantum : 24;
  8006. u64 prio : 4;
  8007. u64 reserved_28_63 : 36;
  8008. } s;
  8009. /* struct nixx_af_tl4x_schedule_s cn; */
  8010. };
  8011. static inline u64 NIXX_AF_TL4X_SCHEDULE(u64 a)
  8012. __attribute__ ((pure, always_inline));
  8013. static inline u64 NIXX_AF_TL4X_SCHEDULE(u64 a)
  8014. {
  8015. return 0x1200 + 0x10000 * a;
  8016. }
  8017. /**
  8018. * Register (RVU_PF_BAR0) nix#_af_tl4#_sdp_link_cfg
  8019. *
  8020. * NIX AF Transmit Level 4 Link Configuration Registers These registers
  8021. * specify which TL4 queues transmit to and are optionally backpressured
  8022. * by SDP.
  8023. */
  8024. union nixx_af_tl4x_sdp_link_cfg {
  8025. u64 u;
  8026. struct nixx_af_tl4x_sdp_link_cfg_s {
  8027. u64 relchan : 8;
  8028. u64 reserved_8_11 : 4;
  8029. u64 ena : 1;
  8030. u64 bp_ena : 1;
  8031. u64 reserved_14_63 : 50;
  8032. } s;
  8033. /* struct nixx_af_tl4x_sdp_link_cfg_s cn; */
  8034. };
  8035. static inline u64 NIXX_AF_TL4X_SDP_LINK_CFG(u64 a)
  8036. __attribute__ ((pure, always_inline));
  8037. static inline u64 NIXX_AF_TL4X_SDP_LINK_CFG(u64 a)
  8038. {
  8039. return 0xb10 + 0x10000 * a;
  8040. }
  8041. /**
  8042. * Register (RVU_PF_BAR0) nix#_af_tl4#_shape
  8043. *
  8044. * NIX AF Transmit Level 4 Shaping Control Registers This register has
  8045. * the same bit fields as NIX_AF_TL2()_SHAPE.
  8046. */
  8047. union nixx_af_tl4x_shape {
  8048. u64 u;
  8049. struct nixx_af_tl4x_shape_s {
  8050. u64 adjust : 9;
  8051. u64 red_algo : 2;
  8052. u64 red_disable : 1;
  8053. u64 yellow_disable : 1;
  8054. u64 reserved_13_23 : 11;
  8055. u64 length_disable : 1;
  8056. u64 schedule_list : 2;
  8057. u64 reserved_27_63 : 37;
  8058. } s;
  8059. /* struct nixx_af_tl4x_shape_s cn; */
  8060. };
  8061. static inline u64 NIXX_AF_TL4X_SHAPE(u64 a)
  8062. __attribute__ ((pure, always_inline));
  8063. static inline u64 NIXX_AF_TL4X_SHAPE(u64 a)
  8064. {
  8065. return 0x1210 + 0x10000 * a;
  8066. }
  8067. /**
  8068. * Register (RVU_PF_BAR0) nix#_af_tl4#_shape_state
  8069. *
  8070. * NIX AF Transmit Level 4 Shaping State Registers This register has the
  8071. * same bit fields as NIX_AF_TL2()_SHAPE_STATE. This register must not be
  8072. * written during normal operation.
  8073. */
  8074. union nixx_af_tl4x_shape_state {
  8075. u64 u;
  8076. struct nixx_af_tl4x_shape_state_s {
  8077. u64 cir_accum : 26;
  8078. u64 pir_accum : 26;
  8079. u64 color : 2;
  8080. u64 reserved_54_63 : 10;
  8081. } s;
  8082. /* struct nixx_af_tl4x_shape_state_s cn; */
  8083. };
  8084. static inline u64 NIXX_AF_TL4X_SHAPE_STATE(u64 a)
  8085. __attribute__ ((pure, always_inline));
  8086. static inline u64 NIXX_AF_TL4X_SHAPE_STATE(u64 a)
  8087. {
  8088. return 0x1250 + 0x10000 * a;
  8089. }
  8090. /**
  8091. * Register (RVU_PF_BAR0) nix#_af_tl4#_sw_xoff
  8092. *
  8093. * NIX AF Transmit Level 4 Software Controlled XOFF Registers This
  8094. * register has the same bit fields as NIX_AF_TL1()_SW_XOFF
  8095. */
  8096. union nixx_af_tl4x_sw_xoff {
  8097. u64 u;
  8098. struct nixx_af_tl4x_sw_xoff_s {
  8099. u64 xoff : 1;
  8100. u64 drain : 1;
  8101. u64 reserved_2 : 1;
  8102. u64 drain_irq : 1;
  8103. u64 reserved_4_63 : 60;
  8104. } s;
  8105. /* struct nixx_af_tl4x_sw_xoff_s cn; */
  8106. };
  8107. static inline u64 NIXX_AF_TL4X_SW_XOFF(u64 a)
  8108. __attribute__ ((pure, always_inline));
  8109. static inline u64 NIXX_AF_TL4X_SW_XOFF(u64 a)
  8110. {
  8111. return 0x1270 + 0x10000 * a;
  8112. }
  8113. /**
  8114. * Register (RVU_PF_BAR0) nix#_af_tl4#_topology
  8115. *
  8116. * NIX AF Transmit Level 4 Topology Registers
  8117. */
  8118. union nixx_af_tl4x_topology {
  8119. u64 u;
  8120. struct nixx_af_tl4x_topology_s {
  8121. u64 reserved_0 : 1;
  8122. u64 rr_prio : 4;
  8123. u64 reserved_5_31 : 27;
  8124. u64 prio_anchor : 9;
  8125. u64 reserved_41_63 : 23;
  8126. } s;
  8127. /* struct nixx_af_tl4x_topology_s cn; */
  8128. };
  8129. static inline u64 NIXX_AF_TL4X_TOPOLOGY(u64 a)
  8130. __attribute__ ((pure, always_inline));
  8131. static inline u64 NIXX_AF_TL4X_TOPOLOGY(u64 a)
  8132. {
  8133. return 0x1280 + 0x10000 * a;
  8134. }
  8135. /**
  8136. * Register (RVU_PF_BAR0) nix#_af_tl4#_yellow
  8137. *
  8138. * INTERNAL: NIX Transmit Level 4 Yellow State Debug Register This
  8139. * register has the same bit fields as NIX_AF_TL3()_YELLOW
  8140. */
  8141. union nixx_af_tl4x_yellow {
  8142. u64 u;
  8143. struct nixx_af_tl4x_yellow_s {
  8144. u64 tail : 9;
  8145. u64 reserved_9 : 1;
  8146. u64 head : 9;
  8147. u64 reserved_19_63 : 45;
  8148. } s;
  8149. /* struct nixx_af_tl4x_yellow_s cn; */
  8150. };
  8151. static inline u64 NIXX_AF_TL4X_YELLOW(u64 a)
  8152. __attribute__ ((pure, always_inline));
  8153. static inline u64 NIXX_AF_TL4X_YELLOW(u64 a)
  8154. {
  8155. return 0x12a0 + 0x10000 * a;
  8156. }
  8157. /**
  8158. * Register (RVU_PF_BAR0) nix#_af_tl4_const
  8159. *
  8160. * NIX AF Transmit Level 4 Constants Register This register contains
  8161. * constants for software discovery.
  8162. */
  8163. union nixx_af_tl4_const {
  8164. u64 u;
  8165. struct nixx_af_tl4_const_s {
  8166. u64 count : 16;
  8167. u64 reserved_16_63 : 48;
  8168. } s;
  8169. /* struct nixx_af_tl4_const_s cn; */
  8170. };
  8171. static inline u64 NIXX_AF_TL4_CONST(void)
  8172. __attribute__ ((pure, always_inline));
  8173. static inline u64 NIXX_AF_TL4_CONST(void)
  8174. {
  8175. return 0x88;
  8176. }
  8177. /**
  8178. * Register (RVU_PF_BAR0) nix#_af_tx_link#_expr_credit
  8179. *
  8180. * INTERNAL: NIX AF Transmit Link Express Credit Registers Internal:
  8181. * 802.3br frame preemption/express path is defeatured. Old definition:
  8182. * These registers track credits per link for express packets that may
  8183. * potentially preempt normal packets. Link index enumerated by
  8184. * NIX_LINK_E.
  8185. */
  8186. union nixx_af_tx_linkx_expr_credit {
  8187. u64 u;
  8188. struct nixx_af_tx_linkx_expr_credit_s {
  8189. u64 reserved_0 : 1;
  8190. u64 cc_enable : 1;
  8191. u64 cc_packet_cnt : 10;
  8192. u64 cc_unit_cnt : 20;
  8193. u64 reserved_32_63 : 32;
  8194. } s;
  8195. /* struct nixx_af_tx_linkx_expr_credit_s cn; */
  8196. };
  8197. static inline u64 NIXX_AF_TX_LINKX_EXPR_CREDIT(u64 a)
  8198. __attribute__ ((pure, always_inline));
  8199. static inline u64 NIXX_AF_TX_LINKX_EXPR_CREDIT(u64 a)
  8200. {
  8201. return 0xa10 + 0x10000 * a;
  8202. }
  8203. /**
  8204. * Register (RVU_PF_BAR0) nix#_af_tx_link#_hw_xoff
  8205. *
  8206. * NIX AF Transmit Link Hardware Controlled XOFF Registers Link index
  8207. * enumerated by NIX_LINK_E.
  8208. */
  8209. union nixx_af_tx_linkx_hw_xoff {
  8210. u64 u;
  8211. struct nixx_af_tx_linkx_hw_xoff_s {
  8212. u64 chan_xoff : 64;
  8213. } s;
  8214. /* struct nixx_af_tx_linkx_hw_xoff_s cn; */
  8215. };
  8216. static inline u64 NIXX_AF_TX_LINKX_HW_XOFF(u64 a)
  8217. __attribute__ ((pure, always_inline));
  8218. static inline u64 NIXX_AF_TX_LINKX_HW_XOFF(u64 a)
  8219. {
  8220. return 0xa30 + 0x10000 * a;
  8221. }
  8222. /**
  8223. * Register (RVU_PF_BAR0) nix#_af_tx_link#_norm_credit
  8224. *
  8225. * NIX AF Transmit Link Normal Credit Registers These registers track
  8226. * credits per link for normal packets sent to CGX and LBK. Link index
  8227. * enumerated by NIX_LINK_E.
  8228. */
  8229. union nixx_af_tx_linkx_norm_credit {
  8230. u64 u;
  8231. struct nixx_af_tx_linkx_norm_credit_s {
  8232. u64 reserved_0 : 1;
  8233. u64 cc_enable : 1;
  8234. u64 cc_packet_cnt : 10;
  8235. u64 cc_unit_cnt : 20;
  8236. u64 reserved_32_63 : 32;
  8237. } s;
  8238. /* struct nixx_af_tx_linkx_norm_credit_s cn; */
  8239. };
  8240. static inline u64 NIXX_AF_TX_LINKX_NORM_CREDIT(u64 a)
  8241. __attribute__ ((pure, always_inline));
  8242. static inline u64 NIXX_AF_TX_LINKX_NORM_CREDIT(u64 a)
  8243. {
  8244. return 0xa00 + 0x10000 * a;
  8245. }
  8246. /**
  8247. * Register (RVU_PF_BAR0) nix#_af_tx_link#_sw_xoff
  8248. *
  8249. * INTERNAL: NIX AF Transmit Link Software Controlled XOFF Registers
  8250. * Link index enumerated by NIX_LINK_E. Internal: Defeatured registers.
  8251. * Software should instead use NIX_AF_TL3()_SW_XOFF registers when
  8252. * NIX_AF_PSE_CHANNEL_LEVEL[BP_LEVEL] is set and NIX_AF_TL2()_SW_XOFF
  8253. * registers when NIX_AF_PSE_CHANNEL_LEVEL[BP_LEVEL] is clear.
  8254. */
  8255. union nixx_af_tx_linkx_sw_xoff {
  8256. u64 u;
  8257. struct nixx_af_tx_linkx_sw_xoff_s {
  8258. u64 chan_xoff : 64;
  8259. } s;
  8260. /* struct nixx_af_tx_linkx_sw_xoff_s cn; */
  8261. };
  8262. static inline u64 NIXX_AF_TX_LINKX_SW_XOFF(u64 a)
  8263. __attribute__ ((pure, always_inline));
  8264. static inline u64 NIXX_AF_TX_LINKX_SW_XOFF(u64 a)
  8265. {
  8266. return 0xa20 + 0x10000 * a;
  8267. }
  8268. /**
  8269. * Register (RVU_PF_BAR0) nix#_af_tx_mcast#
  8270. *
  8271. * NIX AF Transmit Multicast Registers These registers access transmit
  8272. * multicast table entries used to specify multicast replication lists.
  8273. * Each list consists of linked entries with [EOL] = 1 in the last entry.
  8274. * A transmit packet is multicast when the action returned by NPC has
  8275. * NIX_TX_ACTION_S[OP] = NIX_TX_ACTIONOP_E::MCAST. NIX_TX_ACTION_S[INDEX]
  8276. * points to the start of the multicast replication list, and [EOL] = 1
  8277. * indicates the end of list.
  8278. */
  8279. union nixx_af_tx_mcastx {
  8280. u64 u;
  8281. struct nixx_af_tx_mcastx_s {
  8282. u64 channel : 12;
  8283. u64 eol : 1;
  8284. u64 reserved_13_15 : 3;
  8285. u64 next : 16;
  8286. u64 reserved_32_63 : 32;
  8287. } s;
  8288. /* struct nixx_af_tx_mcastx_s cn; */
  8289. };
  8290. static inline u64 NIXX_AF_TX_MCASTX(u64 a)
  8291. __attribute__ ((pure, always_inline));
  8292. static inline u64 NIXX_AF_TX_MCASTX(u64 a)
  8293. {
  8294. return 0x1900 + 0x8000 * a;
  8295. }
  8296. /**
  8297. * Register (RVU_PF_BAR0) nix#_af_tx_npc_capture_config
  8298. *
  8299. * NIX AF Transmit NPC Response Capture Configuration Register Configures
  8300. * the NPC response capture logic for transmit packets. When enabled,
  8301. * allows NPC responses for selected packets to be captured in
  8302. * NIX_AF_TX_NPC_CAPTURE_INFO and NIX_AF_TX_NPC_CAPTURE_RESP().
  8303. */
  8304. union nixx_af_tx_npc_capture_config {
  8305. u64 u;
  8306. struct nixx_af_tx_npc_capture_config_s {
  8307. u64 en : 1;
  8308. u64 continuous : 1;
  8309. u64 lso_segnum_en : 1;
  8310. u64 sqe_id_en : 1;
  8311. u64 sq_id_en : 1;
  8312. u64 lf_id_en : 1;
  8313. u64 reserved_6_11 : 6;
  8314. u64 lso_segnum : 8;
  8315. u64 sqe_id : 16;
  8316. u64 sq_id : 20;
  8317. u64 lf_id : 8;
  8318. } s;
  8319. /* struct nixx_af_tx_npc_capture_config_s cn; */
  8320. };
  8321. static inline u64 NIXX_AF_TX_NPC_CAPTURE_CONFIG(void)
  8322. __attribute__ ((pure, always_inline));
  8323. static inline u64 NIXX_AF_TX_NPC_CAPTURE_CONFIG(void)
  8324. {
  8325. return 0x660;
  8326. }
  8327. /**
  8328. * Register (RVU_PF_BAR0) nix#_af_tx_npc_capture_info
  8329. *
  8330. * NIX AF Transmit NPC Response Capture Information Register This
  8331. * register contains captured NPC response information for a transmit
  8332. * packet. See NIX_AF_TX_NPC_CAPTURE_CONFIG.
  8333. */
  8334. union nixx_af_tx_npc_capture_info {
  8335. u64 u;
  8336. struct nixx_af_tx_npc_capture_info_s {
  8337. u64 vld : 1;
  8338. u64 reserved_1_11 : 11;
  8339. u64 lso_segnum : 8;
  8340. u64 sqe_id : 16;
  8341. u64 sq_id : 20;
  8342. u64 lf_id : 8;
  8343. } s;
  8344. /* struct nixx_af_tx_npc_capture_info_s cn; */
  8345. };
  8346. static inline u64 NIXX_AF_TX_NPC_CAPTURE_INFO(void)
  8347. __attribute__ ((pure, always_inline));
  8348. static inline u64 NIXX_AF_TX_NPC_CAPTURE_INFO(void)
  8349. {
  8350. return 0x668;
  8351. }
  8352. /**
  8353. * Register (RVU_PF_BAR0) nix#_af_tx_npc_capture_resp#
  8354. *
  8355. * NIX AF Transmit NPC Capture Response Registers These registers contain
  8356. * the captured NPC response for a transmit packet when
  8357. * NIX_AF_TX_NPC_CAPTURE_INFO[VLD] is set. See also
  8358. * NIX_AF_TX_NPC_CAPTURE_CONFIG.
  8359. */
  8360. union nixx_af_tx_npc_capture_respx {
  8361. u64 u;
  8362. struct nixx_af_tx_npc_capture_respx_s {
  8363. u64 data : 64;
  8364. } s;
  8365. /* struct nixx_af_tx_npc_capture_respx_s cn; */
  8366. };
  8367. static inline u64 NIXX_AF_TX_NPC_CAPTURE_RESPX(u64 a)
  8368. __attribute__ ((pure, always_inline));
  8369. static inline u64 NIXX_AF_TX_NPC_CAPTURE_RESPX(u64 a)
  8370. {
  8371. return 0x680 + 8 * a;
  8372. }
  8373. /**
  8374. * Register (RVU_PF_BAR0) nix#_af_tx_tstmp_cfg
  8375. *
  8376. * NIX AF Transmit Timestamp Configuration Register
  8377. */
  8378. union nixx_af_tx_tstmp_cfg {
  8379. u64 u;
  8380. struct nixx_af_tx_tstmp_cfg_s {
  8381. u64 tstmp_wd_period : 4;
  8382. u64 reserved_4_7 : 4;
  8383. u64 express : 16;
  8384. u64 reserved_24_63 : 40;
  8385. } s;
  8386. /* struct nixx_af_tx_tstmp_cfg_s cn; */
  8387. };
  8388. static inline u64 NIXX_AF_TX_TSTMP_CFG(void)
  8389. __attribute__ ((pure, always_inline));
  8390. static inline u64 NIXX_AF_TX_TSTMP_CFG(void)
  8391. {
  8392. return 0xc0;
  8393. }
  8394. /**
  8395. * Register (RVU_PF_BAR0) nix#_af_tx_vtag_def#_ctl
  8396. *
  8397. * NIX AF Transmit Vtag Definition Control Registers The transmit Vtag
  8398. * definition table specifies Vtag layers (e.g. VLAN, E-TAG) to
  8399. * optionally insert or replace in the TX packet header. Indexed by
  8400. * NIX_TX_VTAG_ACTION_S[VTAG*_DEF].
  8401. */
  8402. union nixx_af_tx_vtag_defx_ctl {
  8403. u64 u;
  8404. struct nixx_af_tx_vtag_defx_ctl_s {
  8405. u64 size : 1;
  8406. u64 reserved_1_63 : 63;
  8407. } s;
  8408. /* struct nixx_af_tx_vtag_defx_ctl_s cn; */
  8409. };
  8410. static inline u64 NIXX_AF_TX_VTAG_DEFX_CTL(u64 a)
  8411. __attribute__ ((pure, always_inline));
  8412. static inline u64 NIXX_AF_TX_VTAG_DEFX_CTL(u64 a)
  8413. {
  8414. return 0x1a00 + 0x10000 * a;
  8415. }
  8416. /**
  8417. * Register (RVU_PF_BAR0) nix#_af_tx_vtag_def#_data
  8418. *
  8419. * NIX AF Transmit Vtag Definition Data Registers See
  8420. * NIX_AF_TX_VTAG_DEF()_CTL.
  8421. */
  8422. union nixx_af_tx_vtag_defx_data {
  8423. u64 u;
  8424. struct nixx_af_tx_vtag_defx_data_s {
  8425. u64 data : 64;
  8426. } s;
  8427. /* struct nixx_af_tx_vtag_defx_data_s cn; */
  8428. };
  8429. static inline u64 NIXX_AF_TX_VTAG_DEFX_DATA(u64 a)
  8430. __attribute__ ((pure, always_inline));
  8431. static inline u64 NIXX_AF_TX_VTAG_DEFX_DATA(u64 a)
  8432. {
  8433. return 0x1a10 + 0x10000 * a;
  8434. }
  8435. /**
  8436. * Register (RVU_PFVF_BAR2) nix#_lf_cfg
  8437. *
  8438. * NIX LF Configuration Register
  8439. */
  8440. union nixx_lf_cfg {
  8441. u64 u;
  8442. struct nixx_lf_cfg_s {
  8443. u64 tcp_timer_int_ena : 1;
  8444. u64 reserved_1_63 : 63;
  8445. } s;
  8446. /* struct nixx_lf_cfg_s cn; */
  8447. };
  8448. static inline u64 NIXX_LF_CFG(void)
  8449. __attribute__ ((pure, always_inline));
  8450. static inline u64 NIXX_LF_CFG(void)
  8451. {
  8452. return 0x100;
  8453. }
  8454. /**
  8455. * Register (RVU_PFVF_BAR2) nix#_lf_cint#_cnt
  8456. *
  8457. * NIX LF Completion Interrupt Count Registers
  8458. */
  8459. union nixx_lf_cintx_cnt {
  8460. u64 u;
  8461. struct nixx_lf_cintx_cnt_s {
  8462. u64 ecount : 32;
  8463. u64 qcount : 16;
  8464. u64 reserved_48_63 : 16;
  8465. } s;
  8466. /* struct nixx_lf_cintx_cnt_s cn; */
  8467. };
  8468. static inline u64 NIXX_LF_CINTX_CNT(u64 a)
  8469. __attribute__ ((pure, always_inline));
  8470. static inline u64 NIXX_LF_CINTX_CNT(u64 a)
  8471. {
  8472. return 0xd00 + 0x1000 * a;
  8473. }
  8474. /**
  8475. * Register (RVU_PFVF_BAR2) nix#_lf_cint#_ena_w1c
  8476. *
  8477. * NIX LF Completion Interrupt Enable Clear Registers This register
  8478. * clears interrupt enable bits.
  8479. */
  8480. union nixx_lf_cintx_ena_w1c {
  8481. u64 u;
  8482. struct nixx_lf_cintx_ena_w1c_s {
  8483. u64 intr : 1;
  8484. u64 reserved_1_63 : 63;
  8485. } s;
  8486. /* struct nixx_lf_cintx_ena_w1c_s cn; */
  8487. };
  8488. static inline u64 NIXX_LF_CINTX_ENA_W1C(u64 a)
  8489. __attribute__ ((pure, always_inline));
  8490. static inline u64 NIXX_LF_CINTX_ENA_W1C(u64 a)
  8491. {
  8492. return 0xd50 + 0x1000 * a;
  8493. }
  8494. /**
  8495. * Register (RVU_PFVF_BAR2) nix#_lf_cint#_ena_w1s
  8496. *
  8497. * NIX LF Completion Interrupt Enable Set Registers This register sets
  8498. * interrupt enable bits.
  8499. */
  8500. union nixx_lf_cintx_ena_w1s {
  8501. u64 u;
  8502. struct nixx_lf_cintx_ena_w1s_s {
  8503. u64 intr : 1;
  8504. u64 reserved_1_63 : 63;
  8505. } s;
  8506. /* struct nixx_lf_cintx_ena_w1s_s cn; */
  8507. };
  8508. static inline u64 NIXX_LF_CINTX_ENA_W1S(u64 a)
  8509. __attribute__ ((pure, always_inline));
  8510. static inline u64 NIXX_LF_CINTX_ENA_W1S(u64 a)
  8511. {
  8512. return 0xd40 + 0x1000 * a;
  8513. }
  8514. /**
  8515. * Register (RVU_PFVF_BAR2) nix#_lf_cint#_int
  8516. *
  8517. * NIX LF Completion Interrupt Registers
  8518. */
  8519. union nixx_lf_cintx_int {
  8520. u64 u;
  8521. struct nixx_lf_cintx_int_s {
  8522. u64 intr : 1;
  8523. u64 reserved_1_63 : 63;
  8524. } s;
  8525. /* struct nixx_lf_cintx_int_s cn; */
  8526. };
  8527. static inline u64 NIXX_LF_CINTX_INT(u64 a)
  8528. __attribute__ ((pure, always_inline));
  8529. static inline u64 NIXX_LF_CINTX_INT(u64 a)
  8530. {
  8531. return 0xd20 + 0x1000 * a;
  8532. }
  8533. /**
  8534. * Register (RVU_PFVF_BAR2) nix#_lf_cint#_int_w1s
  8535. *
  8536. * NIX LF Completion Interrupt Set Registers This register sets interrupt
  8537. * bits.
  8538. */
  8539. union nixx_lf_cintx_int_w1s {
  8540. u64 u;
  8541. struct nixx_lf_cintx_int_w1s_s {
  8542. u64 intr : 1;
  8543. u64 reserved_1_63 : 63;
  8544. } s;
  8545. /* struct nixx_lf_cintx_int_w1s_s cn; */
  8546. };
  8547. static inline u64 NIXX_LF_CINTX_INT_W1S(u64 a)
  8548. __attribute__ ((pure, always_inline));
  8549. static inline u64 NIXX_LF_CINTX_INT_W1S(u64 a)
  8550. {
  8551. return 0xd30 + 0x1000 * a;
  8552. }
  8553. /**
  8554. * Register (RVU_PFVF_BAR2) nix#_lf_cint#_wait
  8555. *
  8556. * NIX LF Completion Interrupt Count Registers
  8557. */
  8558. union nixx_lf_cintx_wait {
  8559. u64 u;
  8560. struct nixx_lf_cintx_wait_s {
  8561. u64 ecount_wait : 32;
  8562. u64 qcount_wait : 16;
  8563. u64 time_wait : 8;
  8564. u64 reserved_56_63 : 8;
  8565. } s;
  8566. /* struct nixx_lf_cintx_wait_s cn; */
  8567. };
  8568. static inline u64 NIXX_LF_CINTX_WAIT(u64 a)
  8569. __attribute__ ((pure, always_inline));
  8570. static inline u64 NIXX_LF_CINTX_WAIT(u64 a)
  8571. {
  8572. return 0xd10 + 0x1000 * a;
  8573. }
  8574. /**
  8575. * Register (RVU_PFVF_BAR2) nix#_lf_cq_op_door
  8576. *
  8577. * NIX LF CQ Doorbell Operation Register A write to this register
  8578. * dequeues CQEs from a CQ ring within the LF. A read is RAZ. RSL
  8579. * accesses to this register are RAZ/WI.
  8580. */
  8581. union nixx_lf_cq_op_door {
  8582. u64 u;
  8583. struct nixx_lf_cq_op_door_s {
  8584. u64 count : 16;
  8585. u64 reserved_16_31 : 16;
  8586. u64 cq : 20;
  8587. u64 reserved_52_63 : 12;
  8588. } s;
  8589. /* struct nixx_lf_cq_op_door_s cn; */
  8590. };
  8591. static inline u64 NIXX_LF_CQ_OP_DOOR(void)
  8592. __attribute__ ((pure, always_inline));
  8593. static inline u64 NIXX_LF_CQ_OP_DOOR(void)
  8594. {
  8595. return 0xb30;
  8596. }
  8597. /**
  8598. * Register (RVU_PFVF_BAR2) nix#_lf_cq_op_int
  8599. *
  8600. * NIX LF Completion Queue Interrupt Operation Register A 64-bit atomic
  8601. * load-and-add to this register reads CQ interrupts and interrupt
  8602. * enables. A write optionally sets or clears interrupts and interrupt
  8603. * enables. A read is RAZ. RSL accesses to this register are RAZ/WI.
  8604. */
  8605. union nixx_lf_cq_op_int {
  8606. u64 u;
  8607. struct nixx_lf_cq_op_int_s {
  8608. u64 cq_err_int : 8;
  8609. u64 cq_err_int_ena : 8;
  8610. u64 reserved_16_41 : 26;
  8611. u64 op_err : 1;
  8612. u64 setop : 1;
  8613. u64 cq : 20;
  8614. } s;
  8615. /* struct nixx_lf_cq_op_int_s cn; */
  8616. };
  8617. static inline u64 NIXX_LF_CQ_OP_INT(void)
  8618. __attribute__ ((pure, always_inline));
  8619. static inline u64 NIXX_LF_CQ_OP_INT(void)
  8620. {
  8621. return 0xb00;
  8622. }
  8623. /**
  8624. * Register (RVU_PFVF_BAR2) nix#_lf_cq_op_status
  8625. *
  8626. * NIX LF Completion Queue Status Operation Register A 64-bit atomic
  8627. * load-and-add to this register reads NIX_CQ_CTX_S[HEAD,TAIL]. The
  8628. * atomic write data has format NIX_OP_Q_WDATA_S and selects the CQ
  8629. * within LF. All other accesses to this register (e.g. reads and
  8630. * writes) are RAZ/WI. RSL accesses to this register are RAZ/WI.
  8631. */
  8632. union nixx_lf_cq_op_status {
  8633. u64 u;
  8634. struct nixx_lf_cq_op_status_s {
  8635. u64 tail : 20;
  8636. u64 head : 20;
  8637. u64 reserved_40_45 : 6;
  8638. u64 cq_err : 1;
  8639. u64 reserved_47_62 : 16;
  8640. u64 op_err : 1;
  8641. } s;
  8642. /* struct nixx_lf_cq_op_status_s cn; */
  8643. };
  8644. static inline u64 NIXX_LF_CQ_OP_STATUS(void)
  8645. __attribute__ ((pure, always_inline));
  8646. static inline u64 NIXX_LF_CQ_OP_STATUS(void)
  8647. {
  8648. return 0xb40;
  8649. }
  8650. /**
  8651. * Register (RVU_PFVF_BAR2) nix#_lf_err_int
  8652. *
  8653. * NIX LF Error Interrupt Register
  8654. */
  8655. union nixx_lf_err_int {
  8656. u64 u;
  8657. struct nixx_lf_err_int_s {
  8658. u64 sqb_fault : 1;
  8659. u64 sq_ctx_fault : 1;
  8660. u64 rq_ctx_fault : 1;
  8661. u64 cq_ctx_fault : 1;
  8662. u64 reserved_4 : 1;
  8663. u64 rsse_fault : 1;
  8664. u64 ipsec_dyno_fault : 1;
  8665. u64 sq_disabled : 1;
  8666. u64 sq_oor : 1;
  8667. u64 send_jump_fault : 1;
  8668. u64 send_sg_fault : 1;
  8669. u64 rq_disabled : 1;
  8670. u64 rq_oor : 1;
  8671. u64 rx_wqe_fault : 1;
  8672. u64 rss_err : 1;
  8673. u64 reserved_15_19 : 5;
  8674. u64 dyno_err : 1;
  8675. u64 reserved_21_23 : 3;
  8676. u64 cq_disabled : 1;
  8677. u64 cq_oor : 1;
  8678. u64 reserved_26_27 : 2;
  8679. u64 qint_fault : 1;
  8680. u64 cint_fault : 1;
  8681. u64 reserved_30_63 : 34;
  8682. } s;
  8683. /* struct nixx_lf_err_int_s cn; */
  8684. };
  8685. static inline u64 NIXX_LF_ERR_INT(void)
  8686. __attribute__ ((pure, always_inline));
  8687. static inline u64 NIXX_LF_ERR_INT(void)
  8688. {
  8689. return 0x220;
  8690. }
  8691. /**
  8692. * Register (RVU_PFVF_BAR2) nix#_lf_err_int_ena_w1c
  8693. *
  8694. * NIX LF Error Interrupt Enable Clear Register This register clears
  8695. * interrupt enable bits.
  8696. */
  8697. union nixx_lf_err_int_ena_w1c {
  8698. u64 u;
  8699. struct nixx_lf_err_int_ena_w1c_s {
  8700. u64 sqb_fault : 1;
  8701. u64 sq_ctx_fault : 1;
  8702. u64 rq_ctx_fault : 1;
  8703. u64 cq_ctx_fault : 1;
  8704. u64 reserved_4 : 1;
  8705. u64 rsse_fault : 1;
  8706. u64 ipsec_dyno_fault : 1;
  8707. u64 sq_disabled : 1;
  8708. u64 sq_oor : 1;
  8709. u64 send_jump_fault : 1;
  8710. u64 send_sg_fault : 1;
  8711. u64 rq_disabled : 1;
  8712. u64 rq_oor : 1;
  8713. u64 rx_wqe_fault : 1;
  8714. u64 rss_err : 1;
  8715. u64 reserved_15_19 : 5;
  8716. u64 dyno_err : 1;
  8717. u64 reserved_21_23 : 3;
  8718. u64 cq_disabled : 1;
  8719. u64 cq_oor : 1;
  8720. u64 reserved_26_27 : 2;
  8721. u64 qint_fault : 1;
  8722. u64 cint_fault : 1;
  8723. u64 reserved_30_63 : 34;
  8724. } s;
  8725. /* struct nixx_lf_err_int_ena_w1c_s cn; */
  8726. };
  8727. static inline u64 NIXX_LF_ERR_INT_ENA_W1C(void)
  8728. __attribute__ ((pure, always_inline));
  8729. static inline u64 NIXX_LF_ERR_INT_ENA_W1C(void)
  8730. {
  8731. return 0x230;
  8732. }
  8733. /**
  8734. * Register (RVU_PFVF_BAR2) nix#_lf_err_int_ena_w1s
  8735. *
  8736. * NIX LF Error Interrupt Enable Set Register This register sets
  8737. * interrupt enable bits.
  8738. */
  8739. union nixx_lf_err_int_ena_w1s {
  8740. u64 u;
  8741. struct nixx_lf_err_int_ena_w1s_s {
  8742. u64 sqb_fault : 1;
  8743. u64 sq_ctx_fault : 1;
  8744. u64 rq_ctx_fault : 1;
  8745. u64 cq_ctx_fault : 1;
  8746. u64 reserved_4 : 1;
  8747. u64 rsse_fault : 1;
  8748. u64 ipsec_dyno_fault : 1;
  8749. u64 sq_disabled : 1;
  8750. u64 sq_oor : 1;
  8751. u64 send_jump_fault : 1;
  8752. u64 send_sg_fault : 1;
  8753. u64 rq_disabled : 1;
  8754. u64 rq_oor : 1;
  8755. u64 rx_wqe_fault : 1;
  8756. u64 rss_err : 1;
  8757. u64 reserved_15_19 : 5;
  8758. u64 dyno_err : 1;
  8759. u64 reserved_21_23 : 3;
  8760. u64 cq_disabled : 1;
  8761. u64 cq_oor : 1;
  8762. u64 reserved_26_27 : 2;
  8763. u64 qint_fault : 1;
  8764. u64 cint_fault : 1;
  8765. u64 reserved_30_63 : 34;
  8766. } s;
  8767. /* struct nixx_lf_err_int_ena_w1s_s cn; */
  8768. };
  8769. static inline u64 NIXX_LF_ERR_INT_ENA_W1S(void)
  8770. __attribute__ ((pure, always_inline));
  8771. static inline u64 NIXX_LF_ERR_INT_ENA_W1S(void)
  8772. {
  8773. return 0x238;
  8774. }
  8775. /**
  8776. * Register (RVU_PFVF_BAR2) nix#_lf_err_int_w1s
  8777. *
  8778. * NIX LF Error Interrupt Set Register This register sets interrupt bits.
  8779. */
  8780. union nixx_lf_err_int_w1s {
  8781. u64 u;
  8782. struct nixx_lf_err_int_w1s_s {
  8783. u64 sqb_fault : 1;
  8784. u64 sq_ctx_fault : 1;
  8785. u64 rq_ctx_fault : 1;
  8786. u64 cq_ctx_fault : 1;
  8787. u64 reserved_4 : 1;
  8788. u64 rsse_fault : 1;
  8789. u64 ipsec_dyno_fault : 1;
  8790. u64 sq_disabled : 1;
  8791. u64 sq_oor : 1;
  8792. u64 send_jump_fault : 1;
  8793. u64 send_sg_fault : 1;
  8794. u64 rq_disabled : 1;
  8795. u64 rq_oor : 1;
  8796. u64 rx_wqe_fault : 1;
  8797. u64 rss_err : 1;
  8798. u64 reserved_15_19 : 5;
  8799. u64 dyno_err : 1;
  8800. u64 reserved_21_23 : 3;
  8801. u64 cq_disabled : 1;
  8802. u64 cq_oor : 1;
  8803. u64 reserved_26_27 : 2;
  8804. u64 qint_fault : 1;
  8805. u64 cint_fault : 1;
  8806. u64 reserved_30_63 : 34;
  8807. } s;
  8808. /* struct nixx_lf_err_int_w1s_s cn; */
  8809. };
  8810. static inline u64 NIXX_LF_ERR_INT_W1S(void)
  8811. __attribute__ ((pure, always_inline));
  8812. static inline u64 NIXX_LF_ERR_INT_W1S(void)
  8813. {
  8814. return 0x228;
  8815. }
  8816. /**
  8817. * Register (RVU_PFVF_BAR2) nix#_lf_gint
  8818. *
  8819. * NIX LF General Interrupt Register
  8820. */
  8821. union nixx_lf_gint {
  8822. u64 u;
  8823. struct nixx_lf_gint_s {
  8824. u64 drop : 1;
  8825. u64 tcp_timer : 1;
  8826. u64 reserved_2_63 : 62;
  8827. } s;
  8828. /* struct nixx_lf_gint_s cn; */
  8829. };
  8830. static inline u64 NIXX_LF_GINT(void)
  8831. __attribute__ ((pure, always_inline));
  8832. static inline u64 NIXX_LF_GINT(void)
  8833. {
  8834. return 0x200;
  8835. }
  8836. /**
  8837. * Register (RVU_PFVF_BAR2) nix#_lf_gint_ena_w1c
  8838. *
  8839. * NIX LF General Interrupt Enable Clear Register This register clears
  8840. * interrupt enable bits.
  8841. */
  8842. union nixx_lf_gint_ena_w1c {
  8843. u64 u;
  8844. struct nixx_lf_gint_ena_w1c_s {
  8845. u64 drop : 1;
  8846. u64 tcp_timer : 1;
  8847. u64 reserved_2_63 : 62;
  8848. } s;
  8849. /* struct nixx_lf_gint_ena_w1c_s cn; */
  8850. };
  8851. static inline u64 NIXX_LF_GINT_ENA_W1C(void)
  8852. __attribute__ ((pure, always_inline));
  8853. static inline u64 NIXX_LF_GINT_ENA_W1C(void)
  8854. {
  8855. return 0x210;
  8856. }
  8857. /**
  8858. * Register (RVU_PFVF_BAR2) nix#_lf_gint_ena_w1s
  8859. *
  8860. * NIX LF General Interrupt Enable Set Register This register sets
  8861. * interrupt enable bits.
  8862. */
  8863. union nixx_lf_gint_ena_w1s {
  8864. u64 u;
  8865. struct nixx_lf_gint_ena_w1s_s {
  8866. u64 drop : 1;
  8867. u64 tcp_timer : 1;
  8868. u64 reserved_2_63 : 62;
  8869. } s;
  8870. /* struct nixx_lf_gint_ena_w1s_s cn; */
  8871. };
  8872. static inline u64 NIXX_LF_GINT_ENA_W1S(void)
  8873. __attribute__ ((pure, always_inline));
  8874. static inline u64 NIXX_LF_GINT_ENA_W1S(void)
  8875. {
  8876. return 0x218;
  8877. }
  8878. /**
  8879. * Register (RVU_PFVF_BAR2) nix#_lf_gint_w1s
  8880. *
  8881. * NIX LF General Interrupt Set Register This register sets interrupt
  8882. * bits.
  8883. */
  8884. union nixx_lf_gint_w1s {
  8885. u64 u;
  8886. struct nixx_lf_gint_w1s_s {
  8887. u64 drop : 1;
  8888. u64 tcp_timer : 1;
  8889. u64 reserved_2_63 : 62;
  8890. } s;
  8891. /* struct nixx_lf_gint_w1s_s cn; */
  8892. };
  8893. static inline u64 NIXX_LF_GINT_W1S(void)
  8894. __attribute__ ((pure, always_inline));
  8895. static inline u64 NIXX_LF_GINT_W1S(void)
  8896. {
  8897. return 0x208;
  8898. }
  8899. /**
  8900. * Register (RVU_PFVF_BAR2) nix#_lf_mnq_err_dbg
  8901. *
  8902. * NIX LF Meta-descriptor Enqueue Error Debug Register This register
  8903. * captures debug info for an error detected during send meta-descriptor
  8904. * enqueue from an SQ to an SMQ. Hardware sets [VALID] when the debug
  8905. * info is captured, and subsequent errors are not captured until
  8906. * software clears [VALID] by writing a one to it.
  8907. */
  8908. union nixx_lf_mnq_err_dbg {
  8909. u64 u;
  8910. struct nixx_lf_mnq_err_dbg_s {
  8911. u64 errcode : 8;
  8912. u64 sq : 20;
  8913. u64 sqe_id : 16;
  8914. u64 valid : 1;
  8915. u64 reserved_45_63 : 19;
  8916. } s;
  8917. /* struct nixx_lf_mnq_err_dbg_s cn; */
  8918. };
  8919. static inline u64 NIXX_LF_MNQ_ERR_DBG(void)
  8920. __attribute__ ((pure, always_inline));
  8921. static inline u64 NIXX_LF_MNQ_ERR_DBG(void)
  8922. {
  8923. return 0x270;
  8924. }
  8925. /**
  8926. * Register (RVU_PFVF_BAR2) nix#_lf_op_ipsec_dyno_cnt
  8927. *
  8928. * INTERNAL: NIX LF IPSEC Dynamic Ordering Counter Operation Register
  8929. * Internal: Not used; no IPSEC fast-path. All accesses are RAZ/WI.
  8930. */
  8931. union nixx_lf_op_ipsec_dyno_cnt {
  8932. u64 u;
  8933. struct nixx_lf_op_ipsec_dyno_cnt_s {
  8934. u64 count : 32;
  8935. u64 reserved_32_46 : 15;
  8936. u64 storeop : 1;
  8937. u64 dyno_sel : 15;
  8938. u64 op_err : 1;
  8939. } s;
  8940. /* struct nixx_lf_op_ipsec_dyno_cnt_s cn; */
  8941. };
  8942. static inline u64 NIXX_LF_OP_IPSEC_DYNO_CNT(void)
  8943. __attribute__ ((pure, always_inline));
  8944. static inline u64 NIXX_LF_OP_IPSEC_DYNO_CNT(void)
  8945. {
  8946. return 0x980;
  8947. }
  8948. /**
  8949. * Register (RVU_PFVF_BAR2) nix#_lf_op_send#
  8950. *
  8951. * NIX LF Send Operation Registers An LMTST (or large store from CPT) to
  8952. * this address enqueues one or more SQEs to a send queue.
  8953. * NIX_SEND_HDR_S[SQ] in the first SQE selects the send queue.The maximum
  8954. * size of each SQE is specified by NIX_SQ_CTX_S[MAX_SQE_SIZE]. A read
  8955. * to this address is RAZ. An RSL access to this address will fault.
  8956. * The endianness of the instruction write data is controlled by
  8957. * NIX_AF_LF()_CFG[BE]. When a NIX_SEND_JUMP_S is not present in the
  8958. * SQE, the SQE consists of the entire send descriptor. When a
  8959. * NIX_SEND_JUMP_S is present in the SQE, the SQE must contain exactly
  8960. * the portion of the send descriptor up to and including the
  8961. * NIX_SEND_JUMP_S, and the remainder of the send descriptor must be at
  8962. * LF IOVA NIX_SEND_JUMP_S[ADDR] in LLC/DRAM. Software must ensure that
  8963. * all LLC/DRAM locations that will be referenced by NIX while processing
  8964. * this descriptor, including all packet data and post-jump
  8965. * subdescriptors contain the latest updates before issuing the LMTST. A
  8966. * DMB instruction may be required prior to the LMTST to ensure this. A
  8967. * DMB following the LMTST may be useful if SQ descriptor ordering
  8968. * matters and more than one CPU core is simultaneously enqueueing to the
  8969. * same SQ.
  8970. */
  8971. union nixx_lf_op_sendx {
  8972. u64 u;
  8973. struct nixx_lf_op_sendx_s {
  8974. u64 data : 64;
  8975. } s;
  8976. /* struct nixx_lf_op_sendx_s cn; */
  8977. };
  8978. static inline u64 NIXX_LF_OP_SENDX(u64 a)
  8979. __attribute__ ((pure, always_inline));
  8980. static inline u64 NIXX_LF_OP_SENDX(u64 a)
  8981. {
  8982. return 0x800 + 8 * a;
  8983. }
  8984. /**
  8985. * Register (RVU_PFVF_BAR2) nix#_lf_qint#_cnt
  8986. *
  8987. * NIX LF Queue Interrupt Count Registers
  8988. */
  8989. union nixx_lf_qintx_cnt {
  8990. u64 u;
  8991. struct nixx_lf_qintx_cnt_s {
  8992. u64 count : 22;
  8993. u64 reserved_22_63 : 42;
  8994. } s;
  8995. /* struct nixx_lf_qintx_cnt_s cn; */
  8996. };
  8997. static inline u64 NIXX_LF_QINTX_CNT(u64 a)
  8998. __attribute__ ((pure, always_inline));
  8999. static inline u64 NIXX_LF_QINTX_CNT(u64 a)
  9000. {
  9001. return 0xc00 + 0x1000 * a;
  9002. }
  9003. /**
  9004. * Register (RVU_PFVF_BAR2) nix#_lf_qint#_ena_w1c
  9005. *
  9006. * NIX LF Queue Interrupt Enable Clear Registers This register clears
  9007. * interrupt enable bits.
  9008. */
  9009. union nixx_lf_qintx_ena_w1c {
  9010. u64 u;
  9011. struct nixx_lf_qintx_ena_w1c_s {
  9012. u64 intr : 1;
  9013. u64 reserved_1_63 : 63;
  9014. } s;
  9015. /* struct nixx_lf_qintx_ena_w1c_s cn; */
  9016. };
  9017. static inline u64 NIXX_LF_QINTX_ENA_W1C(u64 a)
  9018. __attribute__ ((pure, always_inline));
  9019. static inline u64 NIXX_LF_QINTX_ENA_W1C(u64 a)
  9020. {
  9021. return 0xc30 + 0x1000 * a;
  9022. }
  9023. /**
  9024. * Register (RVU_PFVF_BAR2) nix#_lf_qint#_ena_w1s
  9025. *
  9026. * NIX LF Queue Interrupt Enable Set Registers This register sets
  9027. * interrupt enable bits.
  9028. */
  9029. union nixx_lf_qintx_ena_w1s {
  9030. u64 u;
  9031. struct nixx_lf_qintx_ena_w1s_s {
  9032. u64 intr : 1;
  9033. u64 reserved_1_63 : 63;
  9034. } s;
  9035. /* struct nixx_lf_qintx_ena_w1s_s cn; */
  9036. };
  9037. static inline u64 NIXX_LF_QINTX_ENA_W1S(u64 a)
  9038. __attribute__ ((pure, always_inline));
  9039. static inline u64 NIXX_LF_QINTX_ENA_W1S(u64 a)
  9040. {
  9041. return 0xc20 + 0x1000 * a;
  9042. }
  9043. /**
  9044. * Register (RVU_PFVF_BAR2) nix#_lf_qint#_int
  9045. *
  9046. * NIX LF Queue Interrupt Registers
  9047. */
  9048. union nixx_lf_qintx_int {
  9049. u64 u;
  9050. struct nixx_lf_qintx_int_s {
  9051. u64 intr : 1;
  9052. u64 reserved_1_63 : 63;
  9053. } s;
  9054. /* struct nixx_lf_qintx_int_s cn; */
  9055. };
  9056. static inline u64 NIXX_LF_QINTX_INT(u64 a)
  9057. __attribute__ ((pure, always_inline));
  9058. static inline u64 NIXX_LF_QINTX_INT(u64 a)
  9059. {
  9060. return 0xc10 + 0x1000 * a;
  9061. }
  9062. /**
  9063. * Register (RVU_PFVF_BAR2) nix#_lf_qint#_int_w1s
  9064. *
  9065. * INTERNAL: NIX LF Queue Interrupt Set Registers
  9066. */
  9067. union nixx_lf_qintx_int_w1s {
  9068. u64 u;
  9069. struct nixx_lf_qintx_int_w1s_s {
  9070. u64 intr : 1;
  9071. u64 reserved_1_63 : 63;
  9072. } s;
  9073. /* struct nixx_lf_qintx_int_w1s_s cn; */
  9074. };
  9075. static inline u64 NIXX_LF_QINTX_INT_W1S(u64 a)
  9076. __attribute__ ((pure, always_inline));
  9077. static inline u64 NIXX_LF_QINTX_INT_W1S(u64 a)
  9078. {
  9079. return 0xc18 + 0x1000 * a;
  9080. }
  9081. /**
  9082. * Register (RVU_PFVF_BAR2) nix#_lf_ras
  9083. *
  9084. * NIX LF RAS Interrupt Register
  9085. */
  9086. union nixx_lf_ras {
  9087. u64 u;
  9088. struct nixx_lf_ras_s {
  9089. u64 sqb_poison : 1;
  9090. u64 sq_ctx_poison : 1;
  9091. u64 rq_ctx_poison : 1;
  9092. u64 cq_ctx_poison : 1;
  9093. u64 reserved_4 : 1;
  9094. u64 rsse_poison : 1;
  9095. u64 ipsec_dyno_poison : 1;
  9096. u64 send_jump_poison : 1;
  9097. u64 send_sg_poison : 1;
  9098. u64 qint_poison : 1;
  9099. u64 cint_poison : 1;
  9100. u64 reserved_11_63 : 53;
  9101. } s;
  9102. /* struct nixx_lf_ras_s cn; */
  9103. };
  9104. static inline u64 NIXX_LF_RAS(void)
  9105. __attribute__ ((pure, always_inline));
  9106. static inline u64 NIXX_LF_RAS(void)
  9107. {
  9108. return 0x240;
  9109. }
  9110. /**
  9111. * Register (RVU_PFVF_BAR2) nix#_lf_ras_ena_w1c
  9112. *
  9113. * NIX LF RAS Interrupt Enable Clear Register This register clears
  9114. * interrupt enable bits.
  9115. */
  9116. union nixx_lf_ras_ena_w1c {
  9117. u64 u;
  9118. struct nixx_lf_ras_ena_w1c_s {
  9119. u64 sqb_poison : 1;
  9120. u64 sq_ctx_poison : 1;
  9121. u64 rq_ctx_poison : 1;
  9122. u64 cq_ctx_poison : 1;
  9123. u64 reserved_4 : 1;
  9124. u64 rsse_poison : 1;
  9125. u64 ipsec_dyno_poison : 1;
  9126. u64 send_jump_poison : 1;
  9127. u64 send_sg_poison : 1;
  9128. u64 qint_poison : 1;
  9129. u64 cint_poison : 1;
  9130. u64 reserved_11_63 : 53;
  9131. } s;
  9132. /* struct nixx_lf_ras_ena_w1c_s cn; */
  9133. };
  9134. static inline u64 NIXX_LF_RAS_ENA_W1C(void)
  9135. __attribute__ ((pure, always_inline));
  9136. static inline u64 NIXX_LF_RAS_ENA_W1C(void)
  9137. {
  9138. return 0x250;
  9139. }
  9140. /**
  9141. * Register (RVU_PFVF_BAR2) nix#_lf_ras_ena_w1s
  9142. *
  9143. * NIX LF RAS Interrupt Enable Set Register This register sets interrupt
  9144. * enable bits.
  9145. */
  9146. union nixx_lf_ras_ena_w1s {
  9147. u64 u;
  9148. struct nixx_lf_ras_ena_w1s_s {
  9149. u64 sqb_poison : 1;
  9150. u64 sq_ctx_poison : 1;
  9151. u64 rq_ctx_poison : 1;
  9152. u64 cq_ctx_poison : 1;
  9153. u64 reserved_4 : 1;
  9154. u64 rsse_poison : 1;
  9155. u64 ipsec_dyno_poison : 1;
  9156. u64 send_jump_poison : 1;
  9157. u64 send_sg_poison : 1;
  9158. u64 qint_poison : 1;
  9159. u64 cint_poison : 1;
  9160. u64 reserved_11_63 : 53;
  9161. } s;
  9162. /* struct nixx_lf_ras_ena_w1s_s cn; */
  9163. };
  9164. static inline u64 NIXX_LF_RAS_ENA_W1S(void)
  9165. __attribute__ ((pure, always_inline));
  9166. static inline u64 NIXX_LF_RAS_ENA_W1S(void)
  9167. {
  9168. return 0x258;
  9169. }
  9170. /**
  9171. * Register (RVU_PFVF_BAR2) nix#_lf_ras_w1s
  9172. *
  9173. * NIX LF RAS Interrupt Set Register This register sets interrupt bits.
  9174. */
  9175. union nixx_lf_ras_w1s {
  9176. u64 u;
  9177. struct nixx_lf_ras_w1s_s {
  9178. u64 sqb_poison : 1;
  9179. u64 sq_ctx_poison : 1;
  9180. u64 rq_ctx_poison : 1;
  9181. u64 cq_ctx_poison : 1;
  9182. u64 reserved_4 : 1;
  9183. u64 rsse_poison : 1;
  9184. u64 ipsec_dyno_poison : 1;
  9185. u64 send_jump_poison : 1;
  9186. u64 send_sg_poison : 1;
  9187. u64 qint_poison : 1;
  9188. u64 cint_poison : 1;
  9189. u64 reserved_11_63 : 53;
  9190. } s;
  9191. /* struct nixx_lf_ras_w1s_s cn; */
  9192. };
  9193. static inline u64 NIXX_LF_RAS_W1S(void)
  9194. __attribute__ ((pure, always_inline));
  9195. static inline u64 NIXX_LF_RAS_W1S(void)
  9196. {
  9197. return 0x248;
  9198. }
  9199. /**
  9200. * Register (RVU_PFVF_BAR2) nix#_lf_rq_op_drop_octs
  9201. *
  9202. * NIX LF Receive Queue Dropped Octets Operation Register A 64-bit atomic
  9203. * load-and-add to this register reads NIX_RQ_CTX_S[DROP_OCTS]. The
  9204. * atomic write data has format NIX_OP_Q_WDATA_S and selects the RQ
  9205. * within LF. All other accesses to this register (e.g. reads and
  9206. * writes) are RAZ/WI. RSL accesses to this register are RAZ/WI.
  9207. */
  9208. union nixx_lf_rq_op_drop_octs {
  9209. u64 u;
  9210. struct nixx_lf_rq_op_drop_octs_s {
  9211. u64 cnt : 48;
  9212. u64 reserved_48_62 : 15;
  9213. u64 op_err : 1;
  9214. } s;
  9215. /* struct nixx_lf_rq_op_drop_octs_s cn; */
  9216. };
  9217. static inline u64 NIXX_LF_RQ_OP_DROP_OCTS(void)
  9218. __attribute__ ((pure, always_inline));
  9219. static inline u64 NIXX_LF_RQ_OP_DROP_OCTS(void)
  9220. {
  9221. return 0x930;
  9222. }
  9223. /**
  9224. * Register (RVU_PFVF_BAR2) nix#_lf_rq_op_drop_pkts
  9225. *
  9226. * NIX LF Receive Queue Dropped Packets Operation Register A 64-bit
  9227. * atomic load-and-add to this register reads NIX_RQ_CTX_S[DROP_PKTS].
  9228. * The atomic write data has format NIX_OP_Q_WDATA_S and selects the RQ
  9229. * within LF. All other accesses to this register (e.g. reads and
  9230. * writes) are RAZ/WI. RSL accesses to this register are RAZ/WI.
  9231. */
  9232. union nixx_lf_rq_op_drop_pkts {
  9233. u64 u;
  9234. struct nixx_lf_rq_op_drop_pkts_s {
  9235. u64 cnt : 48;
  9236. u64 reserved_48_62 : 15;
  9237. u64 op_err : 1;
  9238. } s;
  9239. /* struct nixx_lf_rq_op_drop_pkts_s cn; */
  9240. };
  9241. static inline u64 NIXX_LF_RQ_OP_DROP_PKTS(void)
  9242. __attribute__ ((pure, always_inline));
  9243. static inline u64 NIXX_LF_RQ_OP_DROP_PKTS(void)
  9244. {
  9245. return 0x940;
  9246. }
  9247. /**
  9248. * Register (RVU_PFVF_BAR2) nix#_lf_rq_op_int
  9249. *
  9250. * NIX LF Receive Queue Interrupt Operation Register A 64-bit atomic
  9251. * load-and-add to this register reads RQ interrupts and interrupt
  9252. * enables. A 64-bit write optionally sets or clears interrupts and
  9253. * interrupt enables. All other accesses to this register (e.g. reads,
  9254. * 128-bit accesses) are RAZ/WI. RSL accesses to this register are
  9255. * RAZ/WI.
  9256. */
  9257. union nixx_lf_rq_op_int {
  9258. u64 u;
  9259. struct nixx_lf_rq_op_int_s {
  9260. u64 rq_int : 8;
  9261. u64 rq_int_ena : 8;
  9262. u64 reserved_16_41 : 26;
  9263. u64 op_err : 1;
  9264. u64 setop : 1;
  9265. u64 rq : 20;
  9266. } s;
  9267. /* struct nixx_lf_rq_op_int_s cn; */
  9268. };
  9269. static inline u64 NIXX_LF_RQ_OP_INT(void)
  9270. __attribute__ ((pure, always_inline));
  9271. static inline u64 NIXX_LF_RQ_OP_INT(void)
  9272. {
  9273. return 0x900;
  9274. }
  9275. /**
  9276. * Register (RVU_PFVF_BAR2) nix#_lf_rq_op_octs
  9277. *
  9278. * NIX LF Receive Queue Octets Operation Register A 64-bit atomic load-
  9279. * and-add to this register reads NIX_RQ_CTX_S[OCTS]. The atomic write
  9280. * data has format NIX_OP_Q_WDATA_S and selects the RQ within LF. All
  9281. * other accesses to this register (e.g. reads and writes) are RAZ/WI.
  9282. * RSL accesses to this register are RAZ/WI.
  9283. */
  9284. union nixx_lf_rq_op_octs {
  9285. u64 u;
  9286. struct nixx_lf_rq_op_octs_s {
  9287. u64 cnt : 48;
  9288. u64 reserved_48_62 : 15;
  9289. u64 op_err : 1;
  9290. } s;
  9291. /* struct nixx_lf_rq_op_octs_s cn; */
  9292. };
  9293. static inline u64 NIXX_LF_RQ_OP_OCTS(void)
  9294. __attribute__ ((pure, always_inline));
  9295. static inline u64 NIXX_LF_RQ_OP_OCTS(void)
  9296. {
  9297. return 0x910;
  9298. }
  9299. /**
  9300. * Register (RVU_PFVF_BAR2) nix#_lf_rq_op_pkts
  9301. *
  9302. * NIX LF Receive Queue Packets Operation Register A 64-bit atomic load-
  9303. * and-add to this register reads NIX_RQ_CTX_S[PKTS]. The atomic write
  9304. * data has format NIX_OP_Q_WDATA_S and selects the RQ within LF. All
  9305. * other accesses to this register (e.g. reads and writes) are RAZ/WI.
  9306. * RSL accesses to this register are RAZ/WI.
  9307. */
  9308. union nixx_lf_rq_op_pkts {
  9309. u64 u;
  9310. struct nixx_lf_rq_op_pkts_s {
  9311. u64 cnt : 48;
  9312. u64 reserved_48_62 : 15;
  9313. u64 op_err : 1;
  9314. } s;
  9315. /* struct nixx_lf_rq_op_pkts_s cn; */
  9316. };
  9317. static inline u64 NIXX_LF_RQ_OP_PKTS(void)
  9318. __attribute__ ((pure, always_inline));
  9319. static inline u64 NIXX_LF_RQ_OP_PKTS(void)
  9320. {
  9321. return 0x920;
  9322. }
  9323. /**
  9324. * Register (RVU_PFVF_BAR2) nix#_lf_rq_op_re_pkts
  9325. *
  9326. * NIX LF Receive Queue Errored Packets Operation Register A 64-bit
  9327. * atomic load-and-add to this register reads NIX_RQ_CTX_S[RE_PKTS]. The
  9328. * atomic write data has format NIX_OP_Q_WDATA_S and selects the RQ
  9329. * within LF. All other accesses to this register (e.g. reads and
  9330. * writes) are RAZ/WI. RSL accesses to this register are RAZ/WI.
  9331. */
  9332. union nixx_lf_rq_op_re_pkts {
  9333. u64 u;
  9334. struct nixx_lf_rq_op_re_pkts_s {
  9335. u64 cnt : 48;
  9336. u64 reserved_48_62 : 15;
  9337. u64 op_err : 1;
  9338. } s;
  9339. /* struct nixx_lf_rq_op_re_pkts_s cn; */
  9340. };
  9341. static inline u64 NIXX_LF_RQ_OP_RE_PKTS(void)
  9342. __attribute__ ((pure, always_inline));
  9343. static inline u64 NIXX_LF_RQ_OP_RE_PKTS(void)
  9344. {
  9345. return 0x950;
  9346. }
  9347. /**
  9348. * Register (RVU_PFVF_BAR2) nix#_lf_rx_secret#
  9349. *
  9350. * NIX LF Receive Secret Key Registers
  9351. */
  9352. union nixx_lf_rx_secretx {
  9353. u64 u;
  9354. struct nixx_lf_rx_secretx_s {
  9355. u64 key : 64;
  9356. } s;
  9357. /* struct nixx_lf_rx_secretx_s cn; */
  9358. };
  9359. static inline u64 NIXX_LF_RX_SECRETX(u64 a)
  9360. __attribute__ ((pure, always_inline));
  9361. static inline u64 NIXX_LF_RX_SECRETX(u64 a)
  9362. {
  9363. return 0 + 8 * a;
  9364. }
  9365. /**
  9366. * Register (RVU_PFVF_BAR2) nix#_lf_rx_stat#
  9367. *
  9368. * NIX LF Receive Statistics Registers The last dimension indicates which
  9369. * statistic, and is enumerated by NIX_STAT_LF_RX_E.
  9370. */
  9371. union nixx_lf_rx_statx {
  9372. u64 u;
  9373. struct nixx_lf_rx_statx_s {
  9374. u64 stat : 48;
  9375. u64 reserved_48_63 : 16;
  9376. } s;
  9377. /* struct nixx_lf_rx_statx_s cn; */
  9378. };
  9379. static inline u64 NIXX_LF_RX_STATX(u64 a)
  9380. __attribute__ ((pure, always_inline));
  9381. static inline u64 NIXX_LF_RX_STATX(u64 a)
  9382. {
  9383. return 0x400 + 8 * a;
  9384. }
  9385. /**
  9386. * Register (RVU_PFVF_BAR2) nix#_lf_send_err_dbg
  9387. *
  9388. * NIX LF Send Error Debug Register This register captures debug info an
  9389. * error detected on packet send after a meta-descriptor is granted by
  9390. * PSE. Hardware sets [VALID] when the debug info is captured, and
  9391. * subsequent errors are not captured until software clears [VALID] by
  9392. * writing a one to it.
  9393. */
  9394. union nixx_lf_send_err_dbg {
  9395. u64 u;
  9396. struct nixx_lf_send_err_dbg_s {
  9397. u64 errcode : 8;
  9398. u64 sq : 20;
  9399. u64 sqe_id : 16;
  9400. u64 valid : 1;
  9401. u64 reserved_45_63 : 19;
  9402. } s;
  9403. /* struct nixx_lf_send_err_dbg_s cn; */
  9404. };
  9405. static inline u64 NIXX_LF_SEND_ERR_DBG(void)
  9406. __attribute__ ((pure, always_inline));
  9407. static inline u64 NIXX_LF_SEND_ERR_DBG(void)
  9408. {
  9409. return 0x280;
  9410. }
  9411. /**
  9412. * Register (RVU_PFVF_BAR2) nix#_lf_sq_op_drop_octs
  9413. *
  9414. * NIX LF Send Queue Dropped Octets Operation Register A 64-bit atomic
  9415. * load-and-add to this register reads NIX_SQ_CTX_S[DROP_OCTS]. The
  9416. * atomic write data has format NIX_OP_Q_WDATA_S and selects the SQ
  9417. * within LF. All other accesses to this register (e.g. reads and
  9418. * writes) are RAZ/WI. RSL accesses to this register are RAZ/WI.
  9419. */
  9420. union nixx_lf_sq_op_drop_octs {
  9421. u64 u;
  9422. struct nixx_lf_sq_op_drop_octs_s {
  9423. u64 cnt : 48;
  9424. u64 reserved_48_62 : 15;
  9425. u64 op_err : 1;
  9426. } s;
  9427. /* struct nixx_lf_sq_op_drop_octs_s cn; */
  9428. };
  9429. static inline u64 NIXX_LF_SQ_OP_DROP_OCTS(void)
  9430. __attribute__ ((pure, always_inline));
  9431. static inline u64 NIXX_LF_SQ_OP_DROP_OCTS(void)
  9432. {
  9433. return 0xa40;
  9434. }
  9435. /**
  9436. * Register (RVU_PFVF_BAR2) nix#_lf_sq_op_drop_pkts
  9437. *
  9438. * NIX LF Send Queue Dropped Packets Operation Register A 64-bit atomic
  9439. * load-and-add to this register reads NIX_SQ_CTX_S[DROP_PKTS]. The
  9440. * atomic write data has format NIX_OP_Q_WDATA_S and selects the SQ
  9441. * within LF. All other accesses to this register (e.g. reads and
  9442. * writes) are RAZ/WI. RSL accesses to this register are RAZ/WI.
  9443. */
  9444. union nixx_lf_sq_op_drop_pkts {
  9445. u64 u;
  9446. struct nixx_lf_sq_op_drop_pkts_s {
  9447. u64 cnt : 48;
  9448. u64 reserved_48_62 : 15;
  9449. u64 op_err : 1;
  9450. } s;
  9451. /* struct nixx_lf_sq_op_drop_pkts_s cn; */
  9452. };
  9453. static inline u64 NIXX_LF_SQ_OP_DROP_PKTS(void)
  9454. __attribute__ ((pure, always_inline));
  9455. static inline u64 NIXX_LF_SQ_OP_DROP_PKTS(void)
  9456. {
  9457. return 0xa50;
  9458. }
  9459. /**
  9460. * Register (RVU_PFVF_BAR2) nix#_lf_sq_op_err_dbg
  9461. *
  9462. * NIX LF SQ Operation Error Debug Register This register captures debug
  9463. * info for an error detected on LMT store to NIX_LF_OP_SEND() or when a
  9464. * NIX_LF_SQ_OP_* register is accessed. Hardware sets [VALID] when the
  9465. * debug info is captured, and subsequent errors are not captured until
  9466. * software clears [VALID] by writing a one to it.
  9467. */
  9468. union nixx_lf_sq_op_err_dbg {
  9469. u64 u;
  9470. struct nixx_lf_sq_op_err_dbg_s {
  9471. u64 errcode : 8;
  9472. u64 sq : 20;
  9473. u64 sqe_id : 16;
  9474. u64 valid : 1;
  9475. u64 reserved_45_63 : 19;
  9476. } s;
  9477. /* struct nixx_lf_sq_op_err_dbg_s cn; */
  9478. };
  9479. static inline u64 NIXX_LF_SQ_OP_ERR_DBG(void)
  9480. __attribute__ ((pure, always_inline));
  9481. static inline u64 NIXX_LF_SQ_OP_ERR_DBG(void)
  9482. {
  9483. return 0x260;
  9484. }
  9485. /**
  9486. * Register (RVU_PFVF_BAR2) nix#_lf_sq_op_int
  9487. *
  9488. * NIX LF Send Queue Interrupt Operation Register A 64-bit atomic load-
  9489. * and-add to this register reads SQ interrupts, interrupt enables and
  9490. * XOFF status. A write optionally sets or clears interrupts, interrupt
  9491. * enables and XOFF status. A read is RAZ. RSL accesses to this register
  9492. * are RAZ/WI.
  9493. */
  9494. union nixx_lf_sq_op_int {
  9495. u64 u;
  9496. struct nixx_lf_sq_op_int_s {
  9497. u64 sq_int : 8;
  9498. u64 sq_int_ena : 8;
  9499. u64 xoff : 1;
  9500. u64 reserved_17_41 : 25;
  9501. u64 op_err : 1;
  9502. u64 setop : 1;
  9503. u64 sq : 20;
  9504. } s;
  9505. /* struct nixx_lf_sq_op_int_s cn; */
  9506. };
  9507. static inline u64 NIXX_LF_SQ_OP_INT(void)
  9508. __attribute__ ((pure, always_inline));
  9509. static inline u64 NIXX_LF_SQ_OP_INT(void)
  9510. {
  9511. return 0xa00;
  9512. }
  9513. /**
  9514. * Register (RVU_PFVF_BAR2) nix#_lf_sq_op_octs
  9515. *
  9516. * NIX LF Send Queue Octets Operation Register A 64-bit atomic load-and-
  9517. * add to this register reads NIX_SQ_CTX_S[OCTS]. The atomic write data
  9518. * has format NIX_OP_Q_WDATA_S and selects the SQ within LF. All other
  9519. * accesses to this register (e.g. reads and writes) are RAZ/WI. RSL
  9520. * accesses to this register are RAZ/WI.
  9521. */
  9522. union nixx_lf_sq_op_octs {
  9523. u64 u;
  9524. struct nixx_lf_sq_op_octs_s {
  9525. u64 cnt : 48;
  9526. u64 reserved_48_62 : 15;
  9527. u64 op_err : 1;
  9528. } s;
  9529. /* struct nixx_lf_sq_op_octs_s cn; */
  9530. };
  9531. static inline u64 NIXX_LF_SQ_OP_OCTS(void)
  9532. __attribute__ ((pure, always_inline));
  9533. static inline u64 NIXX_LF_SQ_OP_OCTS(void)
  9534. {
  9535. return 0xa10;
  9536. }
  9537. /**
  9538. * Register (RVU_PFVF_BAR2) nix#_lf_sq_op_pkts
  9539. *
  9540. * NIX LF Send Queue Packets Operation Register A 64-bit atomic load-and-
  9541. * add to this register reads NIX_SQ_CTX_S[PKTS]. The atomic write data
  9542. * has format NIX_OP_Q_WDATA_S and selects the SQ within LF. All other
  9543. * accesses to this register (e.g. reads and writes) are RAZ/WI. RSL
  9544. * accesses to this register are RAZ/WI.
  9545. */
  9546. union nixx_lf_sq_op_pkts {
  9547. u64 u;
  9548. struct nixx_lf_sq_op_pkts_s {
  9549. u64 cnt : 48;
  9550. u64 reserved_48_62 : 15;
  9551. u64 op_err : 1;
  9552. } s;
  9553. /* struct nixx_lf_sq_op_pkts_s cn; */
  9554. };
  9555. static inline u64 NIXX_LF_SQ_OP_PKTS(void)
  9556. __attribute__ ((pure, always_inline));
  9557. static inline u64 NIXX_LF_SQ_OP_PKTS(void)
  9558. {
  9559. return 0xa20;
  9560. }
  9561. /**
  9562. * Register (RVU_PFVF_BAR2) nix#_lf_sq_op_status
  9563. *
  9564. * NIX LF Send Queue Status Operation Register A 64-bit atomic load-and-
  9565. * add to this register reads status fields in NIX_SQ_CTX_S. The atomic
  9566. * write data has format NIX_OP_Q_WDATA_S and selects the SQ within LF.
  9567. * Completion of the load-and-add operation also ensures that all
  9568. * previously issued LMT stores to NIX_LF_OP_SEND() have completed. All
  9569. * other accesses to this register (e.g. reads and writes) are RAZ/WI.
  9570. * RSL accesses to this register are RAZ/WI.
  9571. */
  9572. union nixx_lf_sq_op_status {
  9573. u64 u;
  9574. struct nixx_lf_sq_op_status_s {
  9575. u64 sqb_count : 16;
  9576. u64 reserved_16_19 : 4;
  9577. u64 head_offset : 6;
  9578. u64 reserved_26_27 : 2;
  9579. u64 tail_offset : 6;
  9580. u64 reserved_34_62 : 29;
  9581. u64 op_err : 1;
  9582. } s;
  9583. struct nixx_lf_sq_op_status_cn {
  9584. u64 sqb_count : 16;
  9585. u64 reserved_16_19 : 4;
  9586. u64 head_offset : 6;
  9587. u64 reserved_26_27 : 2;
  9588. u64 tail_offset : 6;
  9589. u64 reserved_34_35 : 2;
  9590. u64 reserved_36_62 : 27;
  9591. u64 op_err : 1;
  9592. } cn;
  9593. };
  9594. static inline u64 NIXX_LF_SQ_OP_STATUS(void)
  9595. __attribute__ ((pure, always_inline));
  9596. static inline u64 NIXX_LF_SQ_OP_STATUS(void)
  9597. {
  9598. return 0xa30;
  9599. }
  9600. /**
  9601. * Register (RVU_PFVF_BAR2) nix#_lf_tx_stat#
  9602. *
  9603. * NIX LF Transmit Statistics Registers The last dimension indicates
  9604. * which statistic, and is enumerated by NIX_STAT_LF_TX_E.
  9605. */
  9606. union nixx_lf_tx_statx {
  9607. u64 u;
  9608. struct nixx_lf_tx_statx_s {
  9609. u64 stat : 48;
  9610. u64 reserved_48_63 : 16;
  9611. } s;
  9612. /* struct nixx_lf_tx_statx_s cn; */
  9613. };
  9614. static inline u64 NIXX_LF_TX_STATX(u64 a)
  9615. __attribute__ ((pure, always_inline));
  9616. static inline u64 NIXX_LF_TX_STATX(u64 a)
  9617. {
  9618. return 0x300 + 8 * a;
  9619. }
  9620. /**
  9621. * Register (RVU_PF_BAR0) nix#_priv_af_int_cfg
  9622. *
  9623. * NIX Privileged Admin Function Interrupt Configuration Register
  9624. */
  9625. union nixx_priv_af_int_cfg {
  9626. u64 u;
  9627. struct nixx_priv_af_int_cfg_s {
  9628. u64 msix_offset : 11;
  9629. u64 reserved_11 : 1;
  9630. u64 msix_size : 8;
  9631. u64 reserved_20_63 : 44;
  9632. } s;
  9633. /* struct nixx_priv_af_int_cfg_s cn; */
  9634. };
  9635. static inline u64 NIXX_PRIV_AF_INT_CFG(void)
  9636. __attribute__ ((pure, always_inline));
  9637. static inline u64 NIXX_PRIV_AF_INT_CFG(void)
  9638. {
  9639. return 0x8000000;
  9640. }
  9641. /**
  9642. * Register (RVU_PF_BAR0) nix#_priv_lf#_cfg
  9643. *
  9644. * NIX Privileged Local Function Configuration Registers These registers
  9645. * allow each NIX local function (LF) to be provisioned to a VF/PF for
  9646. * RVU. See also NIX_AF_RVU_LF_CFG_DEBUG. Software should read this
  9647. * register after write to ensure that the LF is mapped to [PF_FUNC]
  9648. * before issuing transactions to the mapped PF and function. [SLOT]
  9649. * must be zero. Internal: Hardware ignores [SLOT] and always assumes
  9650. * 0x0.
  9651. */
  9652. union nixx_priv_lfx_cfg {
  9653. u64 u;
  9654. struct nixx_priv_lfx_cfg_s {
  9655. u64 slot : 8;
  9656. u64 pf_func : 16;
  9657. u64 reserved_24_62 : 39;
  9658. u64 ena : 1;
  9659. } s;
  9660. /* struct nixx_priv_lfx_cfg_s cn; */
  9661. };
  9662. static inline u64 NIXX_PRIV_LFX_CFG(u64 a)
  9663. __attribute__ ((pure, always_inline));
  9664. static inline u64 NIXX_PRIV_LFX_CFG(u64 a)
  9665. {
  9666. return 0x8000010 + 0x100 * a;
  9667. }
  9668. /**
  9669. * Register (RVU_PF_BAR0) nix#_priv_lf#_int_cfg
  9670. *
  9671. * NIX Privileged LF Interrupt Configuration Registers
  9672. */
  9673. union nixx_priv_lfx_int_cfg {
  9674. u64 u;
  9675. struct nixx_priv_lfx_int_cfg_s {
  9676. u64 msix_offset : 11;
  9677. u64 reserved_11 : 1;
  9678. u64 msix_size : 8;
  9679. u64 reserved_20_63 : 44;
  9680. } s;
  9681. /* struct nixx_priv_lfx_int_cfg_s cn; */
  9682. };
  9683. static inline u64 NIXX_PRIV_LFX_INT_CFG(u64 a)
  9684. __attribute__ ((pure, always_inline));
  9685. static inline u64 NIXX_PRIV_LFX_INT_CFG(u64 a)
  9686. {
  9687. return 0x8000020 + 0x100 * a;
  9688. }
  9689. #endif /* __CSRS_NIX_H__ */