csrs-mio_emm.h 32 KB

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  1. /* SPDX-License-Identifier: GPL-2.0
  2. *
  3. * Copyright (C) 2020 Marvell International Ltd.
  4. *
  5. * https://spdx.org/licenses
  6. */
  7. #ifndef __CSRS_MIO_EMM_H__
  8. #define __CSRS_MIO_EMM_H__
  9. /**
  10. * @file
  11. *
  12. * Configuration and status register (CSR) address and type definitions for
  13. * MIO_EMM.
  14. *
  15. * This file is auto generated. Do not edit.
  16. *
  17. */
  18. /**
  19. * Enumeration mio_emm_bar_e
  20. *
  21. * eMMC Base Address Register Enumeration Enumerates the base address
  22. * registers.
  23. */
  24. #define MIO_EMM_BAR_E_MIO_EMM_PF_BAR0_CN8 (0x87e009000000ll)
  25. #define MIO_EMM_BAR_E_MIO_EMM_PF_BAR0_CN8_SIZE 0x800000ull
  26. #define MIO_EMM_BAR_E_MIO_EMM_PF_BAR0_CN9 (0x87e009000000ll)
  27. #define MIO_EMM_BAR_E_MIO_EMM_PF_BAR0_CN9_SIZE 0x10000ull
  28. #define MIO_EMM_BAR_E_MIO_EMM_PF_BAR4 (0x87e009f00000ll)
  29. #define MIO_EMM_BAR_E_MIO_EMM_PF_BAR4_SIZE 0x100000ull
  30. /**
  31. * Enumeration mio_emm_int_vec_e
  32. *
  33. * eMMC MSI-X Vector Enumeration Enumerates the MSI-X interrupt vectors.
  34. */
  35. #define MIO_EMM_INT_VEC_E_DMA_INT_DONE (8)
  36. #define MIO_EMM_INT_VEC_E_DMA_INT_FIFO (7)
  37. #define MIO_EMM_INT_VEC_E_EMM_BUF_DONE (0)
  38. #define MIO_EMM_INT_VEC_E_EMM_CMD_DONE (1)
  39. #define MIO_EMM_INT_VEC_E_EMM_CMD_ERR (3)
  40. #define MIO_EMM_INT_VEC_E_EMM_DMA_DONE (2)
  41. #define MIO_EMM_INT_VEC_E_EMM_DMA_ERR (4)
  42. #define MIO_EMM_INT_VEC_E_EMM_SWITCH_DONE (5)
  43. #define MIO_EMM_INT_VEC_E_EMM_SWITCH_ERR (6)
  44. #define MIO_EMM_INT_VEC_E_NCB_FLT (9)
  45. #define MIO_EMM_INT_VEC_E_NCB_RAS (0xa)
  46. /**
  47. * Register (RSL) mio_emm_access_wdog
  48. *
  49. * eMMC Access Watchdog Register
  50. */
  51. union mio_emm_access_wdog {
  52. u64 u;
  53. struct mio_emm_access_wdog_s {
  54. u64 clk_cnt : 32;
  55. u64 reserved_32_63 : 32;
  56. } s;
  57. /* struct mio_emm_access_wdog_s cn; */
  58. };
  59. static inline u64 MIO_EMM_ACCESS_WDOG(void)
  60. __attribute__ ((pure, always_inline));
  61. static inline u64 MIO_EMM_ACCESS_WDOG(void)
  62. {
  63. return 0x20f0;
  64. }
  65. /**
  66. * Register (RSL) mio_emm_buf_dat
  67. *
  68. * eMMC Data Buffer Access Register
  69. */
  70. union mio_emm_buf_dat {
  71. u64 u;
  72. struct mio_emm_buf_dat_s {
  73. u64 dat : 64;
  74. } s;
  75. /* struct mio_emm_buf_dat_s cn; */
  76. };
  77. static inline u64 MIO_EMM_BUF_DAT(void)
  78. __attribute__ ((pure, always_inline));
  79. static inline u64 MIO_EMM_BUF_DAT(void)
  80. {
  81. return 0x20e8;
  82. }
  83. /**
  84. * Register (RSL) mio_emm_buf_idx
  85. *
  86. * eMMC Data Buffer Address Register
  87. */
  88. union mio_emm_buf_idx {
  89. u64 u;
  90. struct mio_emm_buf_idx_s {
  91. u64 offset : 6;
  92. u64 buf_num : 1;
  93. u64 reserved_7_15 : 9;
  94. u64 inc : 1;
  95. u64 reserved_17_63 : 47;
  96. } s;
  97. /* struct mio_emm_buf_idx_s cn; */
  98. };
  99. static inline u64 MIO_EMM_BUF_IDX(void)
  100. __attribute__ ((pure, always_inline));
  101. static inline u64 MIO_EMM_BUF_IDX(void)
  102. {
  103. return 0x20e0;
  104. }
  105. /**
  106. * Register (RSL) mio_emm_calb
  107. *
  108. * eMMC Calbration Register This register initiates delay line
  109. * characterization.
  110. */
  111. union mio_emm_calb {
  112. u64 u;
  113. struct mio_emm_calb_s {
  114. u64 start : 1;
  115. u64 reserved_1_63 : 63;
  116. } s;
  117. /* struct mio_emm_calb_s cn; */
  118. };
  119. static inline u64 MIO_EMM_CALB(void)
  120. __attribute__ ((pure, always_inline));
  121. static inline u64 MIO_EMM_CALB(void)
  122. {
  123. return 0x20c0;
  124. }
  125. /**
  126. * Register (RSL) mio_emm_cfg
  127. *
  128. * eMMC Configuration Register
  129. */
  130. union mio_emm_cfg {
  131. u64 u;
  132. struct mio_emm_cfg_s {
  133. u64 bus_ena : 4;
  134. u64 reserved_4_63 : 60;
  135. } s;
  136. /* struct mio_emm_cfg_s cn; */
  137. };
  138. static inline u64 MIO_EMM_CFG(void)
  139. __attribute__ ((pure, always_inline));
  140. static inline u64 MIO_EMM_CFG(void)
  141. {
  142. return 0x2000;
  143. }
  144. /**
  145. * Register (RSL) mio_emm_cmd
  146. *
  147. * eMMC Command Register
  148. */
  149. union mio_emm_cmd {
  150. u64 u;
  151. struct mio_emm_cmd_s {
  152. u64 arg : 32;
  153. u64 cmd_idx : 6;
  154. u64 rtype_xor : 3;
  155. u64 ctype_xor : 2;
  156. u64 reserved_43_48 : 6;
  157. u64 offset : 6;
  158. u64 dbuf : 1;
  159. u64 reserved_56_58 : 3;
  160. u64 cmd_val : 1;
  161. u64 bus_id : 2;
  162. u64 skip_busy : 1;
  163. u64 reserved_63 : 1;
  164. } s;
  165. /* struct mio_emm_cmd_s cn; */
  166. };
  167. static inline u64 MIO_EMM_CMD(void)
  168. __attribute__ ((pure, always_inline));
  169. static inline u64 MIO_EMM_CMD(void)
  170. {
  171. return 0x2058;
  172. }
  173. /**
  174. * Register (RSL) mio_emm_comp
  175. *
  176. * eMMC Compensation Register
  177. */
  178. union mio_emm_comp {
  179. u64 u;
  180. struct mio_emm_comp_s {
  181. u64 nctl : 3;
  182. u64 reserved_3_7 : 5;
  183. u64 pctl : 3;
  184. u64 reserved_11_63 : 53;
  185. } s;
  186. /* struct mio_emm_comp_s cn; */
  187. };
  188. static inline u64 MIO_EMM_COMP(void)
  189. __attribute__ ((pure, always_inline));
  190. static inline u64 MIO_EMM_COMP(void)
  191. {
  192. return 0x2040;
  193. }
  194. /**
  195. * Register (RSL) mio_emm_debug
  196. *
  197. * eMMC Debug Register
  198. */
  199. union mio_emm_debug {
  200. u64 u;
  201. struct mio_emm_debug_s {
  202. u64 clk_on : 1;
  203. u64 reserved_1_7 : 7;
  204. u64 cmd_sm : 4;
  205. u64 data_sm : 4;
  206. u64 dma_sm : 4;
  207. u64 emmc_clk_disable : 1;
  208. u64 rdsync_rst : 1;
  209. u64 reserved_22_63 : 42;
  210. } s;
  211. struct mio_emm_debug_cn96xxp1 {
  212. u64 clk_on : 1;
  213. u64 reserved_1_7 : 7;
  214. u64 cmd_sm : 4;
  215. u64 data_sm : 4;
  216. u64 dma_sm : 4;
  217. u64 reserved_20_63 : 44;
  218. } cn96xxp1;
  219. /* struct mio_emm_debug_s cn96xxp3; */
  220. /* struct mio_emm_debug_cn96xxp1 cnf95xx; */
  221. };
  222. static inline u64 MIO_EMM_DEBUG(void)
  223. __attribute__ ((pure, always_inline));
  224. static inline u64 MIO_EMM_DEBUG(void)
  225. {
  226. return 0x20f8;
  227. }
  228. /**
  229. * Register (RSL) mio_emm_dma
  230. *
  231. * eMMC External DMA Configuration Register
  232. */
  233. union mio_emm_dma {
  234. u64 u;
  235. struct mio_emm_dma_s {
  236. u64 card_addr : 32;
  237. u64 block_cnt : 16;
  238. u64 multi : 1;
  239. u64 rw : 1;
  240. u64 rel_wr : 1;
  241. u64 thres : 6;
  242. u64 dat_null : 1;
  243. u64 sector : 1;
  244. u64 dma_val : 1;
  245. u64 bus_id : 2;
  246. u64 skip_busy : 1;
  247. u64 extra_args : 1;
  248. } s;
  249. struct mio_emm_dma_cn8 {
  250. u64 card_addr : 32;
  251. u64 block_cnt : 16;
  252. u64 multi : 1;
  253. u64 rw : 1;
  254. u64 rel_wr : 1;
  255. u64 thres : 6;
  256. u64 dat_null : 1;
  257. u64 sector : 1;
  258. u64 dma_val : 1;
  259. u64 bus_id : 2;
  260. u64 skip_busy : 1;
  261. u64 reserved_63 : 1;
  262. } cn8;
  263. struct mio_emm_dma_cn9 {
  264. u64 card_addr : 32;
  265. u64 block_cnt : 16;
  266. u64 multi : 1;
  267. u64 rw : 1;
  268. u64 reserved_50 : 1;
  269. u64 thres : 6;
  270. u64 dat_null : 1;
  271. u64 sector : 1;
  272. u64 dma_val : 1;
  273. u64 bus_id : 2;
  274. u64 skip_busy : 1;
  275. u64 extra_args : 1;
  276. } cn9;
  277. };
  278. static inline u64 MIO_EMM_DMA(void)
  279. __attribute__ ((pure, always_inline));
  280. static inline u64 MIO_EMM_DMA(void)
  281. {
  282. return 0x2050;
  283. }
  284. /**
  285. * Register (RSL) mio_emm_dma_adr
  286. *
  287. * eMMC DMA Address Register This register sets the address for eMMC/SD
  288. * flash transfers to/from memory. Sixty-four-bit operations must be used
  289. * to access this register. This register is updated by the DMA hardware
  290. * and can be reloaded by the values placed in the MIO_EMM_DMA_FIFO_ADR.
  291. */
  292. union mio_emm_dma_adr {
  293. u64 u;
  294. struct mio_emm_dma_adr_s {
  295. u64 adr : 53;
  296. u64 reserved_53_63 : 11;
  297. } s;
  298. struct mio_emm_dma_adr_cn8 {
  299. u64 adr : 49;
  300. u64 reserved_49_63 : 15;
  301. } cn8;
  302. /* struct mio_emm_dma_adr_s cn9; */
  303. };
  304. static inline u64 MIO_EMM_DMA_ADR(void)
  305. __attribute__ ((pure, always_inline));
  306. static inline u64 MIO_EMM_DMA_ADR(void)
  307. {
  308. return 0x188;
  309. }
  310. /**
  311. * Register (RSL) mio_emm_dma_arg
  312. *
  313. * eMMC External DMA Extra Arguments Register
  314. */
  315. union mio_emm_dma_arg {
  316. u64 u;
  317. struct mio_emm_dma_arg_s {
  318. u64 cmd23_args : 8;
  319. u64 force_pgm : 1;
  320. u64 context_id : 4;
  321. u64 tag_req : 1;
  322. u64 pack_cmd : 1;
  323. u64 rel_wr : 1;
  324. u64 alt_cmd : 6;
  325. u64 skip_blk_cmd : 1;
  326. u64 reserved_23_31 : 9;
  327. u64 alt_cmd_arg : 32;
  328. } s;
  329. /* struct mio_emm_dma_arg_s cn; */
  330. };
  331. static inline u64 MIO_EMM_DMA_ARG(void)
  332. __attribute__ ((pure, always_inline));
  333. static inline u64 MIO_EMM_DMA_ARG(void)
  334. {
  335. return 0x2090;
  336. }
  337. /**
  338. * Register (RSL) mio_emm_dma_cfg
  339. *
  340. * eMMC DMA Configuration Register This register controls the internal
  341. * DMA engine used with the eMMC/SD flash controller. Sixty- four-bit
  342. * operations must be used to access this register. This register is
  343. * updated by the hardware DMA engine and can also be reloaded by writes
  344. * to the MIO_EMM_DMA_FIFO_CMD register.
  345. */
  346. union mio_emm_dma_cfg {
  347. u64 u;
  348. struct mio_emm_dma_cfg_s {
  349. u64 reserved_0_35 : 36;
  350. u64 size : 20;
  351. u64 endian : 1;
  352. u64 swap8 : 1;
  353. u64 swap16 : 1;
  354. u64 swap32 : 1;
  355. u64 reserved_60 : 1;
  356. u64 clr : 1;
  357. u64 rw : 1;
  358. u64 en : 1;
  359. } s;
  360. /* struct mio_emm_dma_cfg_s cn; */
  361. };
  362. static inline u64 MIO_EMM_DMA_CFG(void)
  363. __attribute__ ((pure, always_inline));
  364. static inline u64 MIO_EMM_DMA_CFG(void)
  365. {
  366. return 0x180;
  367. }
  368. /**
  369. * Register (RSL) mio_emm_dma_fifo_adr
  370. *
  371. * eMMC Internal DMA FIFO Address Register This register specifies the
  372. * internal address that is loaded into the eMMC internal DMA FIFO. The
  373. * FIFO is used to queue up operations for the
  374. * MIO_EMM_DMA_CFG/MIO_EMM_DMA_ADR when the DMA completes successfully.
  375. */
  376. union mio_emm_dma_fifo_adr {
  377. u64 u;
  378. struct mio_emm_dma_fifo_adr_s {
  379. u64 reserved_0_2 : 3;
  380. u64 adr : 50;
  381. u64 reserved_53_63 : 11;
  382. } s;
  383. struct mio_emm_dma_fifo_adr_cn8 {
  384. u64 reserved_0_2 : 3;
  385. u64 adr : 46;
  386. u64 reserved_49_63 : 15;
  387. } cn8;
  388. /* struct mio_emm_dma_fifo_adr_s cn9; */
  389. };
  390. static inline u64 MIO_EMM_DMA_FIFO_ADR(void)
  391. __attribute__ ((pure, always_inline));
  392. static inline u64 MIO_EMM_DMA_FIFO_ADR(void)
  393. {
  394. return 0x170;
  395. }
  396. /**
  397. * Register (RSL) mio_emm_dma_fifo_cfg
  398. *
  399. * eMMC Internal DMA FIFO Configuration Register This register controls
  400. * DMA FIFO operations.
  401. */
  402. union mio_emm_dma_fifo_cfg {
  403. u64 u;
  404. struct mio_emm_dma_fifo_cfg_s {
  405. u64 count : 5;
  406. u64 reserved_5_7 : 3;
  407. u64 int_lvl : 5;
  408. u64 reserved_13_15 : 3;
  409. u64 clr : 1;
  410. u64 reserved_17_63 : 47;
  411. } s;
  412. /* struct mio_emm_dma_fifo_cfg_s cn; */
  413. };
  414. static inline u64 MIO_EMM_DMA_FIFO_CFG(void)
  415. __attribute__ ((pure, always_inline));
  416. static inline u64 MIO_EMM_DMA_FIFO_CFG(void)
  417. {
  418. return 0x160;
  419. }
  420. /**
  421. * Register (RSL) mio_emm_dma_fifo_cmd
  422. *
  423. * eMMC Internal DMA FIFO Command Register This register specifies a
  424. * command that is loaded into the eMMC internal DMA FIFO. The FIFO is
  425. * used to queue up operations for the MIO_EMM_DMA_CFG/MIO_EMM_DMA_ADR
  426. * when the DMA completes successfully. Writes to this register store
  427. * both the MIO_EMM_DMA_FIFO_CMD and the MIO_EMM_DMA_FIFO_ADR contents
  428. * into the FIFO and increment the MIO_EMM_DMA_FIFO_CFG[COUNT] field.
  429. * Note: This register has a similar format to MIO_EMM_DMA_CFG with the
  430. * exception that the EN and CLR fields are absent. These are supported
  431. * in MIO_EMM_DMA_FIFO_CFG.
  432. */
  433. union mio_emm_dma_fifo_cmd {
  434. u64 u;
  435. struct mio_emm_dma_fifo_cmd_s {
  436. u64 reserved_0_35 : 36;
  437. u64 size : 20;
  438. u64 endian : 1;
  439. u64 swap8 : 1;
  440. u64 swap16 : 1;
  441. u64 swap32 : 1;
  442. u64 intdis : 1;
  443. u64 reserved_61 : 1;
  444. u64 rw : 1;
  445. u64 reserved_63 : 1;
  446. } s;
  447. /* struct mio_emm_dma_fifo_cmd_s cn; */
  448. };
  449. static inline u64 MIO_EMM_DMA_FIFO_CMD(void)
  450. __attribute__ ((pure, always_inline));
  451. static inline u64 MIO_EMM_DMA_FIFO_CMD(void)
  452. {
  453. return 0x178;
  454. }
  455. /**
  456. * Register (RSL) mio_emm_dma_int
  457. *
  458. * eMMC DMA Interrupt Register Sixty-four-bit operations must be used to
  459. * access this register.
  460. */
  461. union mio_emm_dma_int {
  462. u64 u;
  463. struct mio_emm_dma_int_s {
  464. u64 done : 1;
  465. u64 fifo : 1;
  466. u64 reserved_2_63 : 62;
  467. } s;
  468. /* struct mio_emm_dma_int_s cn; */
  469. };
  470. static inline u64 MIO_EMM_DMA_INT(void)
  471. __attribute__ ((pure, always_inline));
  472. static inline u64 MIO_EMM_DMA_INT(void)
  473. {
  474. return 0x190;
  475. }
  476. /**
  477. * Register (RSL) mio_emm_dma_int_ena_w1c
  478. *
  479. * eMMC DMA Interrupt Enable Clear Register This register clears
  480. * interrupt enable bits.
  481. */
  482. union mio_emm_dma_int_ena_w1c {
  483. u64 u;
  484. struct mio_emm_dma_int_ena_w1c_s {
  485. u64 done : 1;
  486. u64 fifo : 1;
  487. u64 reserved_2_63 : 62;
  488. } s;
  489. /* struct mio_emm_dma_int_ena_w1c_s cn; */
  490. };
  491. static inline u64 MIO_EMM_DMA_INT_ENA_W1C(void)
  492. __attribute__ ((pure, always_inline));
  493. static inline u64 MIO_EMM_DMA_INT_ENA_W1C(void)
  494. {
  495. return 0x1a8;
  496. }
  497. /**
  498. * Register (RSL) mio_emm_dma_int_ena_w1s
  499. *
  500. * eMMC DMA Interrupt Enable Set Register This register sets interrupt
  501. * enable bits.
  502. */
  503. union mio_emm_dma_int_ena_w1s {
  504. u64 u;
  505. struct mio_emm_dma_int_ena_w1s_s {
  506. u64 done : 1;
  507. u64 fifo : 1;
  508. u64 reserved_2_63 : 62;
  509. } s;
  510. /* struct mio_emm_dma_int_ena_w1s_s cn; */
  511. };
  512. static inline u64 MIO_EMM_DMA_INT_ENA_W1S(void)
  513. __attribute__ ((pure, always_inline));
  514. static inline u64 MIO_EMM_DMA_INT_ENA_W1S(void)
  515. {
  516. return 0x1a0;
  517. }
  518. /**
  519. * Register (RSL) mio_emm_dma_int_w1s
  520. *
  521. * eMMC DMA Interrupt Set Register This register sets interrupt bits.
  522. */
  523. union mio_emm_dma_int_w1s {
  524. u64 u;
  525. struct mio_emm_dma_int_w1s_s {
  526. u64 done : 1;
  527. u64 fifo : 1;
  528. u64 reserved_2_63 : 62;
  529. } s;
  530. /* struct mio_emm_dma_int_w1s_s cn; */
  531. };
  532. static inline u64 MIO_EMM_DMA_INT_W1S(void)
  533. __attribute__ ((pure, always_inline));
  534. static inline u64 MIO_EMM_DMA_INT_W1S(void)
  535. {
  536. return 0x198;
  537. }
  538. /**
  539. * Register (RSL) mio_emm_int
  540. *
  541. * eMMC Interrupt Register
  542. */
  543. union mio_emm_int {
  544. u64 u;
  545. struct mio_emm_int_s {
  546. u64 buf_done : 1;
  547. u64 cmd_done : 1;
  548. u64 dma_done : 1;
  549. u64 cmd_err : 1;
  550. u64 dma_err : 1;
  551. u64 switch_done : 1;
  552. u64 switch_err : 1;
  553. u64 ncb_flt : 1;
  554. u64 ncb_ras : 1;
  555. u64 reserved_9_63 : 55;
  556. } s;
  557. struct mio_emm_int_cn8 {
  558. u64 buf_done : 1;
  559. u64 cmd_done : 1;
  560. u64 dma_done : 1;
  561. u64 cmd_err : 1;
  562. u64 dma_err : 1;
  563. u64 switch_done : 1;
  564. u64 switch_err : 1;
  565. u64 reserved_7_63 : 57;
  566. } cn8;
  567. /* struct mio_emm_int_s cn9; */
  568. };
  569. static inline u64 MIO_EMM_INT(void)
  570. __attribute__ ((pure, always_inline));
  571. static inline u64 MIO_EMM_INT(void)
  572. {
  573. return 0x2078;
  574. }
  575. /**
  576. * Register (RSL) mio_emm_int_ena_w1c
  577. *
  578. * eMMC Interrupt Enable Clear Register This register clears interrupt
  579. * enable bits.
  580. */
  581. union mio_emm_int_ena_w1c {
  582. u64 u;
  583. struct mio_emm_int_ena_w1c_s {
  584. u64 buf_done : 1;
  585. u64 cmd_done : 1;
  586. u64 dma_done : 1;
  587. u64 cmd_err : 1;
  588. u64 dma_err : 1;
  589. u64 switch_done : 1;
  590. u64 switch_err : 1;
  591. u64 ncb_flt : 1;
  592. u64 ncb_ras : 1;
  593. u64 reserved_9_63 : 55;
  594. } s;
  595. struct mio_emm_int_ena_w1c_cn8 {
  596. u64 buf_done : 1;
  597. u64 cmd_done : 1;
  598. u64 dma_done : 1;
  599. u64 cmd_err : 1;
  600. u64 dma_err : 1;
  601. u64 switch_done : 1;
  602. u64 switch_err : 1;
  603. u64 reserved_7_63 : 57;
  604. } cn8;
  605. /* struct mio_emm_int_ena_w1c_s cn9; */
  606. };
  607. static inline u64 MIO_EMM_INT_ENA_W1C(void)
  608. __attribute__ ((pure, always_inline));
  609. static inline u64 MIO_EMM_INT_ENA_W1C(void)
  610. {
  611. return 0x20b8;
  612. }
  613. /**
  614. * Register (RSL) mio_emm_int_ena_w1s
  615. *
  616. * eMMC Interrupt Enable Set Register This register sets interrupt enable
  617. * bits.
  618. */
  619. union mio_emm_int_ena_w1s {
  620. u64 u;
  621. struct mio_emm_int_ena_w1s_s {
  622. u64 buf_done : 1;
  623. u64 cmd_done : 1;
  624. u64 dma_done : 1;
  625. u64 cmd_err : 1;
  626. u64 dma_err : 1;
  627. u64 switch_done : 1;
  628. u64 switch_err : 1;
  629. u64 ncb_flt : 1;
  630. u64 ncb_ras : 1;
  631. u64 reserved_9_63 : 55;
  632. } s;
  633. struct mio_emm_int_ena_w1s_cn8 {
  634. u64 buf_done : 1;
  635. u64 cmd_done : 1;
  636. u64 dma_done : 1;
  637. u64 cmd_err : 1;
  638. u64 dma_err : 1;
  639. u64 switch_done : 1;
  640. u64 switch_err : 1;
  641. u64 reserved_7_63 : 57;
  642. } cn8;
  643. /* struct mio_emm_int_ena_w1s_s cn9; */
  644. };
  645. static inline u64 MIO_EMM_INT_ENA_W1S(void)
  646. __attribute__ ((pure, always_inline));
  647. static inline u64 MIO_EMM_INT_ENA_W1S(void)
  648. {
  649. return 0x20b0;
  650. }
  651. /**
  652. * Register (RSL) mio_emm_int_w1s
  653. *
  654. * eMMC Interrupt Set Register This register sets interrupt bits.
  655. */
  656. union mio_emm_int_w1s {
  657. u64 u;
  658. struct mio_emm_int_w1s_s {
  659. u64 buf_done : 1;
  660. u64 cmd_done : 1;
  661. u64 dma_done : 1;
  662. u64 cmd_err : 1;
  663. u64 dma_err : 1;
  664. u64 switch_done : 1;
  665. u64 switch_err : 1;
  666. u64 ncb_flt : 1;
  667. u64 ncb_ras : 1;
  668. u64 reserved_9_63 : 55;
  669. } s;
  670. struct mio_emm_int_w1s_cn8 {
  671. u64 buf_done : 1;
  672. u64 cmd_done : 1;
  673. u64 dma_done : 1;
  674. u64 cmd_err : 1;
  675. u64 dma_err : 1;
  676. u64 switch_done : 1;
  677. u64 switch_err : 1;
  678. u64 reserved_7_63 : 57;
  679. } cn8;
  680. /* struct mio_emm_int_w1s_s cn9; */
  681. };
  682. static inline u64 MIO_EMM_INT_W1S(void)
  683. __attribute__ ((pure, always_inline));
  684. static inline u64 MIO_EMM_INT_W1S(void)
  685. {
  686. return 0x2080;
  687. }
  688. /**
  689. * Register (RSL) mio_emm_io_ctl
  690. *
  691. * eMMC I/O Control Register
  692. */
  693. union mio_emm_io_ctl {
  694. u64 u;
  695. struct mio_emm_io_ctl_s {
  696. u64 slew : 1;
  697. u64 reserved_1 : 1;
  698. u64 drive : 2;
  699. u64 reserved_4_63 : 60;
  700. } s;
  701. /* struct mio_emm_io_ctl_s cn; */
  702. };
  703. static inline u64 MIO_EMM_IO_CTL(void)
  704. __attribute__ ((pure, always_inline));
  705. static inline u64 MIO_EMM_IO_CTL(void)
  706. {
  707. return 0x2040;
  708. }
  709. /**
  710. * Register (RSL) mio_emm_mode#
  711. *
  712. * eMMC Operating Mode Register
  713. */
  714. union mio_emm_modex {
  715. u64 u;
  716. struct mio_emm_modex_s {
  717. u64 clk_lo : 16;
  718. u64 clk_hi : 16;
  719. u64 power_class : 4;
  720. u64 clk_swap : 1;
  721. u64 reserved_37_39 : 3;
  722. u64 bus_width : 3;
  723. u64 reserved_43_47 : 5;
  724. u64 hs_timing : 1;
  725. u64 hs200_timing : 1;
  726. u64 hs400_timing : 1;
  727. u64 reserved_51_63 : 13;
  728. } s;
  729. struct mio_emm_modex_cn8 {
  730. u64 clk_lo : 16;
  731. u64 clk_hi : 16;
  732. u64 power_class : 4;
  733. u64 reserved_36_39 : 4;
  734. u64 bus_width : 3;
  735. u64 reserved_43_47 : 5;
  736. u64 hs_timing : 1;
  737. u64 reserved_49_63 : 15;
  738. } cn8;
  739. struct mio_emm_modex_cn96xxp1 {
  740. u64 clk_lo : 16;
  741. u64 clk_hi : 16;
  742. u64 power_class : 4;
  743. u64 reserved_36_39 : 4;
  744. u64 bus_width : 3;
  745. u64 reserved_43_47 : 5;
  746. u64 hs_timing : 1;
  747. u64 hs200_timing : 1;
  748. u64 hs400_timing : 1;
  749. u64 reserved_51_63 : 13;
  750. } cn96xxp1;
  751. /* struct mio_emm_modex_s cn96xxp3; */
  752. /* struct mio_emm_modex_s cnf95xx; */
  753. };
  754. static inline u64 MIO_EMM_MODEX(u64 a)
  755. __attribute__ ((pure, always_inline));
  756. static inline u64 MIO_EMM_MODEX(u64 a)
  757. {
  758. return 0x2008 + 8 * a;
  759. }
  760. /**
  761. * Register (RSL) mio_emm_msix_pba#
  762. *
  763. * eMMC MSI-X Pending Bit Array Registers This register is the MSI-X PBA
  764. * table; the bit number is indexed by the MIO_EMM_INT_VEC_E enumeration.
  765. */
  766. union mio_emm_msix_pbax {
  767. u64 u;
  768. struct mio_emm_msix_pbax_s {
  769. u64 pend : 64;
  770. } s;
  771. /* struct mio_emm_msix_pbax_s cn; */
  772. };
  773. static inline u64 MIO_EMM_MSIX_PBAX(u64 a)
  774. __attribute__ ((pure, always_inline));
  775. static inline u64 MIO_EMM_MSIX_PBAX(u64 a)
  776. {
  777. return 0xf0000 + 8 * a;
  778. }
  779. /**
  780. * Register (RSL) mio_emm_msix_vec#_addr
  781. *
  782. * eMMC MSI-X Vector-Table Address Register This register is the MSI-X
  783. * vector table, indexed by the MIO_EMM_INT_VEC_E enumeration.
  784. */
  785. union mio_emm_msix_vecx_addr {
  786. u64 u;
  787. struct mio_emm_msix_vecx_addr_s {
  788. u64 secvec : 1;
  789. u64 reserved_1 : 1;
  790. u64 addr : 51;
  791. u64 reserved_53_63 : 11;
  792. } s;
  793. struct mio_emm_msix_vecx_addr_cn8 {
  794. u64 secvec : 1;
  795. u64 reserved_1 : 1;
  796. u64 addr : 47;
  797. u64 reserved_49_63 : 15;
  798. } cn8;
  799. /* struct mio_emm_msix_vecx_addr_s cn9; */
  800. };
  801. static inline u64 MIO_EMM_MSIX_VECX_ADDR(u64 a)
  802. __attribute__ ((pure, always_inline));
  803. static inline u64 MIO_EMM_MSIX_VECX_ADDR(u64 a)
  804. {
  805. return 0 + 0x10 * a;
  806. }
  807. /**
  808. * Register (RSL) mio_emm_msix_vec#_ctl
  809. *
  810. * eMMC MSI-X Vector-Table Control and Data Register This register is the
  811. * MSI-X vector table, indexed by the MIO_EMM_INT_VEC_E enumeration.
  812. */
  813. union mio_emm_msix_vecx_ctl {
  814. u64 u;
  815. struct mio_emm_msix_vecx_ctl_s {
  816. u64 data : 32;
  817. u64 mask : 1;
  818. u64 reserved_33_63 : 31;
  819. } s;
  820. struct mio_emm_msix_vecx_ctl_cn8 {
  821. u64 data : 20;
  822. u64 reserved_20_31 : 12;
  823. u64 mask : 1;
  824. u64 reserved_33_63 : 31;
  825. } cn8;
  826. /* struct mio_emm_msix_vecx_ctl_s cn9; */
  827. };
  828. static inline u64 MIO_EMM_MSIX_VECX_CTL(u64 a)
  829. __attribute__ ((pure, always_inline));
  830. static inline u64 MIO_EMM_MSIX_VECX_CTL(u64 a)
  831. {
  832. return 8 + 0x10 * a;
  833. }
  834. /**
  835. * Register (RSL) mio_emm_rca
  836. *
  837. * eMMC Relative Card Address Register
  838. */
  839. union mio_emm_rca {
  840. u64 u;
  841. struct mio_emm_rca_s {
  842. u64 card_rca : 16;
  843. u64 reserved_16_63 : 48;
  844. } s;
  845. /* struct mio_emm_rca_s cn; */
  846. };
  847. static inline u64 MIO_EMM_RCA(void)
  848. __attribute__ ((pure, always_inline));
  849. static inline u64 MIO_EMM_RCA(void)
  850. {
  851. return 0x20a0;
  852. }
  853. /**
  854. * Register (RSL) mio_emm_rsp_hi
  855. *
  856. * eMMC Response Data High Register
  857. */
  858. union mio_emm_rsp_hi {
  859. u64 u;
  860. struct mio_emm_rsp_hi_s {
  861. u64 dat : 64;
  862. } s;
  863. /* struct mio_emm_rsp_hi_s cn; */
  864. };
  865. static inline u64 MIO_EMM_RSP_HI(void)
  866. __attribute__ ((pure, always_inline));
  867. static inline u64 MIO_EMM_RSP_HI(void)
  868. {
  869. return 0x2070;
  870. }
  871. /**
  872. * Register (RSL) mio_emm_rsp_lo
  873. *
  874. * eMMC Response Data Low Register
  875. */
  876. union mio_emm_rsp_lo {
  877. u64 u;
  878. struct mio_emm_rsp_lo_s {
  879. u64 dat : 64;
  880. } s;
  881. /* struct mio_emm_rsp_lo_s cn; */
  882. };
  883. static inline u64 MIO_EMM_RSP_LO(void)
  884. __attribute__ ((pure, always_inline));
  885. static inline u64 MIO_EMM_RSP_LO(void)
  886. {
  887. return 0x2068;
  888. }
  889. /**
  890. * Register (RSL) mio_emm_rsp_sts
  891. *
  892. * eMMC Response Status Register
  893. */
  894. union mio_emm_rsp_sts {
  895. u64 u;
  896. struct mio_emm_rsp_sts_s {
  897. u64 cmd_done : 1;
  898. u64 cmd_idx : 6;
  899. u64 cmd_type : 2;
  900. u64 rsp_type : 3;
  901. u64 rsp_val : 1;
  902. u64 rsp_bad_sts : 1;
  903. u64 rsp_crc_err : 1;
  904. u64 rsp_timeout : 1;
  905. u64 stp_val : 1;
  906. u64 stp_bad_sts : 1;
  907. u64 stp_crc_err : 1;
  908. u64 stp_timeout : 1;
  909. u64 rsp_busybit : 1;
  910. u64 blk_crc_err : 1;
  911. u64 blk_timeout : 1;
  912. u64 dbuf : 1;
  913. u64 reserved_24_27 : 4;
  914. u64 dbuf_err : 1;
  915. u64 reserved_29_54 : 26;
  916. u64 acc_timeout : 1;
  917. u64 dma_pend : 1;
  918. u64 dma_val : 1;
  919. u64 switch_val : 1;
  920. u64 cmd_val : 1;
  921. u64 bus_id : 2;
  922. u64 reserved_62_63 : 2;
  923. } s;
  924. /* struct mio_emm_rsp_sts_s cn; */
  925. };
  926. static inline u64 MIO_EMM_RSP_STS(void)
  927. __attribute__ ((pure, always_inline));
  928. static inline u64 MIO_EMM_RSP_STS(void)
  929. {
  930. return 0x2060;
  931. }
  932. /**
  933. * Register (RSL) mio_emm_sample
  934. *
  935. * eMMC Sampling Register
  936. */
  937. union mio_emm_sample {
  938. u64 u;
  939. struct mio_emm_sample_s {
  940. u64 dat_cnt : 10;
  941. u64 reserved_10_15 : 6;
  942. u64 cmd_cnt : 10;
  943. u64 reserved_26_63 : 38;
  944. } s;
  945. /* struct mio_emm_sample_s cn; */
  946. };
  947. static inline u64 MIO_EMM_SAMPLE(void)
  948. __attribute__ ((pure, always_inline));
  949. static inline u64 MIO_EMM_SAMPLE(void)
  950. {
  951. return 0x2090;
  952. }
  953. /**
  954. * Register (RSL) mio_emm_sts_mask
  955. *
  956. * eMMC Status Mask Register
  957. */
  958. union mio_emm_sts_mask {
  959. u64 u;
  960. struct mio_emm_sts_mask_s {
  961. u64 sts_msk : 32;
  962. u64 reserved_32_63 : 32;
  963. } s;
  964. /* struct mio_emm_sts_mask_s cn; */
  965. };
  966. static inline u64 MIO_EMM_STS_MASK(void)
  967. __attribute__ ((pure, always_inline));
  968. static inline u64 MIO_EMM_STS_MASK(void)
  969. {
  970. return 0x2098;
  971. }
  972. /**
  973. * Register (RSL) mio_emm_switch
  974. *
  975. * eMMC Operating Mode Switch Register This register allows software to
  976. * change eMMC related parameters associated with a specific BUS_ID. The
  977. * MIO_EMM_MODE() registers contain the current setting for each BUS.
  978. * This register is also used to switch the [CLK_HI] and [CLK_LO]
  979. * settings associated with the common EMMC_CLK. These settings can only
  980. * be changed when [BUS_ID] = 0.
  981. */
  982. union mio_emm_switch {
  983. u64 u;
  984. struct mio_emm_switch_s {
  985. u64 clk_lo : 16;
  986. u64 clk_hi : 16;
  987. u64 power_class : 4;
  988. u64 clk_swap : 1;
  989. u64 reserved_37_39 : 3;
  990. u64 bus_width : 3;
  991. u64 reserved_43_47 : 5;
  992. u64 hs_timing : 1;
  993. u64 hs200_timing : 1;
  994. u64 hs400_timing : 1;
  995. u64 reserved_51_55 : 5;
  996. u64 switch_err2 : 1;
  997. u64 switch_err1 : 1;
  998. u64 switch_err0 : 1;
  999. u64 switch_exe : 1;
  1000. u64 bus_id : 2;
  1001. u64 reserved_62_63 : 2;
  1002. } s;
  1003. struct mio_emm_switch_cn8 {
  1004. u64 clk_lo : 16;
  1005. u64 clk_hi : 16;
  1006. u64 power_class : 4;
  1007. u64 reserved_36_39 : 4;
  1008. u64 bus_width : 3;
  1009. u64 reserved_43_47 : 5;
  1010. u64 hs_timing : 1;
  1011. u64 reserved_49_55 : 7;
  1012. u64 switch_err2 : 1;
  1013. u64 switch_err1 : 1;
  1014. u64 switch_err0 : 1;
  1015. u64 switch_exe : 1;
  1016. u64 bus_id : 2;
  1017. u64 reserved_62_63 : 2;
  1018. } cn8;
  1019. struct mio_emm_switch_cn96xxp1 {
  1020. u64 clk_lo : 16;
  1021. u64 clk_hi : 16;
  1022. u64 power_class : 4;
  1023. u64 reserved_36_39 : 4;
  1024. u64 bus_width : 3;
  1025. u64 reserved_43_47 : 5;
  1026. u64 hs_timing : 1;
  1027. u64 hs200_timing : 1;
  1028. u64 hs400_timing : 1;
  1029. u64 reserved_51_55 : 5;
  1030. u64 switch_err2 : 1;
  1031. u64 switch_err1 : 1;
  1032. u64 switch_err0 : 1;
  1033. u64 switch_exe : 1;
  1034. u64 bus_id : 2;
  1035. u64 reserved_62_63 : 2;
  1036. } cn96xxp1;
  1037. /* struct mio_emm_switch_s cn96xxp3; */
  1038. /* struct mio_emm_switch_s cnf95xx; */
  1039. };
  1040. static inline u64 MIO_EMM_SWITCH(void)
  1041. __attribute__ ((pure, always_inline));
  1042. static inline u64 MIO_EMM_SWITCH(void)
  1043. {
  1044. return 0x2048;
  1045. }
  1046. /**
  1047. * Register (RSL) mio_emm_tap
  1048. *
  1049. * eMMC TAP Delay Register This register indicates the delay line
  1050. * characteristics.
  1051. */
  1052. union mio_emm_tap {
  1053. u64 u;
  1054. struct mio_emm_tap_s {
  1055. u64 delay : 8;
  1056. u64 reserved_8_63 : 56;
  1057. } s;
  1058. /* struct mio_emm_tap_s cn; */
  1059. };
  1060. static inline u64 MIO_EMM_TAP(void)
  1061. __attribute__ ((pure, always_inline));
  1062. static inline u64 MIO_EMM_TAP(void)
  1063. {
  1064. return 0x20c8;
  1065. }
  1066. /**
  1067. * Register (RSL) mio_emm_timing
  1068. *
  1069. * eMMC Timing Register This register determines the number of tap delays
  1070. * the EMM_DAT, EMM_DS, and EMM_CMD lines are transmitted or received in
  1071. * relation to EMM_CLK. These values should only be changed when the eMMC
  1072. * bus is idle.
  1073. */
  1074. union mio_emm_timing {
  1075. u64 u;
  1076. struct mio_emm_timing_s {
  1077. u64 data_out_tap : 6;
  1078. u64 reserved_6_15 : 10;
  1079. u64 data_in_tap : 6;
  1080. u64 reserved_22_31 : 10;
  1081. u64 cmd_out_tap : 6;
  1082. u64 reserved_38_47 : 10;
  1083. u64 cmd_in_tap : 6;
  1084. u64 reserved_54_63 : 10;
  1085. } s;
  1086. /* struct mio_emm_timing_s cn; */
  1087. };
  1088. static inline u64 MIO_EMM_TIMING(void)
  1089. __attribute__ ((pure, always_inline));
  1090. static inline u64 MIO_EMM_TIMING(void)
  1091. {
  1092. return 0x20d0;
  1093. }
  1094. /**
  1095. * Register (RSL) mio_emm_wdog
  1096. *
  1097. * eMMC Watchdog Register
  1098. */
  1099. union mio_emm_wdog {
  1100. u64 u;
  1101. struct mio_emm_wdog_s {
  1102. u64 clk_cnt : 26;
  1103. u64 reserved_26_63 : 38;
  1104. } s;
  1105. /* struct mio_emm_wdog_s cn; */
  1106. };
  1107. static inline u64 MIO_EMM_WDOG(void)
  1108. __attribute__ ((pure, always_inline));
  1109. static inline u64 MIO_EMM_WDOG(void)
  1110. {
  1111. return 0x2088;
  1112. }
  1113. #endif /* __CSRS_MIO_EMM_H__ */