board.h 4.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0
  2. *
  3. * Copyright (C) 2018 Marvell International Ltd.
  4. *
  5. * https://spdx.org/licenses
  6. */
  7. #ifndef __BOARD_H__
  8. #define __BOARD_H__
  9. #include <asm/arch/soc.h>
  10. #define MAX_LMAC_PER_BGX 4
  11. #define LMAC_CNT MAX_LMAC_PER_BGX
  12. #if defined(CONFIG_TARGET_OCTEONTX_81XX)
  13. /** Maximum number of BGX interfaces per CPU node */
  14. #define MAX_BGX_PER_NODE 3
  15. #define OCTEONTX_XCV /* RGMII Interface */
  16. #elif defined(CONFIG_TARGET_OCTEONTX_83XX)
  17. /** Maximum number of BGX interfaces per CPU node */
  18. #define MAX_BGX_PER_NODE 4
  19. #endif
  20. /** Reg offsets */
  21. #define RST_BOOT 0x87E006001600ULL
  22. /** Structure definitions */
  23. /**
  24. * Register (RSL) rst_boot
  25. *
  26. * RST Boot Register This register is not accessible through ROM scripts;
  27. * see SCR_WRITE32_S[ADDR].
  28. */
  29. union rst_boot {
  30. u64 u;
  31. struct rst_boot_s {
  32. u64 rboot_pin : 1;
  33. u64 rboot : 1;
  34. u64 reserved_2_32 : 31;
  35. u64 pnr_mul : 6;
  36. u64 reserved_39 : 1;
  37. u64 c_mul : 7;
  38. u64 reserved_47_52 : 6;
  39. u64 gpio_ejtag : 1;
  40. u64 mcp_jtagdis : 1;
  41. u64 dis_scan : 1;
  42. u64 dis_huk : 1;
  43. u64 vrm_err : 1;
  44. u64 jt_tstmode : 1;
  45. u64 ckill_ppdis : 1;
  46. u64 trusted_mode : 1;
  47. u64 reserved_61_62 : 2;
  48. u64 chipkill : 1;
  49. } s;
  50. struct rst_boot_cn81xx {
  51. u64 rboot_pin : 1;
  52. u64 rboot : 1;
  53. u64 lboot : 10;
  54. u64 lboot_ext23 : 6;
  55. u64 lboot_ext45 : 6;
  56. u64 lboot_jtg : 1;
  57. u64 lboot_ckill : 1;
  58. u64 reserved_26_29 : 4;
  59. u64 lboot_oci : 3;
  60. u64 pnr_mul : 6;
  61. u64 reserved_39 : 1;
  62. u64 c_mul : 7;
  63. u64 reserved_47_54 : 8;
  64. u64 dis_scan : 1;
  65. u64 dis_huk : 1;
  66. u64 vrm_err : 1;
  67. u64 jt_tstmode : 1;
  68. u64 ckill_ppdis : 1;
  69. u64 trusted_mode : 1;
  70. u64 ejtagdis : 1;
  71. u64 jtcsrdis : 1;
  72. u64 chipkill : 1;
  73. } cn81xx;
  74. struct rst_boot_cn83xx {
  75. u64 rboot_pin : 1;
  76. u64 rboot : 1;
  77. u64 lboot : 10;
  78. u64 lboot_ext23 : 6;
  79. u64 lboot_ext45 : 6;
  80. u64 lboot_jtg : 1;
  81. u64 lboot_ckill : 1;
  82. u64 lboot_pf_flr : 4;
  83. u64 lboot_oci : 3;
  84. u64 pnr_mul : 6;
  85. u64 reserved_39 : 1;
  86. u64 c_mul : 7;
  87. u64 reserved_47_54 : 8;
  88. u64 dis_scan : 1;
  89. u64 dis_huk : 1;
  90. u64 vrm_err : 1;
  91. u64 jt_tstmode : 1;
  92. u64 ckill_ppdis : 1;
  93. u64 trusted_mode : 1;
  94. u64 ejtagdis : 1;
  95. u64 jtcsrdis : 1;
  96. u64 chipkill : 1;
  97. } cn83xx;
  98. };
  99. extern unsigned long fdt_base_addr;
  100. /** Function definitions */
  101. void mem_map_fill(void);
  102. int octeontx_board_has_pmp(void);
  103. const char *fdt_get_board_model(void);
  104. const char *fdt_get_board_serial(void);
  105. const char *fdt_get_board_revision(void);
  106. void fdt_parse_phy_info(void);
  107. void fdt_board_get_ethaddr(int bgx, int lmac, unsigned char *eth);
  108. void bgx_set_board_info(int bgx_id, int *mdio_bus, int *phy_addr,
  109. bool *autoneg_dis, bool *lmac_reg, bool *lmac_enable);
  110. #endif /* __BOARD_H__ */