colibri_imx6.c 32 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
  4. * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
  5. * Copyright (C) 2014-2019, Toradex AG
  6. * copied from nitrogen6x
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <env.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/crm_regs.h>
  13. #include <asm/arch/imx-regs.h>
  14. #include <asm/arch/mx6-ddr.h>
  15. #include <asm/arch/mx6-pins.h>
  16. #include <asm/arch/mxc_hdmi.h>
  17. #include <asm/arch/sys_proto.h>
  18. #include <asm/bootm.h>
  19. #include <asm/gpio.h>
  20. #include <asm/mach-imx/boot_mode.h>
  21. #include <asm/mach-imx/iomux-v3.h>
  22. #include <asm/mach-imx/sata.h>
  23. #include <asm/mach-imx/video.h>
  24. #include <cpu.h>
  25. #include <dm/platform_data/serial_mxc.h>
  26. #include <environment.h>
  27. #include <fsl_esdhc_imx.h>
  28. #include <imx_thermal.h>
  29. #include <micrel.h>
  30. #include <miiphy.h>
  31. #include <netdev.h>
  32. #include <cpu.h>
  33. #include "../common/tdx-cfg-block.h"
  34. #ifdef CONFIG_TDX_CMD_IMX_MFGR
  35. #include "pf0100.h"
  36. #endif
  37. DECLARE_GLOBAL_DATA_PTR;
  38. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  39. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  40. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  41. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  42. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
  43. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  44. #define USDHC_EMMC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  45. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  46. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  47. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  48. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  49. #define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
  50. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  51. PAD_CTL_SRE_SLOW)
  52. #define NO_PULLUP ( \
  53. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  54. PAD_CTL_SRE_SLOW)
  55. #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
  56. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  57. PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  58. #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
  59. int dram_init(void)
  60. {
  61. /* use the DDR controllers configured size */
  62. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  63. (ulong)imx_ddr_size());
  64. return 0;
  65. }
  66. /* Colibri UARTA */
  67. iomux_v3_cfg_t const uart1_pads[] = {
  68. MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  69. MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  70. };
  71. #if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
  72. /* Colibri MMC */
  73. iomux_v3_cfg_t const usdhc1_pads[] = {
  74. MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  75. MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  76. MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  77. MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  78. MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  79. MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  80. MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  81. # define GPIO_MMC_CD IMX_GPIO_NR(2, 5)
  82. };
  83. /* eMMC */
  84. iomux_v3_cfg_t const usdhc3_pads[] = {
  85. MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  86. MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  87. MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  88. MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  89. MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  90. MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  91. MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  92. MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  93. MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  94. MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
  95. MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  96. };
  97. #endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
  98. iomux_v3_cfg_t const enet_pads[] = {
  99. MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  100. MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  101. MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  102. MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  103. MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
  104. MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  105. MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  106. MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  107. MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  108. MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
  109. };
  110. static void setup_iomux_enet(void)
  111. {
  112. imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
  113. }
  114. /* mux auxiliary pins to GPIO, so they can be used from the U-Boot cmdline */
  115. iomux_v3_cfg_t const gpio_pads[] = {
  116. /* ADDRESS[17:18] [25] used as GPIO */
  117. MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
  118. MUX_MODE_SION,
  119. MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(WEAK_PULLUP) |
  120. MUX_MODE_SION,
  121. MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(WEAK_PULLUP) |
  122. MUX_MODE_SION,
  123. /* ADDRESS[19:24] used as GPIO */
  124. MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(WEAK_PULLUP) |
  125. MUX_MODE_SION,
  126. MX6_PAD_DISP0_DAT22__GPIO5_IO16 | MUX_PAD_CTRL(WEAK_PULLUP) |
  127. MUX_MODE_SION,
  128. MX6_PAD_DISP0_DAT21__GPIO5_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
  129. MUX_MODE_SION,
  130. MX6_PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
  131. MUX_MODE_SION,
  132. MX6_PAD_DISP0_DAT19__GPIO5_IO13 | MUX_PAD_CTRL(WEAK_PULLUP) |
  133. MUX_MODE_SION,
  134. MX6_PAD_DISP0_DAT18__GPIO5_IO12 | MUX_PAD_CTRL(WEAK_PULLUP) |
  135. MUX_MODE_SION,
  136. /* DATA[16:29] [31] used as GPIO */
  137. MX6_PAD_EIM_LBA__GPIO2_IO27 | MUX_PAD_CTRL(WEAK_PULLUP) |
  138. MUX_MODE_SION,
  139. MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(WEAK_PULLUP) |
  140. MUX_MODE_SION,
  141. MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(WEAK_PULLUP) |
  142. MUX_MODE_SION,
  143. MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
  144. MUX_MODE_SION,
  145. MX6_PAD_NANDF_RB0__GPIO6_IO10 | MUX_PAD_CTRL(WEAK_PULLUP) |
  146. MUX_MODE_SION,
  147. MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) |
  148. MUX_MODE_SION,
  149. MX6_PAD_NANDF_WP_B__GPIO6_IO09 | MUX_PAD_CTRL(WEAK_PULLUP) |
  150. MUX_MODE_SION,
  151. MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
  152. MUX_MODE_SION,
  153. MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(WEAK_PULLUP) |
  154. MUX_MODE_SION,
  155. MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(WEAK_PULLUP) |
  156. MUX_MODE_SION,
  157. MX6_PAD_CSI0_MCLK__GPIO5_IO19 | MUX_PAD_CTRL(WEAK_PULLUP) |
  158. MUX_MODE_SION,
  159. MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
  160. MUX_MODE_SION,
  161. MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
  162. MUX_MODE_SION,
  163. MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(WEAK_PULLUP) |
  164. MUX_MODE_SION,
  165. MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(WEAK_PULLUP) |
  166. MUX_MODE_SION,
  167. /* DQM[0:3] used as GPIO */
  168. MX6_PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(WEAK_PULLUP) |
  169. MUX_MODE_SION,
  170. MX6_PAD_EIM_EB1__GPIO2_IO29 | MUX_PAD_CTRL(WEAK_PULLUP) |
  171. MUX_MODE_SION,
  172. MX6_PAD_SD2_DAT2__GPIO1_IO13 | MUX_PAD_CTRL(WEAK_PULLUP) |
  173. MUX_MODE_SION,
  174. MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(WEAK_PULLUP) |
  175. MUX_MODE_SION,
  176. /* RDY used as GPIO */
  177. MX6_PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(WEAK_PULLUP) |
  178. MUX_MODE_SION,
  179. /* ADDRESS[16] DATA[30] used as GPIO */
  180. MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(WEAK_PULLDOWN) |
  181. MUX_MODE_SION,
  182. MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(WEAK_PULLUP) |
  183. MUX_MODE_SION,
  184. /* CSI pins used as GPIO */
  185. MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
  186. MUX_MODE_SION,
  187. MX6_PAD_SD2_CMD__GPIO1_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
  188. MUX_MODE_SION,
  189. MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
  190. MUX_MODE_SION,
  191. MX6_PAD_EIM_D18__GPIO3_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
  192. MUX_MODE_SION,
  193. MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(WEAK_PULLUP) |
  194. MUX_MODE_SION,
  195. MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(WEAK_PULLDOWN) |
  196. MUX_MODE_SION,
  197. MX6_PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) |
  198. MUX_MODE_SION,
  199. MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(WEAK_PULLUP) |
  200. MUX_MODE_SION,
  201. MX6_PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(WEAK_PULLUP) |
  202. MUX_MODE_SION,
  203. MX6_PAD_EIM_A18__GPIO2_IO20 | MUX_PAD_CTRL(WEAK_PULLUP) |
  204. MUX_MODE_SION,
  205. MX6_PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(WEAK_PULLUP) |
  206. MUX_MODE_SION,
  207. MX6_PAD_EIM_D17__GPIO3_IO17 | MUX_PAD_CTRL(WEAK_PULLUP) |
  208. MUX_MODE_SION,
  209. MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(WEAK_PULLUP) |
  210. MUX_MODE_SION,
  211. /* GPIO */
  212. MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(WEAK_PULLUP) |
  213. MUX_MODE_SION,
  214. MX6_PAD_EIM_D27__GPIO3_IO27 | MUX_PAD_CTRL(WEAK_PULLUP) |
  215. MUX_MODE_SION,
  216. MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP) |
  217. MUX_MODE_SION,
  218. MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(WEAK_PULLUP) |
  219. MUX_MODE_SION,
  220. MX6_PAD_ENET_REF_CLK__GPIO1_IO23 | MUX_PAD_CTRL(WEAK_PULLUP) |
  221. MUX_MODE_SION,
  222. MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(WEAK_PULLUP) |
  223. MUX_MODE_SION,
  224. MX6_PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(WEAK_PULLUP) |
  225. MUX_MODE_SION,
  226. MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP) |
  227. MUX_MODE_SION,
  228. MX6_PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) |
  229. MUX_MODE_SION,
  230. MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(WEAK_PULLUP) |
  231. MUX_MODE_SION,
  232. MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) |
  233. MUX_MODE_SION,
  234. /* USBH_OC */
  235. MX6_PAD_EIM_D30__GPIO3_IO30 | MUX_PAD_CTRL(WEAK_PULLUP),
  236. /* USBC_ID */
  237. MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(WEAK_PULLUP),
  238. /* USBC_DET */
  239. MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(WEAK_PULLUP),
  240. };
  241. static void setup_iomux_gpio(void)
  242. {
  243. imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
  244. }
  245. iomux_v3_cfg_t const usb_pads[] = {
  246. /* USBH_PEN */
  247. MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
  248. # define GPIO_USBH_EN IMX_GPIO_NR(3, 31)
  249. };
  250. /*
  251. * UARTs are used in DTE mode, switch the mode on all UARTs before
  252. * any pinmuxing connects a (DCE) output to a transceiver output.
  253. */
  254. #define UCR3 0x88 /* FIFO Control Register */
  255. #define UCR3_RI BIT(8) /* RIDELT DTE mode */
  256. #define UCR3_DCD BIT(9) /* DCDDELT DTE mode */
  257. #define UFCR 0x90 /* FIFO Control Register */
  258. #define UFCR_DCEDTE BIT(6) /* DCE=0 */
  259. static void setup_dtemode_uart(void)
  260. {
  261. setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
  262. setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
  263. setbits_le32((u32 *)(UART3_BASE + UFCR), UFCR_DCEDTE);
  264. clrbits_le32((u32 *)(UART1_BASE + UCR3), UCR3_DCD | UCR3_RI);
  265. clrbits_le32((u32 *)(UART2_BASE + UCR3), UCR3_DCD | UCR3_RI);
  266. clrbits_le32((u32 *)(UART3_BASE + UCR3), UCR3_DCD | UCR3_RI);
  267. }
  268. static void setup_iomux_uart(void)
  269. {
  270. setup_dtemode_uart();
  271. imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  272. }
  273. #ifdef CONFIG_USB_EHCI_MX6
  274. int board_ehci_hcd_init(int port)
  275. {
  276. imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
  277. return 0;
  278. }
  279. #endif
  280. #if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
  281. /* use the following sequence: eMMC, MMC */
  282. struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
  283. {USDHC3_BASE_ADDR},
  284. {USDHC1_BASE_ADDR},
  285. };
  286. int board_mmc_getcd(struct mmc *mmc)
  287. {
  288. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  289. int ret = true; /* default: assume inserted */
  290. switch (cfg->esdhc_base) {
  291. case USDHC1_BASE_ADDR:
  292. gpio_request(GPIO_MMC_CD, "MMC_CD");
  293. gpio_direction_input(GPIO_MMC_CD);
  294. ret = !gpio_get_value(GPIO_MMC_CD);
  295. break;
  296. }
  297. return ret;
  298. }
  299. int board_mmc_init(bd_t *bis)
  300. {
  301. struct src *psrc = (struct src *)SRC_BASE_ADDR;
  302. unsigned reg = readl(&psrc->sbmr1) >> 11;
  303. /*
  304. * Upon reading BOOT_CFG register the following map is done:
  305. * Bit 11 and 12 of BOOT_CFG register can determine the current
  306. * mmc port
  307. * 0x1 SD1
  308. * 0x2 SD2
  309. * 0x3 SD4
  310. */
  311. switch (reg & 0x3) {
  312. case 0x0:
  313. imx_iomux_v3_setup_multiple_pads(
  314. usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
  315. usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
  316. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  317. gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
  318. break;
  319. case 0x2:
  320. imx_iomux_v3_setup_multiple_pads(
  321. usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  322. usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
  323. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  324. gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
  325. break;
  326. default:
  327. puts("MMC boot device not available");
  328. }
  329. return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  330. }
  331. #endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
  332. int board_phy_config(struct phy_device *phydev)
  333. {
  334. if (phydev->drv->config)
  335. phydev->drv->config(phydev);
  336. return 0;
  337. }
  338. int board_eth_init(bd_t *bis)
  339. {
  340. struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  341. uint32_t base = IMX_FEC_BASE;
  342. struct mii_dev *bus = NULL;
  343. struct phy_device *phydev = NULL;
  344. int ret;
  345. /* provide the PHY clock from the i.MX 6 */
  346. ret = enable_fec_anatop_clock(0, ENET_50MHZ);
  347. if (ret)
  348. return ret;
  349. /* set gpr1[ENET_CLK_SEL] */
  350. setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
  351. setup_iomux_enet();
  352. #ifdef CONFIG_FEC_MXC
  353. bus = fec_get_miibus(base, -1);
  354. if (!bus)
  355. return 0;
  356. /* scan PHY 1..7 */
  357. phydev = phy_find_by_mask(bus, 0xff, PHY_INTERFACE_MODE_RMII);
  358. if (!phydev) {
  359. free(bus);
  360. puts("no PHY found\n");
  361. return 0;
  362. }
  363. phy_reset(phydev);
  364. printf("using PHY at %d\n", phydev->addr);
  365. ret = fec_probe(bis, -1, base, bus, phydev);
  366. if (ret) {
  367. printf("FEC MXC: %s:failed\n", __func__);
  368. free(phydev);
  369. free(bus);
  370. }
  371. #endif /* CONFIG_FEC_MXC */
  372. return 0;
  373. }
  374. static iomux_v3_cfg_t const pwr_intb_pads[] = {
  375. /*
  376. * the bootrom sets the iomux to vselect, potentially connecting
  377. * two outputs. Set this back to GPIO
  378. */
  379. MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
  380. };
  381. #if defined(CONFIG_VIDEO_IPUV3)
  382. static iomux_v3_cfg_t const backlight_pads[] = {
  383. /* Backlight On */
  384. MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL) | MUX_MODE_SION,
  385. #define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 26)
  386. /* Backlight PWM, used as GPIO in U-Boot */
  387. MX6_PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PULLUP),
  388. MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL) |
  389. MUX_MODE_SION,
  390. #define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 9)
  391. };
  392. static iomux_v3_cfg_t const rgb_pads[] = {
  393. MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
  394. MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
  395. MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
  396. MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
  397. MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
  398. MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
  399. MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
  400. MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
  401. MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
  402. MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
  403. MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
  404. MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
  405. MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
  406. MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
  407. MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
  408. MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
  409. MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
  410. MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
  411. MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
  412. MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
  413. MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
  414. MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
  415. };
  416. static void do_enable_hdmi(struct display_info_t const *dev)
  417. {
  418. imx_enable_hdmi_phy();
  419. }
  420. static void enable_rgb(struct display_info_t const *dev)
  421. {
  422. imx_iomux_v3_setup_multiple_pads(
  423. rgb_pads,
  424. ARRAY_SIZE(rgb_pads));
  425. gpio_direction_output(RGB_BACKLIGHT_GP, 1);
  426. gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
  427. }
  428. static int detect_default(struct display_info_t const *dev)
  429. {
  430. (void) dev;
  431. return 1;
  432. }
  433. struct display_info_t const displays[] = {{
  434. .bus = -1,
  435. .addr = 0,
  436. .pixfmt = IPU_PIX_FMT_RGB24,
  437. .detect = detect_hdmi,
  438. .enable = do_enable_hdmi,
  439. .mode = {
  440. .name = "HDMI",
  441. .refresh = 60,
  442. .xres = 1024,
  443. .yres = 768,
  444. .pixclock = 15385,
  445. .left_margin = 220,
  446. .right_margin = 40,
  447. .upper_margin = 21,
  448. .lower_margin = 7,
  449. .hsync_len = 60,
  450. .vsync_len = 10,
  451. .sync = FB_SYNC_EXT,
  452. .vmode = FB_VMODE_NONINTERLACED
  453. } }, {
  454. .bus = -1,
  455. .addr = 0,
  456. .pixfmt = IPU_PIX_FMT_RGB666,
  457. .detect = detect_default,
  458. .enable = enable_rgb,
  459. .mode = {
  460. .name = "vga-rgb",
  461. .refresh = 60,
  462. .xres = 640,
  463. .yres = 480,
  464. .pixclock = 33000,
  465. .left_margin = 48,
  466. .right_margin = 16,
  467. .upper_margin = 31,
  468. .lower_margin = 11,
  469. .hsync_len = 96,
  470. .vsync_len = 2,
  471. .sync = 0,
  472. .vmode = FB_VMODE_NONINTERLACED
  473. } }, {
  474. .bus = -1,
  475. .addr = 0,
  476. .pixfmt = IPU_PIX_FMT_RGB666,
  477. .enable = enable_rgb,
  478. .mode = {
  479. .name = "wvga-rgb",
  480. .refresh = 60,
  481. .xres = 800,
  482. .yres = 480,
  483. .pixclock = 25000,
  484. .left_margin = 40,
  485. .right_margin = 88,
  486. .upper_margin = 33,
  487. .lower_margin = 10,
  488. .hsync_len = 128,
  489. .vsync_len = 2,
  490. .sync = 0,
  491. .vmode = FB_VMODE_NONINTERLACED
  492. } } };
  493. size_t display_count = ARRAY_SIZE(displays);
  494. static void setup_display(void)
  495. {
  496. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  497. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  498. int reg;
  499. enable_ipu_clock();
  500. imx_setup_hdmi();
  501. /* Turn on LDB0,IPU,IPU DI0 clocks */
  502. reg = __raw_readl(&mxc_ccm->CCGR3);
  503. reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
  504. writel(reg, &mxc_ccm->CCGR3);
  505. /* set LDB0, LDB1 clk select to 011/011 */
  506. reg = readl(&mxc_ccm->cs2cdr);
  507. reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
  508. |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
  509. reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
  510. |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
  511. writel(reg, &mxc_ccm->cs2cdr);
  512. reg = readl(&mxc_ccm->cscmr2);
  513. reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
  514. writel(reg, &mxc_ccm->cscmr2);
  515. reg = readl(&mxc_ccm->chsccdr);
  516. reg |= (CHSCCDR_CLK_SEL_LDB_DI0
  517. <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  518. writel(reg, &mxc_ccm->chsccdr);
  519. reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
  520. |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
  521. |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
  522. |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
  523. |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
  524. |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
  525. |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
  526. |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
  527. |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
  528. writel(reg, &iomux->gpr[2]);
  529. reg = readl(&iomux->gpr[3]);
  530. reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
  531. |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
  532. | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
  533. <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
  534. writel(reg, &iomux->gpr[3]);
  535. /* backlight unconditionally on for now */
  536. imx_iomux_v3_setup_multiple_pads(backlight_pads,
  537. ARRAY_SIZE(backlight_pads));
  538. /* use 0 for EDT 7", use 1 for LG fullHD panel */
  539. gpio_request(RGB_BACKLIGHTPWM_GP, "PWM<A>");
  540. gpio_request(RGB_BACKLIGHT_GP, "BL_ON");
  541. gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
  542. gpio_direction_output(RGB_BACKLIGHT_GP, 1);
  543. }
  544. /*
  545. * Backlight off before OS handover
  546. */
  547. void board_preboot_os(void)
  548. {
  549. gpio_direction_output(RGB_BACKLIGHTPWM_GP, 1);
  550. gpio_direction_output(RGB_BACKLIGHT_GP, 0);
  551. }
  552. #endif /* defined(CONFIG_VIDEO_IPUV3) */
  553. int board_early_init_f(void)
  554. {
  555. imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
  556. ARRAY_SIZE(pwr_intb_pads));
  557. setup_iomux_uart();
  558. return 0;
  559. }
  560. /*
  561. * Do not overwrite the console
  562. * Use always serial for U-Boot console
  563. */
  564. int overwrite_console(void)
  565. {
  566. return 1;
  567. }
  568. int board_init(void)
  569. {
  570. /* address of boot parameters */
  571. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  572. #if defined(CONFIG_VIDEO_IPUV3)
  573. setup_display();
  574. #endif
  575. #ifdef CONFIG_TDX_CMD_IMX_MFGR
  576. (void) pmic_init();
  577. #endif
  578. #ifdef CONFIG_SATA
  579. setup_sata();
  580. #endif
  581. setup_iomux_gpio();
  582. return 0;
  583. }
  584. #ifdef CONFIG_BOARD_LATE_INIT
  585. int board_late_init(void)
  586. {
  587. #if defined(CONFIG_REVISION_TAG) && \
  588. defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
  589. char env_str[256];
  590. u32 rev;
  591. rev = get_board_rev();
  592. snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
  593. env_set("board_rev", env_str);
  594. #endif
  595. #ifdef CONFIG_CMD_USB_SDP
  596. if (is_boot_from_usb()) {
  597. printf("Serial Downloader recovery mode, using sdp command\n");
  598. env_set("bootdelay", "0");
  599. env_set("bootcmd", "sdp 0");
  600. }
  601. #endif /* CONFIG_CMD_USB_SDP */
  602. return 0;
  603. }
  604. #endif /* CONFIG_BOARD_LATE_INIT */
  605. int checkboard(void)
  606. {
  607. char it[] = " IT";
  608. int minc, maxc;
  609. switch (get_cpu_temp_grade(&minc, &maxc)) {
  610. case TEMP_AUTOMOTIVE:
  611. case TEMP_INDUSTRIAL:
  612. break;
  613. case TEMP_EXTCOMMERCIAL:
  614. default:
  615. it[0] = 0;
  616. };
  617. printf("Model: Toradex Colibri iMX6 %s %sMB%s\n",
  618. is_cpu_type(MXC_CPU_MX6DL) ? "DualLite" : "Solo",
  619. (gd->ram_size == 0x20000000) ? "512" : "256", it);
  620. return 0;
  621. }
  622. #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
  623. int ft_board_setup(void *blob, bd_t *bd)
  624. {
  625. u32 cma_size;
  626. ft_common_board_setup(blob, bd);
  627. cma_size = env_get_ulong("cma-size", 10, 320 * 1024 * 1024);
  628. cma_size = min((u32)(gd->ram_size >> 1), cma_size);
  629. fdt_setprop_u32(blob,
  630. fdt_path_offset(blob, "/reserved-memory/linux,cma"),
  631. "size",
  632. cma_size);
  633. return 0;
  634. }
  635. #endif
  636. #ifdef CONFIG_CMD_BMODE
  637. static const struct boot_mode board_boot_modes[] = {
  638. {"mmc", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
  639. {NULL, 0},
  640. };
  641. #endif
  642. int misc_init_r(void)
  643. {
  644. #ifdef CONFIG_CMD_BMODE
  645. add_board_boot_modes(board_boot_modes);
  646. #endif
  647. return 0;
  648. }
  649. #ifdef CONFIG_LDO_BYPASS_CHECK
  650. /* TODO, use external pmic, for now always ldo_enable */
  651. void ldo_mode_set(int ldo_bypass)
  652. {
  653. return;
  654. }
  655. #endif
  656. #ifdef CONFIG_SPL_BUILD
  657. #include <spl.h>
  658. #include <linux/libfdt.h>
  659. #include "asm/arch/mx6dl-ddr.h"
  660. #include "asm/arch/iomux.h"
  661. #include "asm/arch/crm_regs.h"
  662. static int mx6s_dcd_table[] = {
  663. /* ddr-setup.cfg */
  664. MX6_IOM_DRAM_SDQS0, 0x00000030,
  665. MX6_IOM_DRAM_SDQS1, 0x00000030,
  666. MX6_IOM_DRAM_SDQS2, 0x00000030,
  667. MX6_IOM_DRAM_SDQS3, 0x00000030,
  668. MX6_IOM_DRAM_SDQS4, 0x00000030,
  669. MX6_IOM_DRAM_SDQS5, 0x00000030,
  670. MX6_IOM_DRAM_SDQS6, 0x00000030,
  671. MX6_IOM_DRAM_SDQS7, 0x00000030,
  672. MX6_IOM_GRP_B0DS, 0x00000030,
  673. MX6_IOM_GRP_B1DS, 0x00000030,
  674. MX6_IOM_GRP_B2DS, 0x00000030,
  675. MX6_IOM_GRP_B3DS, 0x00000030,
  676. MX6_IOM_GRP_B4DS, 0x00000030,
  677. MX6_IOM_GRP_B5DS, 0x00000030,
  678. MX6_IOM_GRP_B6DS, 0x00000030,
  679. MX6_IOM_GRP_B7DS, 0x00000030,
  680. MX6_IOM_GRP_ADDDS, 0x00000030,
  681. /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
  682. MX6_IOM_GRP_CTLDS, 0x00000030,
  683. MX6_IOM_DRAM_DQM0, 0x00020030,
  684. MX6_IOM_DRAM_DQM1, 0x00020030,
  685. MX6_IOM_DRAM_DQM2, 0x00020030,
  686. MX6_IOM_DRAM_DQM3, 0x00020030,
  687. MX6_IOM_DRAM_DQM4, 0x00020030,
  688. MX6_IOM_DRAM_DQM5, 0x00020030,
  689. MX6_IOM_DRAM_DQM6, 0x00020030,
  690. MX6_IOM_DRAM_DQM7, 0x00020030,
  691. MX6_IOM_DRAM_CAS, 0x00020030,
  692. MX6_IOM_DRAM_RAS, 0x00020030,
  693. MX6_IOM_DRAM_SDCLK_0, 0x00020030,
  694. MX6_IOM_DRAM_SDCLK_1, 0x00020030,
  695. MX6_IOM_DRAM_RESET, 0x00020030,
  696. MX6_IOM_DRAM_SDCKE0, 0x00003000,
  697. MX6_IOM_DRAM_SDCKE1, 0x00003000,
  698. MX6_IOM_DRAM_SDODT0, 0x00003030,
  699. MX6_IOM_DRAM_SDODT1, 0x00003030,
  700. /* (differential input) */
  701. MX6_IOM_DDRMODE_CTL, 0x00020000,
  702. /* (differential input) */
  703. MX6_IOM_GRP_DDRMODE, 0x00020000,
  704. /* disable ddr pullups */
  705. MX6_IOM_GRP_DDRPKE, 0x00000000,
  706. MX6_IOM_DRAM_SDBA2, 0x00000000,
  707. /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
  708. MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
  709. /* Read data DQ Byte0-3 delay */
  710. MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
  711. MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
  712. MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
  713. MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
  714. MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
  715. MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
  716. MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
  717. MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
  718. /*
  719. * MDMISC mirroring interleaved (row/bank/col)
  720. */
  721. /* TODO: check what the RALAT field does */
  722. MX6_MMDC_P0_MDMISC, 0x00081740,
  723. /*
  724. * MDSCR con_req
  725. */
  726. MX6_MMDC_P0_MDSCR, 0x00008000,
  727. /* 800mhz_2x64mx16.cfg */
  728. MX6_MMDC_P0_MDPDC, 0x0002002D,
  729. MX6_MMDC_P0_MDCFG0, 0x2C305503,
  730. MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
  731. MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
  732. MX6_MMDC_P0_MDRWD, 0x000026D2,
  733. MX6_MMDC_P0_MDOR, 0x00301023,
  734. MX6_MMDC_P0_MDOTC, 0x00333030,
  735. MX6_MMDC_P0_MDPDC, 0x0002556D,
  736. /* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
  737. MX6_MMDC_P0_MDASP, 0x00000017,
  738. /* DDR3 DATA BUS SIZE: 64BIT */
  739. /* MX6_MMDC_P0_MDCTL, 0x821A0000, */
  740. /* DDR3 DATA BUS SIZE: 32BIT */
  741. MX6_MMDC_P0_MDCTL, 0x82190000,
  742. /* Write commands to DDR */
  743. /* Load Mode Registers */
  744. /* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
  745. /* MX6_MMDC_P0_MDSCR, 0x04408032, */
  746. MX6_MMDC_P0_MDSCR, 0x04008032,
  747. MX6_MMDC_P0_MDSCR, 0x00008033,
  748. MX6_MMDC_P0_MDSCR, 0x00048031,
  749. MX6_MMDC_P0_MDSCR, 0x13208030,
  750. /* ZQ calibration */
  751. MX6_MMDC_P0_MDSCR, 0x04008040,
  752. MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
  753. MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
  754. MX6_MMDC_P0_MDREF, 0x00005800,
  755. MX6_MMDC_P0_MPODTCTRL, 0x00000000,
  756. MX6_MMDC_P1_MPODTCTRL, 0x00000000,
  757. MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
  758. MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
  759. MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
  760. MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
  761. MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
  762. MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
  763. MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
  764. MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
  765. MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
  766. MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
  767. MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
  768. MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
  769. MX6_MMDC_P0_MPMUR0, 0x00000800,
  770. MX6_MMDC_P1_MPMUR0, 0x00000800,
  771. MX6_MMDC_P0_MDSCR, 0x00000000,
  772. MX6_MMDC_P0_MAPSR, 0x00011006,
  773. };
  774. static int mx6dl_dcd_table[] = {
  775. /* ddr-setup.cfg */
  776. MX6_IOM_DRAM_SDQS0, 0x00000030,
  777. MX6_IOM_DRAM_SDQS1, 0x00000030,
  778. MX6_IOM_DRAM_SDQS2, 0x00000030,
  779. MX6_IOM_DRAM_SDQS3, 0x00000030,
  780. MX6_IOM_DRAM_SDQS4, 0x00000030,
  781. MX6_IOM_DRAM_SDQS5, 0x00000030,
  782. MX6_IOM_DRAM_SDQS6, 0x00000030,
  783. MX6_IOM_DRAM_SDQS7, 0x00000030,
  784. MX6_IOM_GRP_B0DS, 0x00000030,
  785. MX6_IOM_GRP_B1DS, 0x00000030,
  786. MX6_IOM_GRP_B2DS, 0x00000030,
  787. MX6_IOM_GRP_B3DS, 0x00000030,
  788. MX6_IOM_GRP_B4DS, 0x00000030,
  789. MX6_IOM_GRP_B5DS, 0x00000030,
  790. MX6_IOM_GRP_B6DS, 0x00000030,
  791. MX6_IOM_GRP_B7DS, 0x00000030,
  792. MX6_IOM_GRP_ADDDS, 0x00000030,
  793. /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
  794. MX6_IOM_GRP_CTLDS, 0x00000030,
  795. MX6_IOM_DRAM_DQM0, 0x00020030,
  796. MX6_IOM_DRAM_DQM1, 0x00020030,
  797. MX6_IOM_DRAM_DQM2, 0x00020030,
  798. MX6_IOM_DRAM_DQM3, 0x00020030,
  799. MX6_IOM_DRAM_DQM4, 0x00020030,
  800. MX6_IOM_DRAM_DQM5, 0x00020030,
  801. MX6_IOM_DRAM_DQM6, 0x00020030,
  802. MX6_IOM_DRAM_DQM7, 0x00020030,
  803. MX6_IOM_DRAM_CAS, 0x00020030,
  804. MX6_IOM_DRAM_RAS, 0x00020030,
  805. MX6_IOM_DRAM_SDCLK_0, 0x00020030,
  806. MX6_IOM_DRAM_SDCLK_1, 0x00020030,
  807. MX6_IOM_DRAM_RESET, 0x00020030,
  808. MX6_IOM_DRAM_SDCKE0, 0x00003000,
  809. MX6_IOM_DRAM_SDCKE1, 0x00003000,
  810. MX6_IOM_DRAM_SDODT0, 0x00003030,
  811. MX6_IOM_DRAM_SDODT1, 0x00003030,
  812. /* (differential input) */
  813. MX6_IOM_DDRMODE_CTL, 0x00020000,
  814. /* (differential input) */
  815. MX6_IOM_GRP_DDRMODE, 0x00020000,
  816. /* disable ddr pullups */
  817. MX6_IOM_GRP_DDRPKE, 0x00000000,
  818. MX6_IOM_DRAM_SDBA2, 0x00000000,
  819. /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
  820. MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
  821. /* Read data DQ Byte0-3 delay */
  822. MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
  823. MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
  824. MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
  825. MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
  826. MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
  827. MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
  828. MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
  829. MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
  830. /*
  831. * MDMISC mirroring interleaved (row/bank/col)
  832. */
  833. /* TODO: check what the RALAT field does */
  834. MX6_MMDC_P0_MDMISC, 0x00081740,
  835. /*
  836. * MDSCR con_req
  837. */
  838. MX6_MMDC_P0_MDSCR, 0x00008000,
  839. /* 800mhz_2x64mx16.cfg */
  840. MX6_MMDC_P0_MDPDC, 0x0002002D,
  841. MX6_MMDC_P0_MDCFG0, 0x2C305503,
  842. MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
  843. MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
  844. MX6_MMDC_P0_MDRWD, 0x000026D2,
  845. MX6_MMDC_P0_MDOR, 0x00301023,
  846. MX6_MMDC_P0_MDOTC, 0x00333030,
  847. MX6_MMDC_P0_MDPDC, 0x0002556D,
  848. /* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
  849. MX6_MMDC_P0_MDASP, 0x00000017,
  850. /* DDR3 DATA BUS SIZE: 64BIT */
  851. MX6_MMDC_P0_MDCTL, 0x821A0000,
  852. /* DDR3 DATA BUS SIZE: 32BIT */
  853. /* MX6_MMDC_P0_MDCTL, 0x82190000, */
  854. /* Write commands to DDR */
  855. /* Load Mode Registers */
  856. /* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
  857. /* MX6_MMDC_P0_MDSCR, 0x04408032, */
  858. MX6_MMDC_P0_MDSCR, 0x04008032,
  859. MX6_MMDC_P0_MDSCR, 0x00008033,
  860. MX6_MMDC_P0_MDSCR, 0x00048031,
  861. MX6_MMDC_P0_MDSCR, 0x13208030,
  862. /* ZQ calibration */
  863. MX6_MMDC_P0_MDSCR, 0x04008040,
  864. MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
  865. MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
  866. MX6_MMDC_P0_MDREF, 0x00005800,
  867. MX6_MMDC_P0_MPODTCTRL, 0x00000000,
  868. MX6_MMDC_P1_MPODTCTRL, 0x00000000,
  869. MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
  870. MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
  871. MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
  872. MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
  873. MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
  874. MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
  875. MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
  876. MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
  877. MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
  878. MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
  879. MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
  880. MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
  881. MX6_MMDC_P0_MPMUR0, 0x00000800,
  882. MX6_MMDC_P1_MPMUR0, 0x00000800,
  883. MX6_MMDC_P0_MDSCR, 0x00000000,
  884. MX6_MMDC_P0_MAPSR, 0x00011006,
  885. };
  886. static void ccgr_init(void)
  887. {
  888. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  889. writel(0x00C03F3F, &ccm->CCGR0);
  890. writel(0x0030FC03, &ccm->CCGR1);
  891. writel(0x0FFFFFF3, &ccm->CCGR2);
  892. writel(0x3FF0300F, &ccm->CCGR3);
  893. writel(0x00FFF300, &ccm->CCGR4);
  894. writel(0x0F0000F3, &ccm->CCGR5);
  895. writel(0x000003FF, &ccm->CCGR6);
  896. /*
  897. * Setup CCM_CCOSR register as follows:
  898. *
  899. * cko1_en = 1 --> CKO1 enabled
  900. * cko1_div = 111 --> divide by 8
  901. * cko1_sel = 1011 --> ahb_clk_root
  902. *
  903. * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
  904. */
  905. writel(0x000000FB, &ccm->ccosr);
  906. }
  907. static void ddr_init(int *table, int size)
  908. {
  909. int i;
  910. for (i = 0; i < size / 2 ; i++)
  911. writel(table[2 * i + 1], table[2 * i]);
  912. }
  913. static void spl_dram_init(void)
  914. {
  915. int minc, maxc;
  916. switch (get_cpu_temp_grade(&minc, &maxc)) {
  917. case TEMP_COMMERCIAL:
  918. case TEMP_EXTCOMMERCIAL:
  919. if (is_cpu_type(MXC_CPU_MX6DL)) {
  920. puts("Commercial temperature grade DDR3 timings, 64bit bus width.\n");
  921. ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
  922. } else {
  923. puts("Commercial temperature grade DDR3 timings, 32bit bus width.\n");
  924. ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
  925. }
  926. break;
  927. case TEMP_INDUSTRIAL:
  928. case TEMP_AUTOMOTIVE:
  929. default:
  930. if (is_cpu_type(MXC_CPU_MX6DL)) {
  931. puts("Industrial temperature grade DDR3 timings, 64bit bus width.\n");
  932. ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
  933. } else {
  934. puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n");
  935. ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
  936. }
  937. break;
  938. };
  939. udelay(100);
  940. }
  941. static iomux_v3_cfg_t const gpio_reset_pad[] = {
  942. MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL) |
  943. MUX_MODE_SION
  944. #define GPIO_NRESET IMX_GPIO_NR(6, 27)
  945. };
  946. #define IMX_RESET_CAUSE_POR 0x00011
  947. static void nreset_out(void)
  948. {
  949. int reset_cause = get_imx_reset_cause();
  950. if (reset_cause != IMX_RESET_CAUSE_POR) {
  951. imx_iomux_v3_setup_multiple_pads(gpio_reset_pad,
  952. ARRAY_SIZE(gpio_reset_pad));
  953. gpio_direction_output(GPIO_NRESET, 1);
  954. udelay(100);
  955. gpio_direction_output(GPIO_NRESET, 0);
  956. }
  957. }
  958. void board_init_f(ulong dummy)
  959. {
  960. /* setup AIPS and disable watchdog */
  961. arch_cpu_init();
  962. ccgr_init();
  963. gpr_init();
  964. /* iomux */
  965. board_early_init_f();
  966. /* setup GP timer */
  967. timer_init();
  968. /* UART clocks enabled and gd valid - init serial console */
  969. preloader_console_init();
  970. /* Make sure we use dte mode */
  971. setup_dtemode_uart();
  972. /* DDR initialization */
  973. spl_dram_init();
  974. /* Clear the BSS. */
  975. memset(__bss_start, 0, __bss_end - __bss_start);
  976. /* Assert nReset_Out */
  977. nreset_out();
  978. /* load/boot image from boot device */
  979. board_init_r(NULL, 0);
  980. }
  981. void reset_cpu(ulong addr)
  982. {
  983. }
  984. #endif /* CONFIG_SPL_BUILD */
  985. static struct mxc_serial_platdata mxc_serial_plat = {
  986. .reg = (struct mxc_uart *)UART1_BASE,
  987. .use_dte = true,
  988. };
  989. U_BOOT_DEVICE(mxc_serial) = {
  990. .name = "serial_mxc",
  991. .platdata = &mxc_serial_plat,
  992. };