sdram_s10.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
  4. *
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <dm.h>
  9. #include <errno.h>
  10. #include <div64.h>
  11. #include <fdtdec.h>
  12. #include <ram.h>
  13. #include <reset.h>
  14. #include "sdram_s10.h"
  15. #include <wait_bit.h>
  16. #include <asm/arch/firewall_s10.h>
  17. #include <asm/arch/system_manager.h>
  18. #include <asm/arch/reset_manager.h>
  19. #include <asm/io.h>
  20. #include <linux/sizes.h>
  21. struct altera_sdram_priv {
  22. struct ram_info info;
  23. struct reset_ctl_bulk resets;
  24. };
  25. struct altera_sdram_platdata {
  26. void __iomem *hmc;
  27. void __iomem *ddr_sch;
  28. void __iomem *iomhc;
  29. };
  30. DECLARE_GLOBAL_DATA_PTR;
  31. static const struct socfpga_system_manager *sysmgr_regs =
  32. (void *)SOCFPGA_SYSMGR_ADDRESS;
  33. #define DDR_CONFIG(A, B, C, R) (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
  34. #define PGTABLE_OFF 0x4000
  35. /* The followring are the supported configurations */
  36. u32 ddr_config[] = {
  37. /* DDR_CONFIG(Address order,Bank,Column,Row) */
  38. /* List for DDR3 or LPDDR3 (pinout order > chip, row, bank, column) */
  39. DDR_CONFIG(0, 3, 10, 12),
  40. DDR_CONFIG(0, 3, 9, 13),
  41. DDR_CONFIG(0, 3, 10, 13),
  42. DDR_CONFIG(0, 3, 9, 14),
  43. DDR_CONFIG(0, 3, 10, 14),
  44. DDR_CONFIG(0, 3, 10, 15),
  45. DDR_CONFIG(0, 3, 11, 14),
  46. DDR_CONFIG(0, 3, 11, 15),
  47. DDR_CONFIG(0, 3, 10, 16),
  48. DDR_CONFIG(0, 3, 11, 16),
  49. DDR_CONFIG(0, 3, 12, 15), /* 0xa */
  50. /* List for DDR4 only (pinout order > chip, bank, row, column) */
  51. DDR_CONFIG(1, 3, 10, 14),
  52. DDR_CONFIG(1, 4, 10, 14),
  53. DDR_CONFIG(1, 3, 10, 15),
  54. DDR_CONFIG(1, 4, 10, 15),
  55. DDR_CONFIG(1, 3, 10, 16),
  56. DDR_CONFIG(1, 4, 10, 16),
  57. DDR_CONFIG(1, 3, 10, 17),
  58. DDR_CONFIG(1, 4, 10, 17),
  59. };
  60. static u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg)
  61. {
  62. return readl(plat->iomhc + reg);
  63. }
  64. static u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg)
  65. {
  66. return readl(plat->hmc + reg);
  67. }
  68. static u32 hmc_ecc_writel(struct altera_sdram_platdata *plat,
  69. u32 data, u32 reg)
  70. {
  71. return writel(data, plat->hmc + reg);
  72. }
  73. static u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data,
  74. u32 reg)
  75. {
  76. return writel(data, plat->ddr_sch + reg);
  77. }
  78. int match_ddr_conf(u32 ddr_conf)
  79. {
  80. int i;
  81. for (i = 0; i < ARRAY_SIZE(ddr_config); i++) {
  82. if (ddr_conf == ddr_config[i])
  83. return i;
  84. }
  85. return 0;
  86. }
  87. static int emif_clear(struct altera_sdram_platdata *plat)
  88. {
  89. hmc_ecc_writel(plat, 0, RSTHANDSHAKECTRL);
  90. return wait_for_bit_le32((const void *)(plat->hmc +
  91. RSTHANDSHAKESTAT),
  92. DDR_HMC_RSTHANDSHAKE_MASK,
  93. false, 1000, false);
  94. }
  95. static int emif_reset(struct altera_sdram_platdata *plat)
  96. {
  97. u32 c2s, s2c, ret;
  98. c2s = hmc_ecc_readl(plat, RSTHANDSHAKECTRL) & DDR_HMC_RSTHANDSHAKE_MASK;
  99. s2c = hmc_ecc_readl(plat, RSTHANDSHAKESTAT) & DDR_HMC_RSTHANDSHAKE_MASK;
  100. debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
  101. c2s, s2c, hmc_readl(plat, NIOSRESERVED0),
  102. hmc_readl(plat, NIOSRESERVED1), hmc_readl(plat, NIOSRESERVED2),
  103. hmc_readl(plat, DRAMSTS));
  104. if (s2c && emif_clear(plat)) {
  105. printf("DDR: emif_clear() failed\n");
  106. return -1;
  107. }
  108. debug("DDR: Triggerring emif reset\n");
  109. hmc_ecc_writel(plat, DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL);
  110. /* if seq2core[3] = 0, we are good */
  111. ret = wait_for_bit_le32((const void *)(plat->hmc +
  112. RSTHANDSHAKESTAT),
  113. DDR_HMC_SEQ2CORE_INT_RESP_MASK,
  114. false, 1000, false);
  115. if (ret) {
  116. printf("DDR: failed to get ack from EMIF\n");
  117. return ret;
  118. }
  119. ret = emif_clear(plat);
  120. if (ret) {
  121. printf("DDR: emif_clear() failed\n");
  122. return ret;
  123. }
  124. debug("DDR: %s triggered successly\n", __func__);
  125. return 0;
  126. }
  127. static int poll_hmc_clock_status(void)
  128. {
  129. return wait_for_bit_le32(&sysmgr_regs->hmc_clk,
  130. SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false);
  131. }
  132. static void sdram_clear_mem(phys_addr_t addr, phys_size_t size)
  133. {
  134. phys_size_t i;
  135. if (addr % CONFIG_SYS_CACHELINE_SIZE) {
  136. printf("DDR: address 0x%llx is not cacheline size aligned.\n",
  137. addr);
  138. hang();
  139. }
  140. if (size % CONFIG_SYS_CACHELINE_SIZE) {
  141. printf("DDR: size 0x%llx is not multiple of cacheline size\n",
  142. size);
  143. hang();
  144. }
  145. /* Use DC ZVA instruction to clear memory to zeros by a cache line */
  146. for (i = 0; i < size; i = i + CONFIG_SYS_CACHELINE_SIZE) {
  147. asm volatile("dc zva, %0"
  148. :
  149. : "r"(addr)
  150. : "memory");
  151. addr += CONFIG_SYS_CACHELINE_SIZE;
  152. }
  153. }
  154. static void sdram_init_ecc_bits(bd_t *bd)
  155. {
  156. phys_size_t size, size_init;
  157. phys_addr_t start_addr;
  158. int bank = 0;
  159. unsigned int start = get_timer(0);
  160. icache_enable();
  161. start_addr = bd->bi_dram[0].start;
  162. size = bd->bi_dram[0].size;
  163. /* Initialize small block for page table */
  164. memset((void *)start_addr, 0, PGTABLE_SIZE + PGTABLE_OFF);
  165. gd->arch.tlb_addr = start_addr + PGTABLE_OFF;
  166. gd->arch.tlb_size = PGTABLE_SIZE;
  167. start_addr += PGTABLE_SIZE + PGTABLE_OFF;
  168. size -= (PGTABLE_OFF + PGTABLE_SIZE);
  169. dcache_enable();
  170. while (1) {
  171. while (size) {
  172. size_init = min((phys_addr_t)SZ_1G, (phys_addr_t)size);
  173. sdram_clear_mem(start_addr, size_init);
  174. size -= size_init;
  175. start_addr += size_init;
  176. WATCHDOG_RESET();
  177. }
  178. bank++;
  179. if (bank >= CONFIG_NR_DRAM_BANKS)
  180. break;
  181. start_addr = bd->bi_dram[bank].start;
  182. size = bd->bi_dram[bank].size;
  183. }
  184. dcache_disable();
  185. icache_disable();
  186. printf("SDRAM-ECC: Initialized success with %d ms\n",
  187. (unsigned int)get_timer(start));
  188. }
  189. static void sdram_size_check(bd_t *bd)
  190. {
  191. phys_size_t total_ram_check = 0;
  192. phys_size_t ram_check = 0;
  193. phys_addr_t start = 0;
  194. int bank;
  195. /* Sanity check ensure correct SDRAM size specified */
  196. debug("DDR: Running SDRAM size sanity check\n");
  197. for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
  198. start = bd->bi_dram[bank].start;
  199. while (ram_check < bd->bi_dram[bank].size) {
  200. ram_check += get_ram_size((void *)(start + ram_check),
  201. (phys_size_t)SZ_1G);
  202. }
  203. total_ram_check += ram_check;
  204. ram_check = 0;
  205. }
  206. /* If the ram_size is 2GB smaller, we can assume the IO space is
  207. * not mapped in. gd->ram_size is the actual size of the dram
  208. * not the accessible size.
  209. */
  210. if (total_ram_check != gd->ram_size) {
  211. puts("DDR: SDRAM size check failed!\n");
  212. hang();
  213. }
  214. debug("DDR: SDRAM size check passed!\n");
  215. }
  216. /**
  217. * sdram_calculate_size() - Calculate SDRAM size
  218. *
  219. * Calculate SDRAM device size based on SDRAM controller parameters.
  220. * Size is specified in bytes.
  221. */
  222. static phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat)
  223. {
  224. u32 dramaddrw = hmc_readl(plat, DRAMADDRW);
  225. phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
  226. DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) +
  227. DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
  228. DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +
  229. DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw));
  230. size *= (2 << (hmc_ecc_readl(plat, DDRIOCTRL) &
  231. DDR_HMC_DDRIOCTRL_IOSIZE_MSK));
  232. return size;
  233. }
  234. /**
  235. * sdram_mmr_init_full() - Function to initialize SDRAM MMR
  236. *
  237. * Initialize the SDRAM MMR.
  238. */
  239. static int sdram_mmr_init_full(struct udevice *dev)
  240. {
  241. struct altera_sdram_platdata *plat = dev->platdata;
  242. struct altera_sdram_priv *priv = dev_get_priv(dev);
  243. u32 update_value, io48_value, ddrioctl;
  244. u32 i;
  245. int ret;
  246. phys_size_t hw_size;
  247. bd_t bd = {0};
  248. /* Enable access to DDR from CPU master */
  249. clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_DDRREG),
  250. CCU_ADBASE_DI_MASK);
  251. clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE0),
  252. CCU_ADBASE_DI_MASK);
  253. clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1A),
  254. CCU_ADBASE_DI_MASK);
  255. clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1B),
  256. CCU_ADBASE_DI_MASK);
  257. clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1C),
  258. CCU_ADBASE_DI_MASK);
  259. clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1D),
  260. CCU_ADBASE_DI_MASK);
  261. clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1E),
  262. CCU_ADBASE_DI_MASK);
  263. /* Enable access to DDR from IO master */
  264. clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE0),
  265. CCU_ADBASE_DI_MASK);
  266. clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1A),
  267. CCU_ADBASE_DI_MASK);
  268. clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1B),
  269. CCU_ADBASE_DI_MASK);
  270. clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1C),
  271. CCU_ADBASE_DI_MASK);
  272. clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1D),
  273. CCU_ADBASE_DI_MASK);
  274. clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1E),
  275. CCU_ADBASE_DI_MASK);
  276. /* this enables nonsecure access to DDR */
  277. /* mpuregion0addr_limit */
  278. FW_MPU_DDR_SCR_WRITEL(0xFFFF0000, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT);
  279. FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT);
  280. /* nonmpuregion0addr_limit */
  281. FW_MPU_DDR_SCR_WRITEL(0xFFFF0000,
  282. FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT);
  283. FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT);
  284. /* Enable mpuregion0enable and nonmpuregion0enable */
  285. FW_MPU_DDR_SCR_WRITEL(MPUREGION0_ENABLE | NONMPUREGION0_ENABLE,
  286. FW_MPU_DDR_SCR_EN_SET);
  287. /* Ensure HMC clock is running */
  288. if (poll_hmc_clock_status()) {
  289. puts("DDR: Error as HMC clock not running\n");
  290. return -1;
  291. }
  292. /* Try 3 times to do a calibration */
  293. for (i = 0; i < 3; i++) {
  294. ret = wait_for_bit_le32((const void *)(plat->hmc +
  295. DDRCALSTAT),
  296. DDR_HMC_DDRCALSTAT_CAL_MSK, true, 1000,
  297. false);
  298. if (!ret)
  299. break;
  300. emif_reset(plat);
  301. }
  302. if (ret) {
  303. puts("DDR: Error as SDRAM calibration failed\n");
  304. return -1;
  305. }
  306. debug("DDR: Calibration success\n");
  307. u32 ctrlcfg0 = hmc_readl(plat, CTRLCFG0);
  308. u32 ctrlcfg1 = hmc_readl(plat, CTRLCFG1);
  309. u32 dramaddrw = hmc_readl(plat, DRAMADDRW);
  310. u32 dramtim0 = hmc_readl(plat, DRAMTIMING0);
  311. u32 caltim0 = hmc_readl(plat, CALTIMING0);
  312. u32 caltim1 = hmc_readl(plat, CALTIMING1);
  313. u32 caltim2 = hmc_readl(plat, CALTIMING2);
  314. u32 caltim3 = hmc_readl(plat, CALTIMING3);
  315. u32 caltim4 = hmc_readl(plat, CALTIMING4);
  316. u32 caltim9 = hmc_readl(plat, CALTIMING9);
  317. /*
  318. * Configure the DDR IO size [0xFFCFB008]
  319. * niosreserve0: Used to indicate DDR width &
  320. * bit[7:0] = Number of data bits (bit[6:5] 0x01=32bit, 0x10=64bit)
  321. * bit[8] = 1 if user-mode OCT is present
  322. * bit[9] = 1 if warm reset compiled into EMIF Cal Code
  323. * bit[10] = 1 if warm reset is on during generation in EMIF Cal
  324. * niosreserve1: IP ADCDS version encoded as 16 bit value
  325. * bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
  326. * 3=EAP, 4-6 are reserved)
  327. * bit[5:3] = Service Pack # (e.g. 1)
  328. * bit[9:6] = Minor Release #
  329. * bit[14:10] = Major Release #
  330. */
  331. update_value = hmc_readl(plat, NIOSRESERVED0);
  332. hmc_ecc_writel(plat, ((update_value & 0xFF) >> 5), DDRIOCTRL);
  333. ddrioctl = hmc_ecc_readl(plat, DDRIOCTRL);
  334. /* enable HPS interface to HMC */
  335. hmc_ecc_writel(plat, DDR_HMC_HPSINTFCSEL_ENABLE_MASK, HPSINTFCSEL);
  336. /* Set the DDR Configuration */
  337. io48_value = DDR_CONFIG(CTRLCFG1_CFG_ADDR_ORDER(ctrlcfg1),
  338. (DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
  339. DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw)),
  340. DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw),
  341. DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw));
  342. update_value = match_ddr_conf(io48_value);
  343. if (update_value)
  344. ddr_sch_writel(plat, update_value, DDR_SCH_DDRCONF);
  345. /* Configure HMC dramaddrw */
  346. hmc_ecc_writel(plat, hmc_readl(plat, DRAMADDRW), DRAMADDRWIDTH);
  347. /*
  348. * Configure DDR timing
  349. * RDTOMISS = tRTP + tRP + tRCD - BL/2
  350. * WRTOMISS = WL + tWR + tRP + tRCD and
  351. * WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns so...
  352. * First part of equation is in memory clock units so divide by 2
  353. * for HMC clock units. 1066MHz is close to 1ns so use 15 directly.
  354. * WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD
  355. */
  356. u32 burst_len = CTRLCFG0_CFG_CTRL_BURST_LEN(ctrlcfg0);
  357. update_value = CALTIMING2_CFG_RD_TO_WR_PCH(caltim2) +
  358. CALTIMING4_CFG_PCH_TO_VALID(caltim4) +
  359. CALTIMING0_CFG_ACT_TO_RDWR(caltim0) -
  360. (burst_len >> 2);
  361. io48_value = (((DRAMTIMING0_CFG_TCL(dramtim0) + 2 + DDR_TWR +
  362. (burst_len >> 1)) >> 1) -
  363. /* Up to here was in memory cycles so divide by 2 */
  364. CALTIMING1_CFG_RD_TO_WR(caltim1) +
  365. CALTIMING0_CFG_ACT_TO_RDWR(caltim0) +
  366. CALTIMING4_CFG_PCH_TO_VALID(caltim4));
  367. ddr_sch_writel(plat, ((CALTIMING0_CFG_ACT_TO_ACT(caltim0) <<
  368. DDR_SCH_DDRTIMING_ACTTOACT_OFF) |
  369. (update_value << DDR_SCH_DDRTIMING_RDTOMISS_OFF) |
  370. (io48_value << DDR_SCH_DDRTIMING_WRTOMISS_OFF) |
  371. ((burst_len >> 2) << DDR_SCH_DDRTIMING_BURSTLEN_OFF) |
  372. (CALTIMING1_CFG_RD_TO_WR(caltim1) <<
  373. DDR_SCH_DDRTIMING_RDTOWR_OFF) |
  374. (CALTIMING3_CFG_WR_TO_RD(caltim3) <<
  375. DDR_SCH_DDRTIMING_WRTORD_OFF) |
  376. (((ddrioctl == 1) ? 1 : 0) <<
  377. DDR_SCH_DDRTIMING_BWRATIO_OFF)),
  378. DDR_SCH_DDRTIMING);
  379. /* Configure DDR mode [precharge = 0] */
  380. ddr_sch_writel(plat, ((ddrioctl ? 0 : 1) <<
  381. DDR_SCH_DDRMOD_BWRATIOEXTENDED_OFF),
  382. DDR_SCH_DDRMODE);
  383. /* Configure the read latency */
  384. ddr_sch_writel(plat, (DRAMTIMING0_CFG_TCL(dramtim0) >> 1) +
  385. DDR_READ_LATENCY_DELAY,
  386. DDR_SCH_READ_LATENCY);
  387. /*
  388. * Configuring timing values concerning activate commands
  389. * [FAWBANK alway 1 because always 4 bank DDR]
  390. */
  391. ddr_sch_writel(plat, ((CALTIMING0_CFG_ACT_TO_ACT_DB(caltim0) <<
  392. DDR_SCH_ACTIVATE_RRD_OFF) |
  393. (CALTIMING9_CFG_4_ACT_TO_ACT(caltim9) <<
  394. DDR_SCH_ACTIVATE_FAW_OFF) |
  395. (DDR_ACTIVATE_FAWBANK <<
  396. DDR_SCH_ACTIVATE_FAWBANK_OFF)),
  397. DDR_SCH_ACTIVATE);
  398. /*
  399. * Configuring timing values concerning device to device data bus
  400. * ownership change
  401. */
  402. ddr_sch_writel(plat, ((CALTIMING1_CFG_RD_TO_RD_DC(caltim1) <<
  403. DDR_SCH_DEVTODEV_BUSRDTORD_OFF) |
  404. (CALTIMING1_CFG_RD_TO_WR_DC(caltim1) <<
  405. DDR_SCH_DEVTODEV_BUSRDTOWR_OFF) |
  406. (CALTIMING3_CFG_WR_TO_RD_DC(caltim3) <<
  407. DDR_SCH_DEVTODEV_BUSWRTORD_OFF)),
  408. DDR_SCH_DEVTODEV);
  409. /* assigning the SDRAM size */
  410. unsigned long long size = sdram_calculate_size(plat);
  411. /* If the size is invalid, use default Config size */
  412. if (size <= 0)
  413. hw_size = PHYS_SDRAM_1_SIZE;
  414. else
  415. hw_size = size;
  416. /* Get bank configuration from devicetree */
  417. ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL,
  418. (phys_size_t *)&gd->ram_size, &bd);
  419. if (ret) {
  420. puts("DDR: Failed to decode memory node\n");
  421. return -1;
  422. }
  423. if (gd->ram_size != hw_size)
  424. printf("DDR: Warning: DRAM size from device tree mismatch with hardware.\n");
  425. printf("DDR: %lld MiB\n", gd->ram_size >> 20);
  426. /* Enable or disable the SDRAM ECC */
  427. if (CTRLCFG1_CFG_CTRL_EN_ECC(ctrlcfg1)) {
  428. setbits_le32(plat->hmc + ECCCTRL1,
  429. (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
  430. DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
  431. DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
  432. clrbits_le32(plat->hmc + ECCCTRL1,
  433. (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
  434. DDR_HMC_ECCCTL_CNT_RST_SET_MSK));
  435. setbits_le32(plat->hmc + ECCCTRL2,
  436. (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
  437. DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
  438. hmc_ecc_writel(plat, DDR_HMC_ERRINTEN_INTMASK, ERRINTENS);
  439. /* Enable non-secure writes to HMC Adapter for SDRAM ECC */
  440. writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR);
  441. /* Initialize memory content if not from warm reset */
  442. if (!cpu_has_been_warmreset())
  443. sdram_init_ecc_bits(&bd);
  444. } else {
  445. clrbits_le32(plat->hmc + ECCCTRL1,
  446. (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
  447. DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
  448. DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
  449. clrbits_le32(plat->hmc + ECCCTRL2,
  450. (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
  451. DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
  452. }
  453. sdram_size_check(&bd);
  454. priv->info.base = bd.bi_dram[0].start;
  455. priv->info.size = gd->ram_size;
  456. debug("DDR: HMC init success\n");
  457. return 0;
  458. }
  459. static int altera_sdram_ofdata_to_platdata(struct udevice *dev)
  460. {
  461. struct altera_sdram_platdata *plat = dev->platdata;
  462. fdt_addr_t addr;
  463. addr = dev_read_addr_index(dev, 0);
  464. if (addr == FDT_ADDR_T_NONE)
  465. return -EINVAL;
  466. plat->ddr_sch = (void __iomem *)addr;
  467. addr = dev_read_addr_index(dev, 1);
  468. if (addr == FDT_ADDR_T_NONE)
  469. return -EINVAL;
  470. plat->iomhc = (void __iomem *)addr;
  471. addr = dev_read_addr_index(dev, 2);
  472. if (addr == FDT_ADDR_T_NONE)
  473. return -EINVAL;
  474. plat->hmc = (void __iomem *)addr;
  475. return 0;
  476. }
  477. static int altera_sdram_probe(struct udevice *dev)
  478. {
  479. int ret;
  480. struct altera_sdram_priv *priv = dev_get_priv(dev);
  481. ret = reset_get_bulk(dev, &priv->resets);
  482. if (ret) {
  483. dev_err(dev, "Can't get reset: %d\n", ret);
  484. return -ENODEV;
  485. }
  486. reset_deassert_bulk(&priv->resets);
  487. if (sdram_mmr_init_full(dev) != 0) {
  488. puts("SDRAM init failed.\n");
  489. goto failed;
  490. }
  491. return 0;
  492. failed:
  493. reset_release_bulk(&priv->resets);
  494. return -ENODEV;
  495. }
  496. static int altera_sdram_get_info(struct udevice *dev,
  497. struct ram_info *info)
  498. {
  499. struct altera_sdram_priv *priv = dev_get_priv(dev);
  500. info->base = priv->info.base;
  501. info->size = priv->info.size;
  502. return 0;
  503. }
  504. static struct ram_ops altera_sdram_ops = {
  505. .get_info = altera_sdram_get_info,
  506. };
  507. static const struct udevice_id altera_sdram_ids[] = {
  508. { .compatible = "altr,sdr-ctl-s10" },
  509. { /* sentinel */ }
  510. };
  511. U_BOOT_DRIVER(altera_sdram) = {
  512. .name = "altr_sdr_ctl",
  513. .id = UCLASS_RAM,
  514. .of_match = altera_sdram_ids,
  515. .ops = &altera_sdram_ops,
  516. .ofdata_to_platdata = altera_sdram_ofdata_to_platdata,
  517. .platdata_auto_alloc_size = sizeof(struct altera_sdram_platdata),
  518. .probe = altera_sdram_probe,
  519. .priv_auto_alloc_size = sizeof(struct altera_sdram_priv),
  520. };