sdram_arria10.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2017 Intel Corporation <www.intel.com>
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <errno.h>
  8. #include <fdtdec.h>
  9. #include <malloc.h>
  10. #include <wait_bit.h>
  11. #include <watchdog.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/fpga_manager.h>
  14. #include <asm/arch/misc.h>
  15. #include <asm/arch/reset_manager.h>
  16. #include <asm/arch/sdram.h>
  17. #include <linux/kernel.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. static void sdram_mmr_init(void);
  20. static u64 sdram_size_calc(void);
  21. /* FAWBANK - Number of Bank of a given device involved in the FAW period. */
  22. #define ARRIA10_SDR_ACTIVATE_FAWBANK (0x1)
  23. #define ARRIA_DDR_CONFIG(A, B, C, R) \
  24. (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
  25. #define DDR_CONFIG_ELEMENTS ARRAY_SIZE(ddr_config)
  26. #define DDR_REG_SEQ2CORE 0xFFD0507C
  27. #define DDR_REG_CORE2SEQ 0xFFD05078
  28. #define DDR_READ_LATENCY_DELAY 40
  29. #define DDR_SIZE_2GB_HEX 0x80000000
  30. #define IO48_MMR_DRAMSTS 0xFFCFA0EC
  31. #define IO48_MMR_NIOS2_RESERVE0 0xFFCFA110
  32. #define IO48_MMR_NIOS2_RESERVE1 0xFFCFA114
  33. #define IO48_MMR_NIOS2_RESERVE2 0xFFCFA118
  34. #define SEQ2CORE_MASK 0xF
  35. #define CORE2SEQ_INT_REQ 0xF
  36. #define SEQ2CORE_INT_RESP_BIT 3
  37. static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base =
  38. (void *)SOCFPGA_SDR_ADDRESS;
  39. static const struct socfpga_noc_ddr_scheduler *socfpga_noc_ddr_scheduler_base =
  40. (void *)SOCFPGA_SDR_SCHEDULER_ADDRESS;
  41. static const struct socfpga_noc_fw_ddr_mpu_fpga2sdram
  42. *socfpga_noc_fw_ddr_mpu_fpga2sdram_base =
  43. (void *)SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS;
  44. static const struct socfpga_noc_fw_ddr_l3 *socfpga_noc_fw_ddr_l3_base =
  45. (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
  46. static const struct socfpga_io48_mmr *socfpga_io48_mmr_base =
  47. (void *)SOCFPGA_HMC_MMR_IO48_ADDRESS;
  48. /* The following are the supported configurations */
  49. static u32 ddr_config[] = {
  50. /* Chip - Row - Bank - Column Style */
  51. /* All Types */
  52. ARRIA_DDR_CONFIG(0, 3, 10, 12),
  53. ARRIA_DDR_CONFIG(0, 3, 10, 13),
  54. ARRIA_DDR_CONFIG(0, 3, 10, 14),
  55. ARRIA_DDR_CONFIG(0, 3, 10, 15),
  56. ARRIA_DDR_CONFIG(0, 3, 10, 16),
  57. ARRIA_DDR_CONFIG(0, 3, 10, 17),
  58. /* LPDDR x16 */
  59. ARRIA_DDR_CONFIG(0, 3, 11, 14),
  60. ARRIA_DDR_CONFIG(0, 3, 11, 15),
  61. ARRIA_DDR_CONFIG(0, 3, 11, 16),
  62. ARRIA_DDR_CONFIG(0, 3, 12, 15),
  63. /* DDR4 Only */
  64. ARRIA_DDR_CONFIG(0, 4, 10, 14),
  65. ARRIA_DDR_CONFIG(0, 4, 10, 15),
  66. ARRIA_DDR_CONFIG(0, 4, 10, 16),
  67. ARRIA_DDR_CONFIG(0, 4, 10, 17), /* 14 */
  68. /* Chip - Bank - Row - Column Style */
  69. ARRIA_DDR_CONFIG(1, 3, 10, 12),
  70. ARRIA_DDR_CONFIG(1, 3, 10, 13),
  71. ARRIA_DDR_CONFIG(1, 3, 10, 14),
  72. ARRIA_DDR_CONFIG(1, 3, 10, 15),
  73. ARRIA_DDR_CONFIG(1, 3, 10, 16),
  74. ARRIA_DDR_CONFIG(1, 3, 10, 17),
  75. ARRIA_DDR_CONFIG(1, 3, 11, 14),
  76. ARRIA_DDR_CONFIG(1, 3, 11, 15),
  77. ARRIA_DDR_CONFIG(1, 3, 11, 16),
  78. ARRIA_DDR_CONFIG(1, 3, 12, 15),
  79. /* DDR4 Only */
  80. ARRIA_DDR_CONFIG(1, 4, 10, 14),
  81. ARRIA_DDR_CONFIG(1, 4, 10, 15),
  82. ARRIA_DDR_CONFIG(1, 4, 10, 16),
  83. ARRIA_DDR_CONFIG(1, 4, 10, 17),
  84. };
  85. static int match_ddr_conf(u32 ddr_conf)
  86. {
  87. int i;
  88. for (i = 0; i < DDR_CONFIG_ELEMENTS; i++) {
  89. if (ddr_conf == ddr_config[i])
  90. return i;
  91. }
  92. return 0;
  93. }
  94. static int emif_clear(void)
  95. {
  96. writel(0, DDR_REG_CORE2SEQ);
  97. return wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE,
  98. SEQ2CORE_MASK, 0, 1000, 0);
  99. }
  100. static int emif_reset(void)
  101. {
  102. u32 c2s, s2c;
  103. int ret;
  104. c2s = readl(DDR_REG_CORE2SEQ);
  105. s2c = readl(DDR_REG_SEQ2CORE);
  106. debug("c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
  107. c2s, s2c, readl(IO48_MMR_NIOS2_RESERVE0),
  108. readl(IO48_MMR_NIOS2_RESERVE1),
  109. readl(IO48_MMR_NIOS2_RESERVE2),
  110. readl(IO48_MMR_DRAMSTS));
  111. if (s2c & SEQ2CORE_MASK) {
  112. ret = emif_clear();
  113. if (ret) {
  114. debug("failed emif_clear()\n");
  115. return -EPERM;
  116. }
  117. }
  118. writel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ);
  119. ret = wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE,
  120. SEQ2CORE_INT_RESP_BIT, false, 1000, false);
  121. if (ret) {
  122. debug("emif_reset failed to see interrupt acknowledge\n");
  123. emif_clear();
  124. return ret;
  125. }
  126. mdelay(1);
  127. ret = emif_clear();
  128. if (ret) {
  129. debug("emif_clear() failed\n");
  130. return -EPERM;
  131. }
  132. debug("emif_reset interrupt cleared\n");
  133. debug("nr0=%08x nr1=%08x nr2=%08x\n",
  134. readl(IO48_MMR_NIOS2_RESERVE0),
  135. readl(IO48_MMR_NIOS2_RESERVE1),
  136. readl(IO48_MMR_NIOS2_RESERVE2));
  137. return 0;
  138. }
  139. static int ddr_setup(void)
  140. {
  141. int i, ret;
  142. /* Try 32 times to do a calibration */
  143. for (i = 0; i < 32; i++) {
  144. mdelay(500);
  145. ret = wait_for_bit_le32(&socfpga_ecc_hmc_base->ddrcalstat,
  146. BIT(0), true, 500, false);
  147. if (!ret)
  148. return 0;
  149. ret = emif_reset();
  150. if (ret)
  151. puts("Error: Failed to reset EMIF\n");
  152. }
  153. puts("Error: Could Not Calibrate SDRAM\n");
  154. return -EPERM;
  155. }
  156. static int sdram_is_ecc_enabled(void)
  157. {
  158. return !!(readl(&socfpga_ecc_hmc_base->eccctrl) &
  159. ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK);
  160. }
  161. /* Initialize SDRAM ECC bits to avoid false DBE */
  162. static void sdram_init_ecc_bits(u32 size)
  163. {
  164. icache_enable();
  165. memset(0, 0, 0x8000);
  166. gd->arch.tlb_addr = 0x4000;
  167. gd->arch.tlb_size = PGTABLE_SIZE;
  168. dcache_enable();
  169. printf("DDRCAL: Scrubbing ECC RAM (%i MiB).\n", size >> 20);
  170. memset((void *)0x8000, 0, size - 0x8000);
  171. flush_dcache_all();
  172. printf("DDRCAL: Scrubbing ECC RAM done.\n");
  173. dcache_disable();
  174. }
  175. /* Function to startup the SDRAM*/
  176. static int sdram_startup(void)
  177. {
  178. /* Release NOC ddr scheduler from reset */
  179. socfpga_reset_deassert_noc_ddr_scheduler();
  180. /* Bringup the DDR (calibration and configuration) */
  181. return ddr_setup();
  182. }
  183. static u64 sdram_size_calc(void)
  184. {
  185. u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw);
  186. u64 size = BIT(((dramaddrw &
  187. IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_MASK) >>
  188. IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_SHIFT) +
  189. ((dramaddrw &
  190. IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >>
  191. IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT) +
  192. ((dramaddrw &
  193. IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >>
  194. IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) +
  195. ((dramaddrw &
  196. IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >>
  197. IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT) +
  198. (dramaddrw & IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK));
  199. size *= (2 << (readl(&socfpga_ecc_hmc_base->ddrioctrl) &
  200. ALT_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE_MSK));
  201. debug("SDRAM size=%llu\n", size);
  202. return size;
  203. }
  204. /* Function to initialize SDRAM MMR and NOC DDR scheduler*/
  205. static void sdram_mmr_init(void)
  206. {
  207. u32 update_value, io48_value;
  208. u32 ctrlcfg0 = readl(&socfpga_io48_mmr_base->ctrlcfg0);
  209. u32 ctrlcfg1 = readl(&socfpga_io48_mmr_base->ctrlcfg1);
  210. u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw);
  211. u32 caltim0 = readl(&socfpga_io48_mmr_base->caltiming0);
  212. u32 caltim1 = readl(&socfpga_io48_mmr_base->caltiming1);
  213. u32 caltim2 = readl(&socfpga_io48_mmr_base->caltiming2);
  214. u32 caltim3 = readl(&socfpga_io48_mmr_base->caltiming3);
  215. u32 caltim4 = readl(&socfpga_io48_mmr_base->caltiming4);
  216. u32 caltim9 = readl(&socfpga_io48_mmr_base->caltiming9);
  217. u32 ddrioctl;
  218. /*
  219. * Configure the DDR IO size [0xFFCFB008]
  220. * niosreserve0: Used to indicate DDR width &
  221. * bit[7:0] = Number of data bits (0x20 for 32bit)
  222. * bit[8] = 1 if user-mode OCT is present
  223. * bit[9] = 1 if warm reset compiled into EMIF Cal Code
  224. * bit[10] = 1 if warm reset is on during generation in EMIF Cal
  225. * niosreserve1: IP ADCDS version encoded as 16 bit value
  226. * bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
  227. * 3=EAP, 4-6 are reserved)
  228. * bit[5:3] = Service Pack # (e.g. 1)
  229. * bit[9:6] = Minor Release #
  230. * bit[14:10] = Major Release #
  231. */
  232. if ((readl(&socfpga_io48_mmr_base->niosreserve1) >> 6) & 0x1FF) {
  233. update_value = readl(&socfpga_io48_mmr_base->niosreserve0);
  234. writel(((update_value & 0xFF) >> 5),
  235. &socfpga_ecc_hmc_base->ddrioctrl);
  236. }
  237. ddrioctl = readl(&socfpga_ecc_hmc_base->ddrioctrl);
  238. /* Set the DDR Configuration [0xFFD12400] */
  239. io48_value = ARRIA_DDR_CONFIG(
  240. ((ctrlcfg1 &
  241. IO48_MMR_CTRLCFG1_ADDR_ORDER_MASK) >>
  242. IO48_MMR_CTRLCFG1_ADDR_ORDER_SHIFT),
  243. ((dramaddrw &
  244. IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >>
  245. IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) +
  246. ((dramaddrw &
  247. IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >>
  248. IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT),
  249. (dramaddrw &
  250. IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK),
  251. ((dramaddrw &
  252. IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >>
  253. IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT));
  254. update_value = match_ddr_conf(io48_value);
  255. if (update_value)
  256. writel(update_value,
  257. &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrconf);
  258. /*
  259. * Configure DDR timing [0xFFD1240C]
  260. * RDTOMISS = tRTP + tRP + tRCD - BL/2
  261. * WRTOMISS = WL + tWR + tRP + tRCD and
  262. * WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns so...
  263. * First part of equation is in memory clock units so divide by 2
  264. * for HMC clock units. 1066MHz is close to 1ns so use 15 directly.
  265. * WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD
  266. */
  267. u32 ctrlcfg0_cfg_ctrl_burst_len =
  268. (ctrlcfg0 & IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_MASK) >>
  269. IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_SHIFT;
  270. u32 caltim0_cfg_act_to_rdwr = caltim0 &
  271. IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_MASK;
  272. u32 caltim0_cfg_act_to_act =
  273. (caltim0 & IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_MASK) >>
  274. IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_SHIFT;
  275. u32 caltim0_cfg_act_to_act_db =
  276. (caltim0 &
  277. IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_MASK) >>
  278. IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_SHIFT;
  279. u32 caltim1_cfg_rd_to_wr =
  280. (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_MASK) >>
  281. IO48_MMR_CALTIMING1_CFG_RD_TO_WR_SHIFT;
  282. u32 caltim1_cfg_rd_to_rd_dc =
  283. (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_MASK) >>
  284. IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_SHIFT;
  285. u32 caltim1_cfg_rd_to_wr_dc =
  286. (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_MASK) >>
  287. IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_SHIFT;
  288. u32 caltim2_cfg_rd_to_pch =
  289. (caltim2 & IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_MASK) >>
  290. IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_SHIFT;
  291. u32 caltim3_cfg_wr_to_rd =
  292. (caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_MASK) >>
  293. IO48_MMR_CALTIMING3_CFG_WR_TO_RD_SHIFT;
  294. u32 caltim3_cfg_wr_to_rd_dc =
  295. (caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_MASK) >>
  296. IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_SHIFT;
  297. u32 caltim4_cfg_pch_to_valid =
  298. (caltim4 & IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_MASK) >>
  299. IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_SHIFT;
  300. u32 caltim9_cfg_4_act_to_act = caltim9 &
  301. IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_MASK;
  302. update_value = (caltim2_cfg_rd_to_pch + caltim4_cfg_pch_to_valid +
  303. caltim0_cfg_act_to_rdwr -
  304. (ctrlcfg0_cfg_ctrl_burst_len >> 2));
  305. io48_value = ((((readl(&socfpga_io48_mmr_base->dramtiming0) &
  306. ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) + 2 + 15 +
  307. (ctrlcfg0_cfg_ctrl_burst_len >> 1)) >> 1) -
  308. /* Up to here was in memory cycles so divide by 2 */
  309. caltim1_cfg_rd_to_wr + caltim0_cfg_act_to_rdwr +
  310. caltim4_cfg_pch_to_valid);
  311. writel(((caltim0_cfg_act_to_act <<
  312. ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB) |
  313. (update_value <<
  314. ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB) |
  315. (io48_value <<
  316. ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB) |
  317. ((ctrlcfg0_cfg_ctrl_burst_len >> 2) <<
  318. ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB) |
  319. (caltim1_cfg_rd_to_wr <<
  320. ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB) |
  321. (caltim3_cfg_wr_to_rd <<
  322. ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB) |
  323. (((ddrioctl == 1) ? 1 : 0) <<
  324. ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB)),
  325. &socfpga_noc_ddr_scheduler_base->
  326. ddr_t_main_scheduler_ddrtiming);
  327. /* Configure DDR mode [0xFFD12410] [precharge = 0] */
  328. writel(((ddrioctl ? 0 : 1) <<
  329. ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB),
  330. &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrmode);
  331. /* Configure the read latency [0xFFD12414] */
  332. writel(((readl(&socfpga_io48_mmr_base->dramtiming0) &
  333. ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) >> 1) +
  334. DDR_READ_LATENCY_DELAY,
  335. &socfpga_noc_ddr_scheduler_base->
  336. ddr_t_main_scheduler_readlatency);
  337. /*
  338. * Configuring timing values concerning activate commands
  339. * [0xFFD12438] [FAWBANK alway 1 because always 4 bank DDR]
  340. */
  341. writel(((caltim0_cfg_act_to_act_db <<
  342. ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB) |
  343. (caltim9_cfg_4_act_to_act <<
  344. ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB) |
  345. (ARRIA10_SDR_ACTIVATE_FAWBANK <<
  346. ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB)),
  347. &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_activate);
  348. /*
  349. * Configuring timing values concerning device to device data bus
  350. * ownership change [0xFFD1243C]
  351. */
  352. writel(((caltim1_cfg_rd_to_rd_dc <<
  353. ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB) |
  354. (caltim1_cfg_rd_to_wr_dc <<
  355. ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB) |
  356. (caltim3_cfg_wr_to_rd_dc <<
  357. ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB)),
  358. &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_devtodev);
  359. /* Enable or disable the SDRAM ECC */
  360. if (ctrlcfg1 & IO48_MMR_CTRLCFG1_CTRL_ENABLE_ECC) {
  361. setbits_le32(&socfpga_ecc_hmc_base->eccctrl,
  362. (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
  363. ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK |
  364. ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));
  365. clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
  366. (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
  367. ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK));
  368. setbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
  369. (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |
  370. ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));
  371. } else {
  372. clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
  373. (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
  374. ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK |
  375. ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));
  376. clrbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
  377. (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |
  378. ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));
  379. }
  380. }
  381. struct firewall_entry {
  382. const char *prop_name;
  383. const u32 cfg_addr;
  384. const u32 en_addr;
  385. const u32 en_bit;
  386. };
  387. #define FW_MPU_FPGA_ADDRESS \
  388. ((const struct socfpga_noc_fw_ddr_mpu_fpga2sdram *)\
  389. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS)
  390. #define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(ADDR) \
  391. (SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS + \
  392. offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram, ADDR))
  393. #define SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(ADDR) \
  394. (SOCFPGA_SDR_FIREWALL_L3_ADDRESS + \
  395. offsetof(struct socfpga_noc_fw_ddr_l3, ADDR))
  396. const struct firewall_entry firewall_table[] = {
  397. {
  398. "mpu0",
  399. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion0addr),
  400. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
  401. ALT_NOC_FW_DDR_SCR_EN_MPUREG0EN_SET_MSK
  402. },
  403. {
  404. "mpu1",
  405. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
  406. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion1addr),
  407. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
  408. ALT_NOC_FW_DDR_SCR_EN_MPUREG1EN_SET_MSK
  409. },
  410. {
  411. "mpu2",
  412. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion2addr),
  413. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
  414. ALT_NOC_FW_DDR_SCR_EN_MPUREG2EN_SET_MSK
  415. },
  416. {
  417. "mpu3",
  418. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion3addr),
  419. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
  420. ALT_NOC_FW_DDR_SCR_EN_MPUREG3EN_SET_MSK
  421. },
  422. {
  423. "l3-0",
  424. SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion0addr),
  425. SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
  426. ALT_NOC_FW_DDR_SCR_EN_HPSREG0EN_SET_MSK
  427. },
  428. {
  429. "l3-1",
  430. SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion1addr),
  431. SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
  432. ALT_NOC_FW_DDR_SCR_EN_HPSREG1EN_SET_MSK
  433. },
  434. {
  435. "l3-2",
  436. SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion2addr),
  437. SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
  438. ALT_NOC_FW_DDR_SCR_EN_HPSREG2EN_SET_MSK
  439. },
  440. {
  441. "l3-3",
  442. SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion3addr),
  443. SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
  444. ALT_NOC_FW_DDR_SCR_EN_HPSREG3EN_SET_MSK
  445. },
  446. {
  447. "l3-4",
  448. SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion4addr),
  449. SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
  450. ALT_NOC_FW_DDR_SCR_EN_HPSREG4EN_SET_MSK
  451. },
  452. {
  453. "l3-5",
  454. SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion5addr),
  455. SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
  456. ALT_NOC_FW_DDR_SCR_EN_HPSREG5EN_SET_MSK
  457. },
  458. {
  459. "l3-6",
  460. SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion6addr),
  461. SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
  462. ALT_NOC_FW_DDR_SCR_EN_HPSREG6EN_SET_MSK
  463. },
  464. {
  465. "l3-7",
  466. SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion7addr),
  467. SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
  468. ALT_NOC_FW_DDR_SCR_EN_HPSREG7EN_SET_MSK
  469. },
  470. {
  471. "fpga2sdram0-0",
  472. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
  473. (fpga2sdram0region0addr),
  474. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
  475. ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG0EN_SET_MSK
  476. },
  477. {
  478. "fpga2sdram0-1",
  479. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
  480. (fpga2sdram0region1addr),
  481. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
  482. ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG1EN_SET_MSK
  483. },
  484. {
  485. "fpga2sdram0-2",
  486. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
  487. (fpga2sdram0region2addr),
  488. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
  489. ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG2EN_SET_MSK
  490. },
  491. {
  492. "fpga2sdram0-3",
  493. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
  494. (fpga2sdram0region3addr),
  495. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
  496. ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG3EN_SET_MSK
  497. },
  498. {
  499. "fpga2sdram1-0",
  500. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
  501. (fpga2sdram1region0addr),
  502. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
  503. ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG0EN_SET_MSK
  504. },
  505. {
  506. "fpga2sdram1-1",
  507. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
  508. (fpga2sdram1region1addr),
  509. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
  510. ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG1EN_SET_MSK
  511. },
  512. {
  513. "fpga2sdram1-2",
  514. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
  515. (fpga2sdram1region2addr),
  516. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
  517. ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG2EN_SET_MSK
  518. },
  519. {
  520. "fpga2sdram1-3",
  521. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
  522. (fpga2sdram1region3addr),
  523. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
  524. ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG3EN_SET_MSK
  525. },
  526. {
  527. "fpga2sdram2-0",
  528. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
  529. (fpga2sdram2region0addr),
  530. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
  531. ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG0EN_SET_MSK
  532. },
  533. {
  534. "fpga2sdram2-1",
  535. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
  536. (fpga2sdram2region1addr),
  537. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
  538. ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG1EN_SET_MSK
  539. },
  540. {
  541. "fpga2sdram2-2",
  542. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
  543. (fpga2sdram2region2addr),
  544. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
  545. ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG2EN_SET_MSK
  546. },
  547. {
  548. "fpga2sdram2-3",
  549. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
  550. (fpga2sdram2region3addr),
  551. SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
  552. ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG3EN_SET_MSK
  553. },
  554. };
  555. static int of_sdram_firewall_setup(const void *blob)
  556. {
  557. int child, i, node, ret;
  558. u32 start_end[2];
  559. char name[32];
  560. node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_NOC);
  561. if (node < 0)
  562. return -ENXIO;
  563. child = fdt_first_subnode(blob, node);
  564. if (child < 0)
  565. return -ENXIO;
  566. /* set to default state */
  567. writel(0, &socfpga_noc_fw_ddr_mpu_fpga2sdram_base->enable);
  568. writel(0, &socfpga_noc_fw_ddr_l3_base->enable);
  569. for (i = 0; i < ARRAY_SIZE(firewall_table); i++) {
  570. sprintf(name, "%s", firewall_table[i].prop_name);
  571. ret = fdtdec_get_int_array(blob, child, name,
  572. start_end, 2);
  573. if (ret) {
  574. sprintf(name, "altr,%s", firewall_table[i].prop_name);
  575. ret = fdtdec_get_int_array(blob, child, name,
  576. start_end, 2);
  577. if (ret)
  578. continue;
  579. }
  580. writel((start_end[0] & ALT_NOC_FW_DDR_ADDR_MASK) |
  581. (start_end[1] << ALT_NOC_FW_DDR_END_ADDR_LSB),
  582. firewall_table[i].cfg_addr);
  583. setbits_le32(firewall_table[i].en_addr,
  584. firewall_table[i].en_bit);
  585. }
  586. return 0;
  587. }
  588. int ddr_calibration_sequence(void)
  589. {
  590. WATCHDOG_RESET();
  591. /* Check to see if SDRAM cal was success */
  592. if (sdram_startup()) {
  593. puts("DDRCAL: Failed\n");
  594. return -EPERM;
  595. }
  596. puts("DDRCAL: Success\n");
  597. WATCHDOG_RESET();
  598. /* initialize the MMR register */
  599. sdram_mmr_init();
  600. /* assigning the SDRAM size */
  601. u64 size = sdram_size_calc();
  602. /*
  603. * If size is less than zero, this is invalid/weird value from
  604. * calculation, use default Config size.
  605. * Up to 2GB is supported, 2GB would be used if more than that.
  606. */
  607. if (size <= 0)
  608. gd->ram_size = PHYS_SDRAM_1_SIZE;
  609. else if (DDR_SIZE_2GB_HEX <= size)
  610. gd->ram_size = DDR_SIZE_2GB_HEX;
  611. else
  612. gd->ram_size = (u32)size;
  613. /* setup the dram info within bd */
  614. dram_init_banksize();
  615. if (of_sdram_firewall_setup(gd->fdt_blob))
  616. puts("FW: Error Configuring Firewall\n");
  617. if (sdram_is_ecc_enabled())
  618. sdram_init_ecc_bits(gd->ram_size);
  619. return 0;
  620. }