edb93xx.c 6.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Board initialization for EP93xx
  4. *
  5. * Copyright (C) 2013
  6. * Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
  7. *
  8. * Copyright (C) 2009
  9. * Matthias Kaehlcke <matthias <at> kaehlcke.net>
  10. *
  11. * (C) Copyright 2002 2003
  12. * Network Audio Technologies, Inc. <www.netaudiotech.com>
  13. * Adam Bezanson <bezanson <at> netaudiotech.com>
  14. */
  15. #include <config.h>
  16. #include <common.h>
  17. #include <cpu_func.h>
  18. #include <netdev.h>
  19. #include <status_led.h>
  20. #include <asm/io.h>
  21. #include <asm/mach-types.h>
  22. #include <asm/arch/ep93xx.h>
  23. DECLARE_GLOBAL_DATA_PTR;
  24. /*
  25. * usb_div: 4, nbyp2: 1, pll2_en: 1
  26. * pll2_x1: 368640000.000000, pll2_x2ip: 15360000.000000,
  27. * pll2_x2: 384000000.000000, pll2_out: 192000000.000000
  28. */
  29. #define CLKSET2_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \
  30. 24 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
  31. 24 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
  32. 1 << SYSCON_CLKSET_PLL_PS_SHIFT | \
  33. SYSCON_CLKSET2_PLL2_EN | \
  34. SYSCON_CLKSET2_NBYP2 | \
  35. 3 << SYSCON_CLKSET2_USB_DIV_SHIFT)
  36. #define SMC_BCR6_VALUE (2 << SMC_BCR_IDCY_SHIFT | 5 << SMC_BCR_WST1_SHIFT | \
  37. SMC_BCR_BLE | 2 << SMC_BCR_WST2_SHIFT | \
  38. 1 << SMC_BCR_MW_SHIFT)
  39. /* delay execution before timers are initialized */
  40. static inline void early_udelay(uint32_t usecs)
  41. {
  42. /* loop takes 4 cycles at 5.0ns (fastest case, running at 200MHz) */
  43. register uint32_t loops = (usecs * 1000) / 20;
  44. __asm__ volatile ("1:\n"
  45. "subs %0, %1, #1\n"
  46. "bne 1b" : "=r" (loops) : "0" (loops));
  47. }
  48. #ifndef CONFIG_EP93XX_NO_FLASH_CFG
  49. static void flash_cfg(void)
  50. {
  51. struct smc_regs *smc = (struct smc_regs *)SMC_BASE;
  52. writel(SMC_BCR6_VALUE, &smc->bcr6);
  53. }
  54. #else
  55. #define flash_cfg()
  56. #endif
  57. int board_init(void)
  58. {
  59. /*
  60. * Setup PLL2, PPL1 has been set during lowlevel init
  61. */
  62. struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
  63. writel(CLKSET2_VAL, &syscon->clkset2);
  64. /*
  65. * the user's guide recommends to wait at least 1 ms for PLL2 to
  66. * stabilize
  67. */
  68. early_udelay(1000);
  69. /* Go to Async mode */
  70. __asm__ volatile ("mrc p15, 0, r0, c1, c0, 0");
  71. __asm__ volatile ("orr r0, r0, #0xc0000000");
  72. __asm__ volatile ("mcr p15, 0, r0, c1, c0, 0");
  73. icache_enable();
  74. #ifdef USE_920T_MMU
  75. dcache_enable();
  76. #endif
  77. /* Machine number, as defined in linux/arch/arm/tools/mach-types */
  78. gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
  79. /* adress of boot parameters */
  80. gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
  81. /* We have a console */
  82. gd->have_console = 1;
  83. enable_interrupts();
  84. flash_cfg();
  85. green_led_on();
  86. red_led_off();
  87. return 0;
  88. }
  89. int board_early_init_f(void)
  90. {
  91. /*
  92. * set UARTBAUD bit to drive UARTs with 14.7456MHz instead of
  93. * 14.7456/2 MHz
  94. */
  95. struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
  96. writel(SYSCON_PWRCNT_UART_BAUD, &syscon->pwrcnt);
  97. return 0;
  98. }
  99. int board_eth_init(bd_t *bd)
  100. {
  101. return ep93xx_eth_initialize(0, MAC_BASE);
  102. }
  103. static void dram_fill_bank_addr(unsigned dram_addr_mask, unsigned dram_bank_cnt,
  104. unsigned dram_bank_base[CONFIG_NR_DRAM_BANKS])
  105. {
  106. if (dram_bank_cnt == 1) {
  107. dram_bank_base[0] = PHYS_SDRAM_1;
  108. } else {
  109. /* Table lookup for holes in address space. Maximum memory
  110. * for the single SDCS may be up to 256Mb. We start scanning
  111. * banks from 1Mb, so it could be up to 128 banks theoretically.
  112. * We need at maximum 7 bits for the loockup, 8 slots is
  113. * enough for the worst case.
  114. */
  115. unsigned tbl[8];
  116. unsigned i = dram_bank_cnt / 2;
  117. unsigned j = 0x00100000; /* 1 Mb */
  118. unsigned *ptbl = tbl;
  119. do {
  120. while (!(dram_addr_mask & j)) {
  121. j <<= 1;
  122. }
  123. *ptbl++ = j;
  124. j <<= 1;
  125. i >>= 1;
  126. } while (i != 0);
  127. for (i = dram_bank_cnt, j = 0;
  128. (i != 0) && (j < CONFIG_NR_DRAM_BANKS); --i, ++j) {
  129. unsigned addr = PHYS_SDRAM_1;
  130. unsigned k;
  131. unsigned bit;
  132. for (k = 0, bit = 1; k < 8; k++, bit <<= 1) {
  133. if (bit & j)
  134. addr |= tbl[k];
  135. }
  136. dram_bank_base[j] = addr;
  137. }
  138. }
  139. }
  140. /* called in board_init_f (before relocation) */
  141. static unsigned dram_init_banksize_int(int print)
  142. {
  143. /*
  144. * Collect information of banks that has been filled during lowlevel
  145. * initialization
  146. */
  147. unsigned i;
  148. unsigned dram_bank_base[CONFIG_NR_DRAM_BANKS];
  149. unsigned dram_total = 0;
  150. unsigned dram_bank_size = *(unsigned *)
  151. (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_SIZE);
  152. unsigned dram_addr_mask = *(unsigned *)
  153. (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_MASK);
  154. unsigned dram_bank_cnt = *(unsigned *)
  155. (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_COUNT);
  156. dram_fill_bank_addr(dram_addr_mask, dram_bank_cnt, dram_bank_base);
  157. for (i = 0; i < dram_bank_cnt; i++) {
  158. gd->bd->bi_dram[i].start = dram_bank_base[i];
  159. gd->bd->bi_dram[i].size = dram_bank_size;
  160. dram_total += dram_bank_size;
  161. }
  162. for (; i < CONFIG_NR_DRAM_BANKS; i++) {
  163. gd->bd->bi_dram[i].start = 0;
  164. gd->bd->bi_dram[i].size = 0;
  165. }
  166. if (print) {
  167. printf("DRAM mask: %08x\n", dram_addr_mask);
  168. printf("DRAM total %u banks:\n", dram_bank_cnt);
  169. printf("bank base-address size\n");
  170. if (dram_bank_cnt > CONFIG_NR_DRAM_BANKS) {
  171. printf("WARNING! UBoot was configured for %u banks,\n"
  172. "but %u has been found. "
  173. "Supressing extra memory banks\n",
  174. CONFIG_NR_DRAM_BANKS, dram_bank_cnt);
  175. dram_bank_cnt = CONFIG_NR_DRAM_BANKS;
  176. }
  177. for (i = 0; i < dram_bank_cnt; i++) {
  178. printf(" %u %08x %08x\n",
  179. i, dram_bank_base[i], dram_bank_size);
  180. }
  181. printf(" ------------------------------------------\n"
  182. "Total %9d\n\n",
  183. dram_total);
  184. }
  185. return dram_total;
  186. }
  187. int dram_init_banksize(void)
  188. {
  189. dram_init_banksize_int(0);
  190. return 0;
  191. }
  192. /* called in board_init_f (before relocation) */
  193. int dram_init(void)
  194. {
  195. struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
  196. unsigned sec_id = readl(SECURITY_EXTENSIONID);
  197. unsigned chip_id = readl(&syscon->chipid);
  198. printf("CPU: Cirrus Logic ");
  199. switch (sec_id & 0x000001FE) {
  200. case 0x00000008:
  201. printf("EP9301");
  202. break;
  203. case 0x00000004:
  204. printf("EP9307");
  205. break;
  206. case 0x00000002:
  207. printf("EP931x");
  208. break;
  209. case 0x00000000:
  210. printf("EP9315");
  211. break;
  212. default:
  213. printf("<unknown>");
  214. break;
  215. }
  216. printf(" - Rev. ");
  217. switch (chip_id & 0xF0000000) {
  218. case 0x00000000:
  219. printf("A");
  220. break;
  221. case 0x10000000:
  222. printf("B");
  223. break;
  224. case 0x20000000:
  225. printf("C");
  226. break;
  227. case 0x30000000:
  228. printf("D0");
  229. break;
  230. case 0x40000000:
  231. printf("D1");
  232. break;
  233. case 0x50000000:
  234. printf("E0");
  235. break;
  236. case 0x60000000:
  237. printf("E1");
  238. break;
  239. case 0x70000000:
  240. printf("E2");
  241. break;
  242. default:
  243. printf("?");
  244. break;
  245. }
  246. printf(" (SecExtID=%.8x/ChipID=%.8x)\n", sec_id, chip_id);
  247. gd->ram_size = dram_init_banksize_int(1);
  248. return 0;
  249. }