integrator.c 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  5. * Marius Groeger <mgroeger@sysgo.de>
  6. *
  7. * (C) Copyright 2002
  8. * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
  9. *
  10. * (C) Copyright 2003
  11. * Texas Instruments, <www.ti.com>
  12. * Kshitij Gupta <Kshitij@ti.com>
  13. *
  14. * (C) Copyright 2004
  15. * ARM Ltd.
  16. * Philippe Robin, <philippe.robin@arm.com>
  17. */
  18. #include <common.h>
  19. #include <cpu_func.h>
  20. #include <dm.h>
  21. #include <env.h>
  22. #include <netdev.h>
  23. #include <asm/io.h>
  24. #include <dm/platform_data/serial_pl01x.h>
  25. #include "arm-ebi.h"
  26. #include "integrator-sc.h"
  27. #include <asm/mach-types.h>
  28. DECLARE_GLOBAL_DATA_PTR;
  29. static const struct pl01x_serial_platdata serial_platdata = {
  30. .base = 0x16000000,
  31. #ifdef CONFIG_ARCH_CINTEGRATOR
  32. .type = TYPE_PL011,
  33. .clock = 14745600,
  34. #else
  35. .type = TYPE_PL010,
  36. .clock = 0, /* Not used for PL010 */
  37. #endif
  38. };
  39. U_BOOT_DEVICE(integrator_serials) = {
  40. .name = "serial_pl01x",
  41. .platdata = &serial_platdata,
  42. };
  43. void peripheral_power_enable (void);
  44. #if defined(CONFIG_SHOW_BOOT_PROGRESS)
  45. void show_boot_progress(int progress)
  46. {
  47. printf("Boot reached stage %d\n", progress);
  48. }
  49. #endif
  50. #define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
  51. /*
  52. * Miscellaneous platform dependent initialisations
  53. */
  54. int board_init (void)
  55. {
  56. u32 val;
  57. /* arch number of Integrator Board */
  58. #ifdef CONFIG_ARCH_CINTEGRATOR
  59. gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR;
  60. #else
  61. gd->bd->bi_arch_number = MACH_TYPE_INTEGRATOR;
  62. #endif
  63. /* adress of boot parameters */
  64. gd->bd->bi_boot_params = 0x00000100;
  65. #ifdef CONFIG_CM_REMAP
  66. extern void cm_remap(void);
  67. cm_remap(); /* remaps writeable memory to 0x00000000 */
  68. #endif
  69. #ifdef CONFIG_ARCH_CINTEGRATOR
  70. /*
  71. * Flash protection on the Integrator/CP is in a simple register
  72. */
  73. val = readl(CP_FLASHPROG);
  74. val |= (CP_FLASHPROG_FLVPPEN | CP_FLASHPROG_FLWREN);
  75. writel(val, CP_FLASHPROG);
  76. #else
  77. /*
  78. * The Integrator/AP has some special protection mechanisms
  79. * for the external memories, first the External Bus Interface (EBI)
  80. * then the system controller (SC).
  81. *
  82. * The system comes up with the flash memory non-writable and
  83. * configuration locked. If we want U-Boot to be used for flash
  84. * access we cannot have the flash memory locked.
  85. */
  86. writel(EBI_UNLOCK_MAGIC, EBI_BASE + EBI_LOCK_REG);
  87. val = readl(EBI_BASE + EBI_CSR1_REG);
  88. val &= EBI_CSR_WREN_MASK;
  89. val |= EBI_CSR_WREN_ENABLE;
  90. writel(val, EBI_BASE + EBI_CSR1_REG);
  91. writel(0, EBI_BASE + EBI_LOCK_REG);
  92. /*
  93. * Set up the system controller to remove write protection from
  94. * the flash memory and enable Vpp
  95. */
  96. writel(SC_CTRL_FLASHVPP | SC_CTRL_FLASHWP, SC_CTRLS);
  97. #endif
  98. icache_enable();
  99. return 0;
  100. }
  101. int misc_init_r (void)
  102. {
  103. env_set("verify", "n");
  104. return (0);
  105. }
  106. /*
  107. * The Integrator remaps the Flash memory to 0x00000000 and executes U-Boot
  108. * from there, which means we cannot test the RAM underneath the ROM at this
  109. * point. It will be unmapped later on, when we are executing from the
  110. * relocated in RAM U-Boot. We simply assume that this RAM is usable if the
  111. * RAM on higher addresses works fine.
  112. */
  113. #define REMAPPED_FLASH_SZ 0x40000
  114. int dram_init (void)
  115. {
  116. gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  117. #ifdef CONFIG_CM_SPD_DETECT
  118. {
  119. extern void dram_query(void);
  120. u32 cm_reg_sdram;
  121. u32 sdram_shift;
  122. dram_query(); /* Assembler accesses to CM registers */
  123. /* Queries the SPD values */
  124. /* Obtain the SDRAM size from the CM SDRAM register */
  125. cm_reg_sdram = readl(CM_BASE + OS_SDRAM);
  126. /* Register SDRAM size
  127. *
  128. * 0xXXXXXXbbb000bb 16 MB
  129. * 0xXXXXXXbbb001bb 32 MB
  130. * 0xXXXXXXbbb010bb 64 MB
  131. * 0xXXXXXXbbb011bb 128 MB
  132. * 0xXXXXXXbbb100bb 256 MB
  133. *
  134. */
  135. sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
  136. gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
  137. REMAPPED_FLASH_SZ,
  138. 0x01000000 << sdram_shift);
  139. }
  140. #else
  141. gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
  142. REMAPPED_FLASH_SZ,
  143. PHYS_SDRAM_1_SIZE);
  144. #endif /* CM_SPD_DETECT */
  145. /* We only have one bank of RAM, set it to whatever was detected */
  146. gd->bd->bi_dram[0].size = gd->ram_size;
  147. return 0;
  148. }
  149. #ifdef CONFIG_CMD_NET
  150. int board_eth_init(bd_t *bis)
  151. {
  152. int rc = 0;
  153. #ifdef CONFIG_SMC91111
  154. rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
  155. #endif
  156. rc += pci_eth_init(bis);
  157. return rc;
  158. }
  159. #endif