cache.c 1.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2008 - 2013 Tensilica Inc.
  4. * (C) Copyright 2014 - 2016 Cadence Design Systems Inc.
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <asm/cache.h>
  9. /*
  10. * We currently run always with caches enabled when running from memory.
  11. * Xtensa version D or later will support changing cache behavior, so
  12. * we could implement it if necessary.
  13. */
  14. int dcache_status(void)
  15. {
  16. return 1;
  17. }
  18. void dcache_enable(void)
  19. {
  20. }
  21. void dcache_disable(void)
  22. {
  23. }
  24. void flush_cache(ulong start_addr, ulong size)
  25. {
  26. __flush_invalidate_dcache_range(start_addr, size);
  27. __invalidate_icache_range(start_addr, size);
  28. }
  29. void flush_dcache_all(void)
  30. {
  31. __flush_dcache_all();
  32. __invalidate_icache_all();
  33. }
  34. void flush_dcache_range(ulong start_addr, ulong end_addr)
  35. {
  36. __flush_invalidate_dcache_range(start_addr, end_addr - start_addr);
  37. }
  38. void invalidate_dcache_range(ulong start, ulong stop)
  39. {
  40. __invalidate_dcache_range(start, stop - start);
  41. }
  42. void invalidate_dcache_all(void)
  43. {
  44. __invalidate_dcache_all();
  45. }
  46. void invalidate_icache_all(void)
  47. {
  48. __invalidate_icache_all();
  49. }