mtrr.c 3.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2014 Google, Inc
  4. *
  5. * Memory Type Range Regsters - these are used to tell the CPU whether
  6. * memory is cacheable and if so the cache write mode to use.
  7. *
  8. * These can speed up booting. See the mtrr command.
  9. *
  10. * Reference: Intel Architecture Software Developer's Manual, Volume 3:
  11. * System Programming
  12. */
  13. /*
  14. * Note that any console output (e.g. debug()) in this file will likely fail
  15. * since the MTRR registers are sometimes in flux.
  16. */
  17. #include <common.h>
  18. #include <cpu_func.h>
  19. #include <asm/io.h>
  20. #include <asm/msr.h>
  21. #include <asm/mtrr.h>
  22. DECLARE_GLOBAL_DATA_PTR;
  23. /* Prepare to adjust MTRRs */
  24. void mtrr_open(struct mtrr_state *state, bool do_caches)
  25. {
  26. if (!gd->arch.has_mtrr)
  27. return;
  28. if (do_caches) {
  29. state->enable_cache = dcache_status();
  30. if (state->enable_cache)
  31. disable_caches();
  32. }
  33. state->deftype = native_read_msr(MTRR_DEF_TYPE_MSR);
  34. wrmsrl(MTRR_DEF_TYPE_MSR, state->deftype & ~MTRR_DEF_TYPE_EN);
  35. }
  36. /* Clean up after adjusting MTRRs, and enable them */
  37. void mtrr_close(struct mtrr_state *state, bool do_caches)
  38. {
  39. if (!gd->arch.has_mtrr)
  40. return;
  41. wrmsrl(MTRR_DEF_TYPE_MSR, state->deftype | MTRR_DEF_TYPE_EN);
  42. if (do_caches && state->enable_cache)
  43. enable_caches();
  44. }
  45. static void set_var_mtrr(uint reg, uint type, uint64_t start, uint64_t size)
  46. {
  47. u64 mask;
  48. wrmsrl(MTRR_PHYS_BASE_MSR(reg), start | type);
  49. mask = ~(size - 1);
  50. mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1;
  51. wrmsrl(MTRR_PHYS_MASK_MSR(reg), mask | MTRR_PHYS_MASK_VALID);
  52. }
  53. int mtrr_commit(bool do_caches)
  54. {
  55. struct mtrr_request *req = gd->arch.mtrr_req;
  56. struct mtrr_state state;
  57. int i;
  58. debug("%s: enabled=%d, count=%d\n", __func__, gd->arch.has_mtrr,
  59. gd->arch.mtrr_req_count);
  60. if (!gd->arch.has_mtrr)
  61. return -ENOSYS;
  62. debug("open\n");
  63. mtrr_open(&state, do_caches);
  64. debug("open done\n");
  65. for (i = 0; i < gd->arch.mtrr_req_count; i++, req++)
  66. set_var_mtrr(i, req->type, req->start, req->size);
  67. /* Clear the ones that are unused */
  68. debug("clear\n");
  69. for (; i < MTRR_COUNT; i++)
  70. wrmsrl(MTRR_PHYS_MASK_MSR(i), 0);
  71. debug("close\n");
  72. mtrr_close(&state, do_caches);
  73. debug("mtrr done\n");
  74. return 0;
  75. }
  76. int mtrr_add_request(int type, uint64_t start, uint64_t size)
  77. {
  78. struct mtrr_request *req;
  79. uint64_t mask;
  80. debug("%s: count=%d\n", __func__, gd->arch.mtrr_req_count);
  81. if (!gd->arch.has_mtrr)
  82. return -ENOSYS;
  83. if (gd->arch.mtrr_req_count == MAX_MTRR_REQUESTS)
  84. return -ENOSPC;
  85. req = &gd->arch.mtrr_req[gd->arch.mtrr_req_count++];
  86. req->type = type;
  87. req->start = start;
  88. req->size = size;
  89. debug("%d: type=%d, %08llx %08llx\n", gd->arch.mtrr_req_count - 1,
  90. req->type, req->start, req->size);
  91. mask = ~(req->size - 1);
  92. mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1;
  93. mask |= MTRR_PHYS_MASK_VALID;
  94. debug(" %016llx %016llx\n", req->start | req->type, mask);
  95. return 0;
  96. }
  97. static int get_var_mtrr_count(void)
  98. {
  99. return msr_read(MSR_MTRR_CAP_MSR).lo & MSR_MTRR_CAP_VCNT;
  100. }
  101. static int get_free_var_mtrr(void)
  102. {
  103. struct msr_t maskm;
  104. int vcnt;
  105. int i;
  106. vcnt = get_var_mtrr_count();
  107. /* Identify the first var mtrr which is not valid */
  108. for (i = 0; i < vcnt; i++) {
  109. maskm = msr_read(MTRR_PHYS_MASK_MSR(i));
  110. if ((maskm.lo & MTRR_PHYS_MASK_VALID) == 0)
  111. return i;
  112. }
  113. /* No free var mtrr */
  114. return -ENOSPC;
  115. }
  116. int mtrr_set_next_var(uint type, uint64_t start, uint64_t size)
  117. {
  118. int mtrr;
  119. mtrr = get_free_var_mtrr();
  120. if (mtrr < 0)
  121. return mtrr;
  122. set_var_mtrr(mtrr, type, start, size);
  123. debug("MTRR %x: start=%x, size=%x\n", mtrr, (uint)start, (uint)size);
  124. return 0;
  125. }