cpu.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2008-2011
  4. * Graeme Russ, <graeme.russ@gmail.com>
  5. *
  6. * (C) Copyright 2002
  7. * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
  8. *
  9. * (C) Copyright 2002
  10. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  11. * Marius Groeger <mgroeger@sysgo.de>
  12. *
  13. * (C) Copyright 2002
  14. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  15. * Alex Zuepke <azu@sysgo.de>
  16. *
  17. * Part of this file is adapted from coreboot
  18. * src/arch/x86/lib/cpu.c
  19. */
  20. #include <common.h>
  21. #include <cpu_func.h>
  22. #include <malloc.h>
  23. #include <asm/control_regs.h>
  24. #include <asm/cpu.h>
  25. #include <asm/mp.h>
  26. #include <asm/msr.h>
  27. #include <asm/mtrr.h>
  28. #include <asm/processor-flags.h>
  29. DECLARE_GLOBAL_DATA_PTR;
  30. /*
  31. * Constructor for a conventional segment GDT (or LDT) entry
  32. * This is a macro so it can be used in initialisers
  33. */
  34. #define GDT_ENTRY(flags, base, limit) \
  35. ((((base) & 0xff000000ULL) << (56-24)) | \
  36. (((flags) & 0x0000f0ffULL) << 40) | \
  37. (((limit) & 0x000f0000ULL) << (48-16)) | \
  38. (((base) & 0x00ffffffULL) << 16) | \
  39. (((limit) & 0x0000ffffULL)))
  40. struct gdt_ptr {
  41. u16 len;
  42. u32 ptr;
  43. } __packed;
  44. struct cpu_device_id {
  45. unsigned vendor;
  46. unsigned device;
  47. };
  48. struct cpuinfo_x86 {
  49. uint8_t x86; /* CPU family */
  50. uint8_t x86_vendor; /* CPU vendor */
  51. uint8_t x86_model;
  52. uint8_t x86_mask;
  53. };
  54. /*
  55. * List of cpu vendor strings along with their normalized
  56. * id values.
  57. */
  58. static const struct {
  59. int vendor;
  60. const char *name;
  61. } x86_vendors[] = {
  62. { X86_VENDOR_INTEL, "GenuineIntel", },
  63. { X86_VENDOR_CYRIX, "CyrixInstead", },
  64. { X86_VENDOR_AMD, "AuthenticAMD", },
  65. { X86_VENDOR_UMC, "UMC UMC UMC ", },
  66. { X86_VENDOR_NEXGEN, "NexGenDriven", },
  67. { X86_VENDOR_CENTAUR, "CentaurHauls", },
  68. { X86_VENDOR_RISE, "RiseRiseRise", },
  69. { X86_VENDOR_TRANSMETA, "GenuineTMx86", },
  70. { X86_VENDOR_TRANSMETA, "TransmetaCPU", },
  71. { X86_VENDOR_NSC, "Geode by NSC", },
  72. { X86_VENDOR_SIS, "SiS SiS SiS ", },
  73. };
  74. static void load_ds(u32 segment)
  75. {
  76. asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE));
  77. }
  78. static void load_es(u32 segment)
  79. {
  80. asm volatile("movl %0, %%es" : : "r" (segment * X86_GDT_ENTRY_SIZE));
  81. }
  82. static void load_fs(u32 segment)
  83. {
  84. asm volatile("movl %0, %%fs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
  85. }
  86. static void load_gs(u32 segment)
  87. {
  88. asm volatile("movl %0, %%gs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
  89. }
  90. static void load_ss(u32 segment)
  91. {
  92. asm volatile("movl %0, %%ss" : : "r" (segment * X86_GDT_ENTRY_SIZE));
  93. }
  94. static void load_gdt(const u64 *boot_gdt, u16 num_entries)
  95. {
  96. struct gdt_ptr gdt;
  97. gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1;
  98. gdt.ptr = (ulong)boot_gdt;
  99. asm volatile("lgdtl %0\n" : : "m" (gdt));
  100. }
  101. void arch_setup_gd(gd_t *new_gd)
  102. {
  103. u64 *gdt_addr;
  104. gdt_addr = new_gd->arch.gdt;
  105. /*
  106. * CS: code, read/execute, 4 GB, base 0
  107. *
  108. * Some OS (like VxWorks) requires GDT entry 1 to be the 32-bit CS
  109. */
  110. gdt_addr[X86_GDT_ENTRY_UNUSED] = GDT_ENTRY(0xc09b, 0, 0xfffff);
  111. gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff);
  112. /* DS: data, read/write, 4 GB, base 0 */
  113. gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff);
  114. /* FS: data, read/write, 4 GB, base (Global Data Pointer) */
  115. new_gd->arch.gd_addr = new_gd;
  116. gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093,
  117. (ulong)&new_gd->arch.gd_addr, 0xfffff);
  118. /* 16-bit CS: code, read/execute, 64 kB, base 0 */
  119. gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff);
  120. /* 16-bit DS: data, read/write, 64 kB, base 0 */
  121. gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x0093, 0, 0x0ffff);
  122. gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_CS] = GDT_ENTRY(0x809b, 0, 0xfffff);
  123. gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_DS] = GDT_ENTRY(0x8093, 0, 0xfffff);
  124. load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES);
  125. load_ds(X86_GDT_ENTRY_32BIT_DS);
  126. load_es(X86_GDT_ENTRY_32BIT_DS);
  127. load_gs(X86_GDT_ENTRY_32BIT_DS);
  128. load_ss(X86_GDT_ENTRY_32BIT_DS);
  129. load_fs(X86_GDT_ENTRY_32BIT_FS);
  130. }
  131. #ifdef CONFIG_HAVE_FSP
  132. /*
  133. * Setup FSP execution environment GDT
  134. *
  135. * Per Intel FSP external architecture specification, before calling any FSP
  136. * APIs, we need make sure the system is in flat 32-bit mode and both the code
  137. * and data selectors should have full 4GB access range. Here we reuse the one
  138. * we used in arch/x86/cpu/start16.S, and reload the segement registers.
  139. */
  140. void setup_fsp_gdt(void)
  141. {
  142. load_gdt((const u64 *)(gdt_rom + CONFIG_RESET_SEG_START), 4);
  143. load_ds(X86_GDT_ENTRY_32BIT_DS);
  144. load_ss(X86_GDT_ENTRY_32BIT_DS);
  145. load_es(X86_GDT_ENTRY_32BIT_DS);
  146. load_fs(X86_GDT_ENTRY_32BIT_DS);
  147. load_gs(X86_GDT_ENTRY_32BIT_DS);
  148. }
  149. #endif
  150. /*
  151. * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected
  152. * by the fact that they preserve the flags across the division of 5/2.
  153. * PII and PPro exhibit this behavior too, but they have cpuid available.
  154. */
  155. /*
  156. * Perform the Cyrix 5/2 test. A Cyrix won't change
  157. * the flags, while other 486 chips will.
  158. */
  159. static inline int test_cyrix_52div(void)
  160. {
  161. unsigned int test;
  162. __asm__ __volatile__(
  163. "sahf\n\t" /* clear flags (%eax = 0x0005) */
  164. "div %b2\n\t" /* divide 5 by 2 */
  165. "lahf" /* store flags into %ah */
  166. : "=a" (test)
  167. : "0" (5), "q" (2)
  168. : "cc");
  169. /* AH is 0x02 on Cyrix after the divide.. */
  170. return (unsigned char) (test >> 8) == 0x02;
  171. }
  172. /*
  173. * Detect a NexGen CPU running without BIOS hypercode new enough
  174. * to have CPUID. (Thanks to Herbert Oppmann)
  175. */
  176. static int deep_magic_nexgen_probe(void)
  177. {
  178. int ret;
  179. __asm__ __volatile__ (
  180. " movw $0x5555, %%ax\n"
  181. " xorw %%dx,%%dx\n"
  182. " movw $2, %%cx\n"
  183. " divw %%cx\n"
  184. " movl $0, %%eax\n"
  185. " jnz 1f\n"
  186. " movl $1, %%eax\n"
  187. "1:\n"
  188. : "=a" (ret) : : "cx", "dx");
  189. return ret;
  190. }
  191. static bool has_cpuid(void)
  192. {
  193. return flag_is_changeable_p(X86_EFLAGS_ID);
  194. }
  195. static bool has_mtrr(void)
  196. {
  197. return cpuid_edx(0x00000001) & (1 << 12) ? true : false;
  198. }
  199. static int build_vendor_name(char *vendor_name)
  200. {
  201. struct cpuid_result result;
  202. result = cpuid(0x00000000);
  203. unsigned int *name_as_ints = (unsigned int *)vendor_name;
  204. name_as_ints[0] = result.ebx;
  205. name_as_ints[1] = result.edx;
  206. name_as_ints[2] = result.ecx;
  207. return result.eax;
  208. }
  209. static void identify_cpu(struct cpu_device_id *cpu)
  210. {
  211. char vendor_name[16];
  212. int i;
  213. vendor_name[0] = '\0'; /* Unset */
  214. cpu->device = 0; /* fix gcc 4.4.4 warning */
  215. /* Find the id and vendor_name */
  216. if (!has_cpuid()) {
  217. /* Its a 486 if we can modify the AC flag */
  218. if (flag_is_changeable_p(X86_EFLAGS_AC))
  219. cpu->device = 0x00000400; /* 486 */
  220. else
  221. cpu->device = 0x00000300; /* 386 */
  222. if ((cpu->device == 0x00000400) && test_cyrix_52div()) {
  223. memcpy(vendor_name, "CyrixInstead", 13);
  224. /* If we ever care we can enable cpuid here */
  225. }
  226. /* Detect NexGen with old hypercode */
  227. else if (deep_magic_nexgen_probe())
  228. memcpy(vendor_name, "NexGenDriven", 13);
  229. }
  230. if (has_cpuid()) {
  231. int cpuid_level;
  232. cpuid_level = build_vendor_name(vendor_name);
  233. vendor_name[12] = '\0';
  234. /* Intel-defined flags: level 0x00000001 */
  235. if (cpuid_level >= 0x00000001) {
  236. cpu->device = cpuid_eax(0x00000001);
  237. } else {
  238. /* Have CPUID level 0 only unheard of */
  239. cpu->device = 0x00000400;
  240. }
  241. }
  242. cpu->vendor = X86_VENDOR_UNKNOWN;
  243. for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) {
  244. if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) {
  245. cpu->vendor = x86_vendors[i].vendor;
  246. break;
  247. }
  248. }
  249. }
  250. static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms)
  251. {
  252. c->x86 = (tfms >> 8) & 0xf;
  253. c->x86_model = (tfms >> 4) & 0xf;
  254. c->x86_mask = tfms & 0xf;
  255. if (c->x86 == 0xf)
  256. c->x86 += (tfms >> 20) & 0xff;
  257. if (c->x86 >= 0x6)
  258. c->x86_model += ((tfms >> 16) & 0xF) << 4;
  259. }
  260. u32 cpu_get_family_model(void)
  261. {
  262. return gd->arch.x86_device & 0x0fff0ff0;
  263. }
  264. u32 cpu_get_stepping(void)
  265. {
  266. return gd->arch.x86_mask;
  267. }
  268. /* initialise FPU, reset EM, set MP and NE */
  269. static void setup_cpu_features(void)
  270. {
  271. const u32 em_rst = ~X86_CR0_EM;
  272. const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE;
  273. asm ("fninit\n" \
  274. "movl %%cr0, %%eax\n" \
  275. "andl %0, %%eax\n" \
  276. "orl %1, %%eax\n" \
  277. "movl %%eax, %%cr0\n" \
  278. : : "i" (em_rst), "i" (mp_ne_set) : "eax");
  279. }
  280. static void setup_identity(void)
  281. {
  282. /* identify CPU via cpuid and store the decoded info into gd->arch */
  283. if (has_cpuid()) {
  284. struct cpu_device_id cpu;
  285. struct cpuinfo_x86 c;
  286. identify_cpu(&cpu);
  287. get_fms(&c, cpu.device);
  288. gd->arch.x86 = c.x86;
  289. gd->arch.x86_vendor = cpu.vendor;
  290. gd->arch.x86_model = c.x86_model;
  291. gd->arch.x86_mask = c.x86_mask;
  292. gd->arch.x86_device = cpu.device;
  293. gd->arch.has_mtrr = has_mtrr();
  294. }
  295. }
  296. /* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */
  297. static void setup_pci_ram_top(void)
  298. {
  299. gd->pci_ram_top = 0x80000000U;
  300. }
  301. static void setup_mtrr(void)
  302. {
  303. u64 mtrr_cap;
  304. /* Configure fixed range MTRRs for some legacy regions */
  305. if (!gd->arch.has_mtrr)
  306. return;
  307. mtrr_cap = native_read_msr(MTRR_CAP_MSR);
  308. if (mtrr_cap & MTRR_CAP_FIX) {
  309. /* Mark the VGA RAM area as uncacheable */
  310. native_write_msr(MTRR_FIX_16K_A0000_MSR,
  311. MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE),
  312. MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE));
  313. /*
  314. * Mark the PCI ROM area as cacheable to improve ROM
  315. * execution performance.
  316. */
  317. native_write_msr(MTRR_FIX_4K_C0000_MSR,
  318. MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
  319. MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
  320. native_write_msr(MTRR_FIX_4K_C8000_MSR,
  321. MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
  322. MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
  323. native_write_msr(MTRR_FIX_4K_D0000_MSR,
  324. MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
  325. MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
  326. native_write_msr(MTRR_FIX_4K_D8000_MSR,
  327. MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
  328. MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
  329. /* Enable the fixed range MTRRs */
  330. msr_setbits_64(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_FIX_EN);
  331. }
  332. }
  333. int x86_cpu_init_tpl(void)
  334. {
  335. setup_cpu_features();
  336. setup_identity();
  337. return 0;
  338. }
  339. int x86_cpu_init_f(void)
  340. {
  341. if (ll_boot_init())
  342. setup_cpu_features();
  343. setup_identity();
  344. setup_mtrr();
  345. setup_pci_ram_top();
  346. /* Set up the i8254 timer if required */
  347. if (IS_ENABLED(CONFIG_I8254_TIMER))
  348. i8254_init();
  349. return 0;
  350. }
  351. int x86_cpu_reinit_f(void)
  352. {
  353. setup_identity();
  354. setup_pci_ram_top();
  355. return 0;
  356. }
  357. void x86_enable_caches(void)
  358. {
  359. unsigned long cr0;
  360. cr0 = read_cr0();
  361. cr0 &= ~(X86_CR0_NW | X86_CR0_CD);
  362. write_cr0(cr0);
  363. wbinvd();
  364. }
  365. void enable_caches(void) __attribute__((weak, alias("x86_enable_caches")));
  366. void x86_disable_caches(void)
  367. {
  368. unsigned long cr0;
  369. cr0 = read_cr0();
  370. cr0 |= X86_CR0_NW | X86_CR0_CD;
  371. wbinvd();
  372. write_cr0(cr0);
  373. wbinvd();
  374. }
  375. void disable_caches(void) __attribute__((weak, alias("x86_disable_caches")));
  376. int dcache_status(void)
  377. {
  378. return !(read_cr0() & X86_CR0_CD);
  379. }
  380. void cpu_enable_paging_pae(ulong cr3)
  381. {
  382. __asm__ __volatile__(
  383. /* Load the page table address */
  384. "movl %0, %%cr3\n"
  385. /* Enable pae */
  386. "movl %%cr4, %%eax\n"
  387. "orl $0x00000020, %%eax\n"
  388. "movl %%eax, %%cr4\n"
  389. /* Enable paging */
  390. "movl %%cr0, %%eax\n"
  391. "orl $0x80000000, %%eax\n"
  392. "movl %%eax, %%cr0\n"
  393. :
  394. : "r" (cr3)
  395. : "eax");
  396. }
  397. void cpu_disable_paging_pae(void)
  398. {
  399. /* Turn off paging */
  400. __asm__ __volatile__ (
  401. /* Disable paging */
  402. "movl %%cr0, %%eax\n"
  403. "andl $0x7fffffff, %%eax\n"
  404. "movl %%eax, %%cr0\n"
  405. /* Disable pae */
  406. "movl %%cr4, %%eax\n"
  407. "andl $0xffffffdf, %%eax\n"
  408. "movl %%eax, %%cr4\n"
  409. :
  410. :
  411. : "eax");
  412. }
  413. static bool can_detect_long_mode(void)
  414. {
  415. return cpuid_eax(0x80000000) > 0x80000000UL;
  416. }
  417. static bool has_long_mode(void)
  418. {
  419. return cpuid_edx(0x80000001) & (1 << 29) ? true : false;
  420. }
  421. int cpu_has_64bit(void)
  422. {
  423. return has_cpuid() && can_detect_long_mode() &&
  424. has_long_mode();
  425. }
  426. #define PAGETABLE_BASE 0x80000
  427. #define PAGETABLE_SIZE (6 * 4096)
  428. /**
  429. * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode
  430. *
  431. * @pgtable: Pointer to a 24iKB block of memory
  432. */
  433. static void build_pagetable(uint32_t *pgtable)
  434. {
  435. uint i;
  436. memset(pgtable, '\0', PAGETABLE_SIZE);
  437. /* Level 4 needs a single entry */
  438. pgtable[0] = (ulong)&pgtable[1024] + 7;
  439. /* Level 3 has one 64-bit entry for each GiB of memory */
  440. for (i = 0; i < 4; i++)
  441. pgtable[1024 + i * 2] = (ulong)&pgtable[2048] + 0x1000 * i + 7;
  442. /* Level 2 has 2048 64-bit entries, each repesenting 2MiB */
  443. for (i = 0; i < 2048; i++)
  444. pgtable[2048 + i * 2] = 0x183 + (i << 21UL);
  445. }
  446. int cpu_jump_to_64bit(ulong setup_base, ulong target)
  447. {
  448. uint32_t *pgtable;
  449. pgtable = memalign(4096, PAGETABLE_SIZE);
  450. if (!pgtable)
  451. return -ENOMEM;
  452. build_pagetable(pgtable);
  453. cpu_call64((ulong)pgtable, setup_base, target);
  454. free(pgtable);
  455. return -EFAULT;
  456. }
  457. /*
  458. * Jump from SPL to U-Boot
  459. *
  460. * This function is work-in-progress with many issues to resolve.
  461. *
  462. * It works by setting up several regions:
  463. * ptr - a place to put the code that jumps into 64-bit mode
  464. * gdt - a place to put the global descriptor table
  465. * pgtable - a place to put the page tables
  466. *
  467. * The cpu_call64() code is copied from ROM and then manually patched so that
  468. * it has the correct GDT address in RAM. U-Boot is copied from ROM into
  469. * its pre-relocation address. Then we jump to the cpu_call64() code in RAM,
  470. * which changes to 64-bit mode and starts U-Boot.
  471. */
  472. int cpu_jump_to_64bit_uboot(ulong target)
  473. {
  474. typedef void (*func_t)(ulong pgtable, ulong setup_base, ulong target);
  475. uint32_t *pgtable;
  476. func_t func;
  477. char *ptr;
  478. pgtable = (uint32_t *)PAGETABLE_BASE;
  479. build_pagetable(pgtable);
  480. extern long call64_stub_size;
  481. ptr = malloc(call64_stub_size);
  482. if (!ptr) {
  483. printf("Failed to allocate the cpu_call64 stub\n");
  484. return -ENOMEM;
  485. }
  486. memcpy(ptr, cpu_call64, call64_stub_size);
  487. func = (func_t)ptr;
  488. /*
  489. * Copy U-Boot from ROM
  490. * TODO(sjg@chromium.org): Figure out a way to get the text base
  491. * correctly here, and in the device-tree binman definition.
  492. *
  493. * Also consider using FIT so we get the correct image length and
  494. * parameters.
  495. */
  496. memcpy((char *)target, (char *)0xfff00000, 0x100000);
  497. /* Jump to U-Boot */
  498. func((ulong)pgtable, 0, (ulong)target);
  499. return -EFAULT;
  500. }
  501. #ifdef CONFIG_SMP
  502. static int enable_smis(struct udevice *cpu, void *unused)
  503. {
  504. return 0;
  505. }
  506. static struct mp_flight_record mp_steps[] = {
  507. MP_FR_BLOCK_APS(mp_init_cpu, NULL, mp_init_cpu, NULL),
  508. /* Wait for APs to finish initialization before proceeding */
  509. MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL),
  510. };
  511. int x86_mp_init(void)
  512. {
  513. struct mp_params mp_params;
  514. mp_params.parallel_microcode_load = 0,
  515. mp_params.flight_plan = &mp_steps[0];
  516. mp_params.num_records = ARRAY_SIZE(mp_steps);
  517. mp_params.microcode_pointer = 0;
  518. if (mp_init(&mp_params)) {
  519. printf("Warning: MP init failure\n");
  520. return -EIO;
  521. }
  522. return 0;
  523. }
  524. #endif