cpu.c 5.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2008-2011
  4. * Graeme Russ, <graeme.russ@gmail.com>
  5. *
  6. * (C) Copyright 2002
  7. * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
  8. *
  9. * (C) Copyright 2002
  10. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  11. * Marius Groeger <mgroeger@sysgo.de>
  12. *
  13. * (C) Copyright 2002
  14. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  15. * Alex Zuepke <azu@sysgo.de>
  16. *
  17. * Part of this file is adapted from coreboot
  18. * src/arch/x86/lib/cpu.c
  19. */
  20. #include <common.h>
  21. #include <acpi_s3.h>
  22. #include <command.h>
  23. #include <cpu_func.h>
  24. #include <dm.h>
  25. #include <errno.h>
  26. #include <malloc.h>
  27. #include <syscon.h>
  28. #include <asm/acpi.h>
  29. #include <asm/acpi_table.h>
  30. #include <asm/control_regs.h>
  31. #include <asm/coreboot_tables.h>
  32. #include <asm/cpu.h>
  33. #include <asm/lapic.h>
  34. #include <asm/microcode.h>
  35. #include <asm/mp.h>
  36. #include <asm/mrccache.h>
  37. #include <asm/msr.h>
  38. #include <asm/mtrr.h>
  39. #include <asm/post.h>
  40. #include <asm/processor.h>
  41. #include <asm/processor-flags.h>
  42. #include <asm/interrupt.h>
  43. #include <asm/tables.h>
  44. #include <linux/compiler.h>
  45. DECLARE_GLOBAL_DATA_PTR;
  46. static const char *const x86_vendor_name[] = {
  47. [X86_VENDOR_INTEL] = "Intel",
  48. [X86_VENDOR_CYRIX] = "Cyrix",
  49. [X86_VENDOR_AMD] = "AMD",
  50. [X86_VENDOR_UMC] = "UMC",
  51. [X86_VENDOR_NEXGEN] = "NexGen",
  52. [X86_VENDOR_CENTAUR] = "Centaur",
  53. [X86_VENDOR_RISE] = "Rise",
  54. [X86_VENDOR_TRANSMETA] = "Transmeta",
  55. [X86_VENDOR_NSC] = "NSC",
  56. [X86_VENDOR_SIS] = "SiS",
  57. };
  58. int __weak x86_cleanup_before_linux(void)
  59. {
  60. #ifdef CONFIG_BOOTSTAGE_STASH
  61. bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR,
  62. CONFIG_BOOTSTAGE_STASH_SIZE);
  63. #endif
  64. return 0;
  65. }
  66. int x86_init_cache(void)
  67. {
  68. enable_caches();
  69. return 0;
  70. }
  71. int init_cache(void) __attribute__((weak, alias("x86_init_cache")));
  72. void flush_cache(unsigned long dummy1, unsigned long dummy2)
  73. {
  74. asm("wbinvd\n");
  75. }
  76. /* Define these functions to allow ehch-hcd to function */
  77. void flush_dcache_range(unsigned long start, unsigned long stop)
  78. {
  79. }
  80. void invalidate_dcache_range(unsigned long start, unsigned long stop)
  81. {
  82. }
  83. void dcache_enable(void)
  84. {
  85. enable_caches();
  86. }
  87. void dcache_disable(void)
  88. {
  89. disable_caches();
  90. }
  91. void icache_enable(void)
  92. {
  93. }
  94. void icache_disable(void)
  95. {
  96. }
  97. int icache_status(void)
  98. {
  99. return 1;
  100. }
  101. const char *cpu_vendor_name(int vendor)
  102. {
  103. const char *name;
  104. name = "<invalid cpu vendor>";
  105. if (vendor < ARRAY_SIZE(x86_vendor_name) &&
  106. x86_vendor_name[vendor])
  107. name = x86_vendor_name[vendor];
  108. return name;
  109. }
  110. char *cpu_get_name(char *name)
  111. {
  112. unsigned int *name_as_ints = (unsigned int *)name;
  113. struct cpuid_result regs;
  114. char *ptr;
  115. int i;
  116. /* This bit adds up to 48 bytes */
  117. for (i = 0; i < 3; i++) {
  118. regs = cpuid(0x80000002 + i);
  119. name_as_ints[i * 4 + 0] = regs.eax;
  120. name_as_ints[i * 4 + 1] = regs.ebx;
  121. name_as_ints[i * 4 + 2] = regs.ecx;
  122. name_as_ints[i * 4 + 3] = regs.edx;
  123. }
  124. name[CPU_MAX_NAME_LEN - 1] = '\0';
  125. /* Skip leading spaces. */
  126. ptr = name;
  127. while (*ptr == ' ')
  128. ptr++;
  129. return ptr;
  130. }
  131. int default_print_cpuinfo(void)
  132. {
  133. printf("CPU: %s, vendor %s, device %xh\n",
  134. cpu_has_64bit() ? "x86_64" : "x86",
  135. cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device);
  136. #ifdef CONFIG_HAVE_ACPI_RESUME
  137. debug("ACPI previous sleep state: %s\n",
  138. acpi_ss_string(gd->arch.prev_sleep_state));
  139. #endif
  140. return 0;
  141. }
  142. void show_boot_progress(int val)
  143. {
  144. outb(val, POST_PORT);
  145. }
  146. #if !defined(CONFIG_SYS_COREBOOT) && !defined(CONFIG_EFI_STUB)
  147. /*
  148. * Implement a weak default function for boards that optionally
  149. * need to clean up the system before jumping to the kernel.
  150. */
  151. __weak void board_final_cleanup(void)
  152. {
  153. }
  154. int last_stage_init(void)
  155. {
  156. struct acpi_fadt __maybe_unused *fadt;
  157. board_final_cleanup();
  158. #ifdef CONFIG_HAVE_ACPI_RESUME
  159. fadt = acpi_find_fadt();
  160. if (fadt && gd->arch.prev_sleep_state == ACPI_S3)
  161. acpi_resume(fadt);
  162. #endif
  163. write_tables();
  164. #ifdef CONFIG_GENERATE_ACPI_TABLE
  165. fadt = acpi_find_fadt();
  166. /* Don't touch ACPI hardware on HW reduced platforms */
  167. if (fadt && !(fadt->flags & ACPI_FADT_HW_REDUCED_ACPI)) {
  168. /*
  169. * Other than waiting for OSPM to request us to switch to ACPI
  170. * mode, do it by ourselves, since SMI will not be triggered.
  171. */
  172. enter_acpi_mode(fadt->pm1a_cnt_blk);
  173. }
  174. #endif
  175. return 0;
  176. }
  177. #endif
  178. static int x86_init_cpus(void)
  179. {
  180. #ifdef CONFIG_SMP
  181. debug("Init additional CPUs\n");
  182. x86_mp_init();
  183. #else
  184. struct udevice *dev;
  185. /*
  186. * This causes the cpu-x86 driver to be probed.
  187. * We don't check return value here as we want to allow boards
  188. * which have not been converted to use cpu uclass driver to boot.
  189. */
  190. uclass_first_device(UCLASS_CPU, &dev);
  191. #endif
  192. return 0;
  193. }
  194. int cpu_init_r(void)
  195. {
  196. struct udevice *dev;
  197. int ret;
  198. if (!ll_boot_init())
  199. return 0;
  200. ret = x86_init_cpus();
  201. if (ret)
  202. return ret;
  203. /*
  204. * Set up the northbridge, PCH and LPC if available. Note that these
  205. * may have had some limited pre-relocation init if they were probed
  206. * before relocation, but this is post relocation.
  207. */
  208. uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
  209. uclass_first_device(UCLASS_PCH, &dev);
  210. uclass_first_device(UCLASS_LPC, &dev);
  211. /* Set up pin control if available */
  212. ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev);
  213. debug("%s, pinctrl=%p, ret=%d\n", __func__, dev, ret);
  214. return 0;
  215. }
  216. #ifndef CONFIG_EFI_STUB
  217. int reserve_arch(void)
  218. {
  219. #ifdef CONFIG_ENABLE_MRC_CACHE
  220. mrccache_reserve();
  221. #endif
  222. #ifdef CONFIG_SEABIOS
  223. high_table_reserve();
  224. #endif
  225. #ifdef CONFIG_HAVE_ACPI_RESUME
  226. acpi_s3_reserve();
  227. #ifdef CONFIG_HAVE_FSP
  228. /*
  229. * Save stack address to CMOS so that at next S3 boot,
  230. * we can use it as the stack address for fsp_contiue()
  231. */
  232. fsp_save_s3_stack();
  233. #endif /* CONFIG_HAVE_FSP */
  234. #endif /* CONFIG_HAVE_ACPI_RESUME */
  235. return 0;
  236. }
  237. #endif