cache.c 1.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Andes Technology Corporation
  4. * Rick Chen, Andes Technology Corporation <rick@andestech.com>
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. void invalidate_icache_all(void)
  9. {
  10. asm volatile ("fence.i" ::: "memory");
  11. }
  12. __weak void flush_dcache_all(void)
  13. {
  14. }
  15. __weak void flush_dcache_range(unsigned long start, unsigned long end)
  16. {
  17. }
  18. void invalidate_icache_range(unsigned long start, unsigned long end)
  19. {
  20. /*
  21. * RISC-V does not have an instruction for invalidating parts of the
  22. * instruction cache. Invalidate all of it instead.
  23. */
  24. invalidate_icache_all();
  25. }
  26. __weak void invalidate_dcache_range(unsigned long start, unsigned long end)
  27. {
  28. }
  29. void cache_flush(void)
  30. {
  31. invalidate_icache_all();
  32. flush_dcache_all();
  33. }
  34. void flush_cache(unsigned long addr, unsigned long size)
  35. {
  36. invalidate_icache_range(addr, addr + size);
  37. flush_dcache_range(addr, addr + size);
  38. }
  39. __weak void icache_enable(void)
  40. {
  41. }
  42. __weak void icache_disable(void)
  43. {
  44. }
  45. __weak int icache_status(void)
  46. {
  47. return 0;
  48. }
  49. __weak void dcache_enable(void)
  50. {
  51. }
  52. __weak void dcache_disable(void)
  53. {
  54. }
  55. __weak int dcache_status(void)
  56. {
  57. return 0;
  58. }