cache.c 2.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Andes Technology Corporation
  4. * Rick Chen, Andes Technology Corporation <rick@andestech.com>
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <dm.h>
  9. #include <dm/uclass-internal.h>
  10. #include <cache.h>
  11. #include <asm/csr.h>
  12. #ifdef CONFIG_RISCV_NDS_CACHE
  13. /* mcctlcommand */
  14. #define CCTL_REG_MCCTLCOMMAND_NUM 0x7cc
  15. /* D-cache operation */
  16. #define CCTL_L1D_WBINVAL_ALL 6
  17. #endif
  18. void flush_dcache_all(void)
  19. {
  20. #ifdef CONFIG_RISCV_NDS_CACHE
  21. csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
  22. #endif
  23. }
  24. void flush_dcache_range(unsigned long start, unsigned long end)
  25. {
  26. flush_dcache_all();
  27. }
  28. void invalidate_dcache_range(unsigned long start, unsigned long end)
  29. {
  30. flush_dcache_all();
  31. }
  32. void icache_enable(void)
  33. {
  34. #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
  35. #ifdef CONFIG_RISCV_NDS_CACHE
  36. asm volatile (
  37. "csrr t1, mcache_ctl\n\t"
  38. "ori t0, t1, 0x1\n\t"
  39. "csrw mcache_ctl, t0\n\t"
  40. );
  41. #endif
  42. #endif
  43. }
  44. void icache_disable(void)
  45. {
  46. #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
  47. #ifdef CONFIG_RISCV_NDS_CACHE
  48. asm volatile (
  49. "fence.i\n\t"
  50. "csrr t1, mcache_ctl\n\t"
  51. "andi t0, t1, ~0x1\n\t"
  52. "csrw mcache_ctl, t0\n\t"
  53. );
  54. #endif
  55. #endif
  56. }
  57. void dcache_enable(void)
  58. {
  59. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  60. #ifdef CONFIG_RISCV_NDS_CACHE
  61. struct udevice *dev = NULL;
  62. asm volatile (
  63. "csrr t1, mcache_ctl\n\t"
  64. "ori t0, t1, 0x2\n\t"
  65. "csrw mcache_ctl, t0\n\t"
  66. );
  67. uclass_find_first_device(UCLASS_CACHE, &dev);
  68. if (dev)
  69. cache_enable(dev);
  70. #endif
  71. #endif
  72. }
  73. void dcache_disable(void)
  74. {
  75. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  76. #ifdef CONFIG_RISCV_NDS_CACHE
  77. struct udevice *dev = NULL;
  78. csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
  79. asm volatile (
  80. "csrr t1, mcache_ctl\n\t"
  81. "andi t0, t1, ~0x2\n\t"
  82. "csrw mcache_ctl, t0\n\t"
  83. );
  84. uclass_find_first_device(UCLASS_CACHE, &dev);
  85. if (dev)
  86. cache_disable(dev);
  87. #endif
  88. #endif
  89. }
  90. int icache_status(void)
  91. {
  92. int ret = 0;
  93. #ifdef CONFIG_RISCV_NDS_CACHE
  94. asm volatile (
  95. "csrr t1, mcache_ctl\n\t"
  96. "andi %0, t1, 0x01\n\t"
  97. : "=r" (ret)
  98. :
  99. : "memory"
  100. );
  101. #endif
  102. return ret;
  103. }
  104. int dcache_status(void)
  105. {
  106. int ret = 0;
  107. #ifdef CONFIG_RISCV_NDS_CACHE
  108. asm volatile (
  109. "csrr t1, mcache_ctl\n\t"
  110. "andi %0, t1, 0x02\n\t"
  111. : "=r" (ret)
  112. :
  113. : "memory"
  114. );
  115. #endif
  116. return ret;
  117. }