spd_sdram.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2006-2007 Freescale Semiconductor, Inc.
  4. *
  5. * (C) Copyright 2006
  6. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  7. *
  8. * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
  9. * (C) Copyright 2003 Motorola Inc.
  10. * Xianghua Xiao (X.Xiao@motorola.com)
  11. */
  12. #ifndef CONFIG_MPC83XX_SDRAM
  13. #include <common.h>
  14. #include <cpu_func.h>
  15. #include <vsprintf.h>
  16. #include <asm/processor.h>
  17. #include <asm/io.h>
  18. #include <i2c.h>
  19. #include <spd.h>
  20. #include <asm/mmu.h>
  21. #include <spd_sdram.h>
  22. DECLARE_GLOBAL_DATA_PTR;
  23. void board_add_ram_info(int use_default)
  24. {
  25. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  26. volatile ddr83xx_t *ddr = &immap->ddr;
  27. char buf[32];
  28. printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK)
  29. >> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1);
  30. #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
  31. if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_16)
  32. puts(", 16-bit");
  33. else if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_32)
  34. puts(", 32-bit");
  35. else
  36. puts(", unknown width");
  37. #else
  38. if (ddr->sdram_cfg & SDRAM_CFG_32_BE)
  39. puts(", 32-bit");
  40. else
  41. puts(", 64-bit");
  42. #endif
  43. if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
  44. puts(", ECC on");
  45. else
  46. puts(", ECC off");
  47. printf(", %s MHz)", strmhz(buf, gd->mem_clk));
  48. #if defined(CONFIG_SYS_LB_SDRAM) && defined(CONFIG_SYS_LBC_SDRAM_SIZE)
  49. puts("\nSDRAM: ");
  50. print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)");
  51. #endif
  52. }
  53. #ifdef CONFIG_SPD_EEPROM
  54. #ifndef CONFIG_SYS_READ_SPD
  55. #define CONFIG_SYS_READ_SPD i2c_read
  56. #endif
  57. #ifndef SPD_EEPROM_OFFSET
  58. #define SPD_EEPROM_OFFSET 0
  59. #endif
  60. #ifndef SPD_EEPROM_ADDR_LEN
  61. #define SPD_EEPROM_ADDR_LEN 1
  62. #endif
  63. /*
  64. * Convert picoseconds into clock cycles (rounding up if needed).
  65. */
  66. int
  67. picos_to_clk(int picos)
  68. {
  69. unsigned int mem_bus_clk;
  70. int clks;
  71. mem_bus_clk = gd->mem_clk >> 1;
  72. clks = picos / (1000000000 / (mem_bus_clk / 1000));
  73. if (picos % (1000000000 / (mem_bus_clk / 1000)) != 0)
  74. clks++;
  75. return clks;
  76. }
  77. unsigned int banksize(unsigned char row_dens)
  78. {
  79. return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
  80. }
  81. int read_spd(uint addr)
  82. {
  83. return ((int) addr);
  84. }
  85. #undef SPD_DEBUG
  86. #ifdef SPD_DEBUG
  87. static void spd_debug(spd_eeprom_t *spd)
  88. {
  89. printf ("\nDIMM type: %-18.18s\n", spd->mpart);
  90. printf ("SPD size: %d\n", spd->info_size);
  91. printf ("EEPROM size: %d\n", 1 << spd->chip_size);
  92. printf ("Memory type: %d\n", spd->mem_type);
  93. printf ("Row addr: %d\n", spd->nrow_addr);
  94. printf ("Column addr: %d\n", spd->ncol_addr);
  95. printf ("# of rows: %d\n", spd->nrows);
  96. printf ("Row density: %d\n", spd->row_dens);
  97. printf ("# of banks: %d\n", spd->nbanks);
  98. printf ("Data width: %d\n",
  99. 256 * spd->dataw_msb + spd->dataw_lsb);
  100. printf ("Chip width: %d\n", spd->primw);
  101. printf ("Refresh rate: %02X\n", spd->refresh);
  102. printf ("CAS latencies: %02X\n", spd->cas_lat);
  103. printf ("Write latencies: %02X\n", spd->write_lat);
  104. printf ("tRP: %d\n", spd->trp);
  105. printf ("tRCD: %d\n", spd->trcd);
  106. printf ("\n");
  107. }
  108. #endif /* SPD_DEBUG */
  109. long int spd_sdram()
  110. {
  111. volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  112. volatile ddr83xx_t *ddr = &immap->ddr;
  113. volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0];
  114. spd_eeprom_t spd;
  115. unsigned int n_ranks;
  116. unsigned int odt_rd_cfg, odt_wr_cfg;
  117. unsigned char twr_clk, twtr_clk;
  118. unsigned int sdram_type;
  119. unsigned int memsize;
  120. unsigned int law_size;
  121. unsigned char caslat, caslat_ctrl;
  122. unsigned int trfc, trfc_clk, trfc_low;
  123. unsigned int trcd_clk, trtp_clk;
  124. unsigned char cke_min_clk;
  125. unsigned char add_lat, wr_lat;
  126. unsigned char wr_data_delay;
  127. unsigned char four_act;
  128. unsigned char cpo;
  129. unsigned char burstlen;
  130. unsigned char odt_cfg, mode_odt_enable;
  131. unsigned int max_bus_clk;
  132. unsigned int max_data_rate, effective_data_rate;
  133. unsigned int ddrc_clk;
  134. unsigned int refresh_clk;
  135. unsigned int sdram_cfg;
  136. unsigned int ddrc_ecc_enable;
  137. unsigned int pvr = get_pvr();
  138. /*
  139. * First disable the memory controller (could be enabled
  140. * by the debugger)
  141. */
  142. clrsetbits_be32(&ddr->sdram_cfg, SDRAM_CFG_MEM_EN, 0);
  143. sync();
  144. isync();
  145. /* Read SPD parameters with I2C */
  146. CONFIG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, SPD_EEPROM_OFFSET,
  147. SPD_EEPROM_ADDR_LEN, (uchar *) &spd, sizeof(spd));
  148. #ifdef SPD_DEBUG
  149. spd_debug(&spd);
  150. #endif
  151. /* Check the memory type */
  152. if (spd.mem_type != SPD_MEMTYPE_DDR && spd.mem_type != SPD_MEMTYPE_DDR2) {
  153. debug("DDR: Module mem type is %02X\n", spd.mem_type);
  154. return 0;
  155. }
  156. /* Check the number of physical bank */
  157. if (spd.mem_type == SPD_MEMTYPE_DDR) {
  158. n_ranks = spd.nrows;
  159. } else {
  160. n_ranks = (spd.nrows & 0x7) + 1;
  161. }
  162. if (n_ranks > 2) {
  163. printf("DDR: The number of physical bank is %02X\n", n_ranks);
  164. return 0;
  165. }
  166. /* Check if the number of row of the module is in the range of DDRC */
  167. if (spd.nrow_addr < 12 || spd.nrow_addr > 15) {
  168. printf("DDR: Row number is out of range of DDRC, row=%02X\n",
  169. spd.nrow_addr);
  170. return 0;
  171. }
  172. /* Check if the number of col of the module is in the range of DDRC */
  173. if (spd.ncol_addr < 8 || spd.ncol_addr > 11) {
  174. printf("DDR: Col number is out of range of DDRC, col=%02X\n",
  175. spd.ncol_addr);
  176. return 0;
  177. }
  178. #ifdef CONFIG_SYS_DDRCDR_VALUE
  179. /*
  180. * Adjust DDR II IO voltage biasing. It just makes it work.
  181. */
  182. if(spd.mem_type == SPD_MEMTYPE_DDR2) {
  183. immap->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
  184. }
  185. udelay(50000);
  186. #endif
  187. /*
  188. * ODT configuration recommendation from DDR Controller Chapter.
  189. */
  190. odt_rd_cfg = 0; /* Never assert ODT */
  191. odt_wr_cfg = 0; /* Never assert ODT */
  192. if (spd.mem_type == SPD_MEMTYPE_DDR2) {
  193. odt_wr_cfg = 1; /* Assert ODT on writes to CSn */
  194. }
  195. /* Setup DDR chip select register */
  196. #ifdef CONFIG_SYS_83XX_DDR_USES_CS0
  197. ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1;
  198. ddr->cs_config[0] = ( 1 << 31
  199. | (odt_rd_cfg << 20)
  200. | (odt_wr_cfg << 16)
  201. | ((spd.nbanks == 8 ? 1 : 0) << 14)
  202. | ((spd.nrow_addr - 12) << 8)
  203. | (spd.ncol_addr - 8) );
  204. debug("\n");
  205. debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds);
  206. debug("cs0_config = 0x%08x\n",ddr->cs_config[0]);
  207. if (n_ranks == 2) {
  208. ddr->csbnds[1].csbnds = ( (banksize(spd.row_dens) >> 8)
  209. | ((banksize(spd.row_dens) >> 23) - 1) );
  210. ddr->cs_config[1] = ( 1<<31
  211. | (odt_rd_cfg << 20)
  212. | (odt_wr_cfg << 16)
  213. | ((spd.nbanks == 8 ? 1 : 0) << 14)
  214. | ((spd.nrow_addr - 12) << 8)
  215. | (spd.ncol_addr - 8) );
  216. debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds);
  217. debug("cs1_config = 0x%08x\n",ddr->cs_config[1]);
  218. }
  219. #else
  220. ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1;
  221. ddr->cs_config[2] = ( 1 << 31
  222. | (odt_rd_cfg << 20)
  223. | (odt_wr_cfg << 16)
  224. | ((spd.nbanks == 8 ? 1 : 0) << 14)
  225. | ((spd.nrow_addr - 12) << 8)
  226. | (spd.ncol_addr - 8) );
  227. debug("\n");
  228. debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds);
  229. debug("cs2_config = 0x%08x\n",ddr->cs_config[2]);
  230. if (n_ranks == 2) {
  231. ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8)
  232. | ((banksize(spd.row_dens) >> 23) - 1) );
  233. ddr->cs_config[3] = ( 1<<31
  234. | (odt_rd_cfg << 20)
  235. | (odt_wr_cfg << 16)
  236. | ((spd.nbanks == 8 ? 1 : 0) << 14)
  237. | ((spd.nrow_addr - 12) << 8)
  238. | (spd.ncol_addr - 8) );
  239. debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds);
  240. debug("cs3_config = 0x%08x\n",ddr->cs_config[3]);
  241. }
  242. #endif
  243. /*
  244. * Figure out memory size in Megabytes.
  245. */
  246. memsize = n_ranks * banksize(spd.row_dens) / 0x100000;
  247. /*
  248. * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23.
  249. */
  250. law_size = 19 + __ilog2(memsize);
  251. /*
  252. * Set up LAWBAR for all of DDR.
  253. */
  254. ecm->bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
  255. ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
  256. debug("DDR:bar=0x%08x\n", ecm->bar);
  257. debug("DDR:ar=0x%08x\n", ecm->ar);
  258. /*
  259. * Find the largest CAS by locating the highest 1 bit
  260. * in the spd.cas_lat field. Translate it to a DDR
  261. * controller field value:
  262. *
  263. * CAS Lat DDR I DDR II Ctrl
  264. * Clocks SPD Bit SPD Bit Value
  265. * ------- ------- ------- -----
  266. * 1.0 0 0001
  267. * 1.5 1 0010
  268. * 2.0 2 2 0011
  269. * 2.5 3 0100
  270. * 3.0 4 3 0101
  271. * 3.5 5 0110
  272. * 4.0 6 4 0111
  273. * 4.5 1000
  274. * 5.0 5 1001
  275. */
  276. caslat = __ilog2(spd.cas_lat);
  277. if ((spd.mem_type == SPD_MEMTYPE_DDR)
  278. && (caslat > 6)) {
  279. printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat);
  280. return 0;
  281. } else if (spd.mem_type == SPD_MEMTYPE_DDR2
  282. && (caslat < 2 || caslat > 5)) {
  283. printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n",
  284. spd.cas_lat);
  285. return 0;
  286. }
  287. debug("DDR: caslat SPD bit is %d\n", caslat);
  288. max_bus_clk = 1000 *10 / (((spd.clk_cycle & 0xF0) >> 4) * 10
  289. + (spd.clk_cycle & 0x0f));
  290. max_data_rate = max_bus_clk * 2;
  291. debug("DDR:Module maximum data rate is: %d MHz\n", max_data_rate);
  292. ddrc_clk = gd->mem_clk / 1000000;
  293. effective_data_rate = 0;
  294. if (max_data_rate >= 460) { /* it is DDR2-800, 667, 533 */
  295. if (spd.cas_lat & 0x08)
  296. caslat = 3;
  297. else
  298. caslat = 4;
  299. if (ddrc_clk <= 460 && ddrc_clk > 350)
  300. effective_data_rate = 400;
  301. else if (ddrc_clk <=350 && ddrc_clk > 280)
  302. effective_data_rate = 333;
  303. else if (ddrc_clk <= 280 && ddrc_clk > 230)
  304. effective_data_rate = 266;
  305. else
  306. effective_data_rate = 200;
  307. } else if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */
  308. if (ddrc_clk <= 460 && ddrc_clk > 350) {
  309. /* DDR controller clk at 350~460 */
  310. effective_data_rate = 400; /* 5ns */
  311. caslat = caslat;
  312. } else if (ddrc_clk <= 350 && ddrc_clk > 280) {
  313. /* DDR controller clk at 280~350 */
  314. effective_data_rate = 333; /* 6ns */
  315. if (spd.clk_cycle2 == 0x60)
  316. caslat = caslat - 1;
  317. else
  318. caslat = caslat;
  319. } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
  320. /* DDR controller clk at 230~280 */
  321. effective_data_rate = 266; /* 7.5ns */
  322. if (spd.clk_cycle3 == 0x75)
  323. caslat = caslat - 2;
  324. else if (spd.clk_cycle2 == 0x75)
  325. caslat = caslat - 1;
  326. else
  327. caslat = caslat;
  328. } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
  329. /* DDR controller clk at 90~230 */
  330. effective_data_rate = 200; /* 10ns */
  331. if (spd.clk_cycle3 == 0xa0)
  332. caslat = caslat - 2;
  333. else if (spd.clk_cycle2 == 0xa0)
  334. caslat = caslat - 1;
  335. else
  336. caslat = caslat;
  337. }
  338. } else if (max_data_rate >= 323) { /* it is DDR 333 */
  339. if (ddrc_clk <= 350 && ddrc_clk > 280) {
  340. /* DDR controller clk at 280~350 */
  341. effective_data_rate = 333; /* 6ns */
  342. caslat = caslat;
  343. } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
  344. /* DDR controller clk at 230~280 */
  345. effective_data_rate = 266; /* 7.5ns */
  346. if (spd.clk_cycle2 == 0x75)
  347. caslat = caslat - 1;
  348. else
  349. caslat = caslat;
  350. } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
  351. /* DDR controller clk at 90~230 */
  352. effective_data_rate = 200; /* 10ns */
  353. if (spd.clk_cycle3 == 0xa0)
  354. caslat = caslat - 2;
  355. else if (spd.clk_cycle2 == 0xa0)
  356. caslat = caslat - 1;
  357. else
  358. caslat = caslat;
  359. }
  360. } else if (max_data_rate >= 256) { /* it is DDR 266 */
  361. if (ddrc_clk <= 350 && ddrc_clk > 280) {
  362. /* DDR controller clk at 280~350 */
  363. printf("DDR: DDR controller freq is more than "
  364. "max data rate of the module\n");
  365. return 0;
  366. } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
  367. /* DDR controller clk at 230~280 */
  368. effective_data_rate = 266; /* 7.5ns */
  369. caslat = caslat;
  370. } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
  371. /* DDR controller clk at 90~230 */
  372. effective_data_rate = 200; /* 10ns */
  373. if (spd.clk_cycle2 == 0xa0)
  374. caslat = caslat - 1;
  375. }
  376. } else if (max_data_rate >= 190) { /* it is DDR 200 */
  377. if (ddrc_clk <= 350 && ddrc_clk > 230) {
  378. /* DDR controller clk at 230~350 */
  379. printf("DDR: DDR controller freq is more than "
  380. "max data rate of the module\n");
  381. return 0;
  382. } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
  383. /* DDR controller clk at 90~230 */
  384. effective_data_rate = 200; /* 10ns */
  385. caslat = caslat;
  386. }
  387. }
  388. debug("DDR:Effective data rate is: %dMHz\n", effective_data_rate);
  389. debug("DDR:The MSB 1 of CAS Latency is: %d\n", caslat);
  390. /*
  391. * Errata DDR6 work around: input enable 2 cycles earlier.
  392. * including MPC834X Rev1.0/1.1 and MPC8360 Rev1.1/1.2.
  393. */
  394. if(PVR_MAJ(pvr) <= 1 && spd.mem_type == SPD_MEMTYPE_DDR){
  395. if (caslat == 2)
  396. ddr->debug_reg = 0x201c0000; /* CL=2 */
  397. else if (caslat == 3)
  398. ddr->debug_reg = 0x202c0000; /* CL=2.5 */
  399. else if (caslat == 4)
  400. ddr->debug_reg = 0x202c0000; /* CL=3.0 */
  401. sync();
  402. debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg);
  403. }
  404. /*
  405. * Convert caslat clocks to DDR controller value.
  406. * Force caslat_ctrl to be DDR Controller field-sized.
  407. */
  408. if (spd.mem_type == SPD_MEMTYPE_DDR) {
  409. caslat_ctrl = (caslat + 1) & 0x07;
  410. } else {
  411. caslat_ctrl = (2 * caslat - 1) & 0x0f;
  412. }
  413. debug("DDR: effective data rate is %d MHz\n", effective_data_rate);
  414. debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n",
  415. caslat, caslat_ctrl);
  416. /*
  417. * Timing Config 0.
  418. * Avoid writing for DDR I.
  419. */
  420. if (spd.mem_type == SPD_MEMTYPE_DDR2) {
  421. unsigned char taxpd_clk = 8; /* By the book. */
  422. unsigned char tmrd_clk = 2; /* By the book. */
  423. unsigned char act_pd_exit = 2; /* Empirical? */
  424. unsigned char pre_pd_exit = 6; /* Empirical? */
  425. ddr->timing_cfg_0 = (0
  426. | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */
  427. | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */
  428. | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */
  429. | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */
  430. );
  431. debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
  432. }
  433. /*
  434. * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD,
  435. * use conservative value.
  436. * For DDR II, they are bytes 36 and 37, in quarter nanos.
  437. */
  438. if (spd.mem_type == SPD_MEMTYPE_DDR) {
  439. twr_clk = 3; /* Clocks */
  440. twtr_clk = 1; /* Clocks */
  441. } else {
  442. twr_clk = picos_to_clk(spd.twr * 250);
  443. twtr_clk = picos_to_clk(spd.twtr * 250);
  444. if (twtr_clk < 2)
  445. twtr_clk = 2;
  446. }
  447. /*
  448. * Calculate Trfc, in picos.
  449. * DDR I: Byte 42 straight up in ns.
  450. * DDR II: Byte 40 and 42 swizzled some, in ns.
  451. */
  452. if (spd.mem_type == SPD_MEMTYPE_DDR) {
  453. trfc = spd.trfc * 1000; /* up to ps */
  454. } else {
  455. unsigned int byte40_table_ps[8] = {
  456. 0,
  457. 250,
  458. 330,
  459. 500,
  460. 660,
  461. 750,
  462. 0,
  463. 0
  464. };
  465. trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000
  466. + byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7];
  467. }
  468. trfc_clk = picos_to_clk(trfc);
  469. /*
  470. * Trcd, Byte 29, from quarter nanos to ps and clocks.
  471. */
  472. trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7;
  473. /*
  474. * Convert trfc_clk to DDR controller fields. DDR I should
  475. * fit in the REFREC field (16-19) of TIMING_CFG_1, but the
  476. * 83xx controller has an extended REFREC field of three bits.
  477. * The controller automatically adds 8 clocks to this value,
  478. * so preadjust it down 8 first before splitting it up.
  479. */
  480. trfc_low = (trfc_clk - 8) & 0xf;
  481. ddr->timing_cfg_1 =
  482. (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) | /* PRETOACT */
  483. ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) | /* ACTTOPRE */
  484. (trcd_clk << 20 ) | /* ACTTORW */
  485. (caslat_ctrl << 16 ) | /* CASLAT */
  486. (trfc_low << 12 ) | /* REFEC */
  487. ((twr_clk & 0x07) << 8) | /* WRRREC */
  488. ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | /* ACTTOACT */
  489. ((twtr_clk & 0x07) << 0) /* WRTORD */
  490. );
  491. /*
  492. * Additive Latency
  493. * For DDR I, 0.
  494. * For DDR II, with ODT enabled, use "a value" less than ACTTORW,
  495. * which comes from Trcd, and also note that:
  496. * add_lat + caslat must be >= 4
  497. */
  498. add_lat = 0;
  499. if (spd.mem_type == SPD_MEMTYPE_DDR2
  500. && (odt_wr_cfg || odt_rd_cfg)
  501. && (caslat < 4)) {
  502. add_lat = 4 - caslat;
  503. if ((add_lat + caslat) < 4) {
  504. add_lat = 0;
  505. }
  506. }
  507. /*
  508. * Write Data Delay
  509. * Historically 0x2 == 4/8 clock delay.
  510. * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266.
  511. */
  512. wr_data_delay = 2;
  513. #ifdef CONFIG_SYS_DDR_WRITE_DATA_DELAY
  514. wr_data_delay = CONFIG_SYS_DDR_WRITE_DATA_DELAY;
  515. #endif
  516. /*
  517. * Write Latency
  518. * Read to Precharge
  519. * Minimum CKE Pulse Width.
  520. * Four Activate Window
  521. */
  522. if (spd.mem_type == SPD_MEMTYPE_DDR) {
  523. /*
  524. * This is a lie. It should really be 1, but if it is
  525. * set to 1, bits overlap into the old controller's
  526. * otherwise unused ACSM field. If we leave it 0, then
  527. * the HW will magically treat it as 1 for DDR 1. Oh Yea.
  528. */
  529. wr_lat = 0;
  530. trtp_clk = 2; /* By the book. */
  531. cke_min_clk = 1; /* By the book. */
  532. four_act = 1; /* By the book. */
  533. } else {
  534. wr_lat = caslat - 1;
  535. /* Convert SPD value from quarter nanos to picos. */
  536. trtp_clk = picos_to_clk(spd.trtp * 250);
  537. if (trtp_clk < 2)
  538. trtp_clk = 2;
  539. trtp_clk += add_lat;
  540. cke_min_clk = 3; /* By the book. */
  541. four_act = picos_to_clk(37500); /* By the book. 1k pages? */
  542. }
  543. /*
  544. * Empirically set ~MCAS-to-preamble override for DDR 2.
  545. * Your mileage will vary.
  546. */
  547. cpo = 0;
  548. if (spd.mem_type == SPD_MEMTYPE_DDR2) {
  549. #ifdef CONFIG_SYS_DDR_CPO
  550. cpo = CONFIG_SYS_DDR_CPO;
  551. #else
  552. if (effective_data_rate == 266) {
  553. cpo = 0x4; /* READ_LAT + 1/2 */
  554. } else if (effective_data_rate == 333) {
  555. cpo = 0x6; /* READ_LAT + 1 */
  556. } else if (effective_data_rate == 400) {
  557. cpo = 0x7; /* READ_LAT + 5/4 */
  558. } else {
  559. /* Automatic calibration */
  560. cpo = 0x1f;
  561. }
  562. #endif
  563. }
  564. ddr->timing_cfg_2 = (0
  565. | ((add_lat & 0x7) << 28) /* ADD_LAT */
  566. | ((cpo & 0x1f) << 23) /* CPO */
  567. | ((wr_lat & 0x7) << 19) /* WR_LAT */
  568. | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */
  569. | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */
  570. | ((cke_min_clk & 0x7) << 6) /* CKE_PLS */
  571. | ((four_act & 0x1f) << 0) /* FOUR_ACT */
  572. );
  573. debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1);
  574. debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
  575. /* Check DIMM data bus width */
  576. if (spd.dataw_lsb < 64) {
  577. if (spd.mem_type == SPD_MEMTYPE_DDR)
  578. burstlen = 0x03; /* 32 bit data bus, burst len is 8 */
  579. else
  580. burstlen = 0x02; /* 32 bit data bus, burst len is 4 */
  581. debug("\n DDR DIMM: data bus width is 32 bit");
  582. } else {
  583. burstlen = 0x02; /* Others act as 64 bit bus, burst len is 4 */
  584. debug("\n DDR DIMM: data bus width is 64 bit");
  585. }
  586. /* Is this an ECC DDR chip? */
  587. if (spd.config == 0x02)
  588. debug(" with ECC\n");
  589. else
  590. debug(" without ECC\n");
  591. /* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus,
  592. Burst type is sequential
  593. */
  594. if (spd.mem_type == SPD_MEMTYPE_DDR) {
  595. switch (caslat) {
  596. case 1:
  597. ddr->sdram_mode = 0x50 | burstlen; /* CL=1.5 */
  598. break;
  599. case 2:
  600. ddr->sdram_mode = 0x20 | burstlen; /* CL=2.0 */
  601. break;
  602. case 3:
  603. ddr->sdram_mode = 0x60 | burstlen; /* CL=2.5 */
  604. break;
  605. case 4:
  606. ddr->sdram_mode = 0x30 | burstlen; /* CL=3.0 */
  607. break;
  608. default:
  609. printf("DDR:only CL 1.5, 2.0, 2.5, 3.0 is supported\n");
  610. return 0;
  611. }
  612. } else {
  613. mode_odt_enable = 0x0; /* Default disabled */
  614. if (odt_wr_cfg || odt_rd_cfg) {
  615. /*
  616. * Bits 6 and 2 in Extended MRS(1)
  617. * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules.
  618. * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module.
  619. */
  620. mode_odt_enable = 0x40; /* 150 Ohm */
  621. }
  622. ddr->sdram_mode =
  623. (0
  624. | (1 << (16 + 10)) /* DQS Differential disable */
  625. #ifdef CONFIG_SYS_DDR_MODE_WEAK
  626. | (1 << (16 + 1)) /* weak driver (~60%) */
  627. #endif
  628. | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */
  629. | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */
  630. | ((twr_clk - 1) << 9) /* Write Recovery Autopre */
  631. | (caslat << 4) /* caslat */
  632. | (burstlen << 0) /* Burst length */
  633. );
  634. }
  635. debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
  636. /*
  637. * Clear EMRS2 and EMRS3.
  638. */
  639. ddr->sdram_mode2 = 0;
  640. debug("DDR: sdram_mode2 = 0x%08x\n", ddr->sdram_mode2);
  641. switch (spd.refresh) {
  642. case 0x00:
  643. case 0x80:
  644. refresh_clk = picos_to_clk(15625000);
  645. break;
  646. case 0x01:
  647. case 0x81:
  648. refresh_clk = picos_to_clk(3900000);
  649. break;
  650. case 0x02:
  651. case 0x82:
  652. refresh_clk = picos_to_clk(7800000);
  653. break;
  654. case 0x03:
  655. case 0x83:
  656. refresh_clk = picos_to_clk(31300000);
  657. break;
  658. case 0x04:
  659. case 0x84:
  660. refresh_clk = picos_to_clk(62500000);
  661. break;
  662. case 0x05:
  663. case 0x85:
  664. refresh_clk = picos_to_clk(125000000);
  665. break;
  666. default:
  667. refresh_clk = 0x512;
  668. break;
  669. }
  670. /*
  671. * Set BSTOPRE to 0x100 for page mode
  672. * If auto-charge is used, set BSTOPRE = 0
  673. */
  674. ddr->sdram_interval = ((refresh_clk & 0x3fff) << 16) | 0x100;
  675. debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);
  676. /*
  677. * SDRAM Cfg 2
  678. */
  679. odt_cfg = 0;
  680. #ifndef CONFIG_NEVER_ASSERT_ODT_TO_CPU
  681. if (odt_rd_cfg | odt_wr_cfg) {
  682. odt_cfg = 0x2; /* ODT to IOs during reads */
  683. }
  684. #endif
  685. if (spd.mem_type == SPD_MEMTYPE_DDR2) {
  686. ddr->sdram_cfg2 = (0
  687. | (0 << 26) /* True DQS */
  688. | (odt_cfg << 21) /* ODT only read */
  689. | (1 << 12) /* 1 refresh at a time */
  690. );
  691. debug("DDR: sdram_cfg2 = 0x%08x\n", ddr->sdram_cfg2);
  692. }
  693. #ifdef CONFIG_SYS_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */
  694. ddr->sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
  695. #endif
  696. debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);
  697. sync();
  698. isync();
  699. udelay(600);
  700. /*
  701. * Figure out the settings for the sdram_cfg register. Build up
  702. * the value in 'sdram_cfg' before writing since the write into
  703. * the register will actually enable the memory controller, and all
  704. * settings must be done before enabling.
  705. *
  706. * sdram_cfg[0] = 1 (ddr sdram logic enable)
  707. * sdram_cfg[1] = 1 (self-refresh-enable)
  708. * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM)
  709. * 010 DDR 1 SDRAM
  710. * 011 DDR 2 SDRAM
  711. * sdram_cfg[12] = 0 (32_BE =0 , 64 bit bus mode)
  712. * sdram_cfg[13] = 0 (8_BE =0, 4-beat bursts)
  713. */
  714. if (spd.mem_type == SPD_MEMTYPE_DDR)
  715. sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR1;
  716. else
  717. sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR2;
  718. sdram_cfg = (0
  719. | SDRAM_CFG_MEM_EN /* DDR enable */
  720. | SDRAM_CFG_SREN /* Self refresh */
  721. | sdram_type /* SDRAM type */
  722. );
  723. /* sdram_cfg[3] = RD_EN - registered DIMM enable */
  724. if (spd.mod_attr & 0x02)
  725. sdram_cfg |= SDRAM_CFG_RD_EN;
  726. /* The DIMM is 32bit width */
  727. if (spd.dataw_lsb < 64) {
  728. if (spd.mem_type == SPD_MEMTYPE_DDR)
  729. sdram_cfg |= SDRAM_CFG_32_BE | SDRAM_CFG_8_BE;
  730. if (spd.mem_type == SPD_MEMTYPE_DDR2)
  731. sdram_cfg |= SDRAM_CFG_32_BE;
  732. }
  733. ddrc_ecc_enable = 0;
  734. #if defined(CONFIG_DDR_ECC)
  735. /* Enable ECC with sdram_cfg[2] */
  736. if (spd.config == 0x02) {
  737. sdram_cfg |= 0x20000000;
  738. ddrc_ecc_enable = 1;
  739. /* disable error detection */
  740. ddr->err_disable = ~ECC_ERROR_ENABLE;
  741. /* set single bit error threshold to maximum value,
  742. * reset counter to zero */
  743. ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) |
  744. (0 << ECC_ERROR_MAN_SBEC_SHIFT);
  745. }
  746. debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
  747. debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
  748. #endif
  749. debug(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF");
  750. #if defined(CONFIG_DDR_2T_TIMING)
  751. /*
  752. * Enable 2T timing by setting sdram_cfg[16].
  753. */
  754. sdram_cfg |= SDRAM_CFG_2T_EN;
  755. #endif
  756. /* Enable controller, and GO! */
  757. ddr->sdram_cfg = sdram_cfg;
  758. sync();
  759. isync();
  760. udelay(500);
  761. debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
  762. return memsize; /*in MBytes*/
  763. }
  764. #endif /* CONFIG_SPD_EEPROM */
  765. #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  766. static inline u32 mftbu(void)
  767. {
  768. u32 rval;
  769. asm volatile("mftbu %0" : "=r" (rval));
  770. return rval;
  771. }
  772. static inline u32 mftb(void)
  773. {
  774. u32 rval;
  775. asm volatile("mftb %0" : "=r" (rval));
  776. return rval;
  777. }
  778. /*
  779. * Use timebase counter, get_timer() is not available
  780. * at this point of initialization yet.
  781. */
  782. static __inline__ unsigned long get_tbms (void)
  783. {
  784. unsigned long tbl;
  785. unsigned long tbu1, tbu2;
  786. unsigned long ms;
  787. unsigned long long tmp;
  788. ulong tbclk = get_tbclk();
  789. /* get the timebase ticks */
  790. do {
  791. tbu1 = mftbu();
  792. tbl = mftb();
  793. tbu2 = mftbu();
  794. } while (tbu1 != tbu2);
  795. /* convert ticks to ms */
  796. tmp = (unsigned long long)(tbu1);
  797. tmp = (tmp << 32);
  798. tmp += (unsigned long long)(tbl);
  799. ms = tmp/(tbclk/1000);
  800. return ms;
  801. }
  802. /*
  803. * Initialize all of memory for ECC, then enable errors.
  804. */
  805. void ddr_enable_ecc(unsigned int dram_size)
  806. {
  807. volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  808. volatile ddr83xx_t *ddr= &immap->ddr;
  809. unsigned long t_start, t_end;
  810. register u64 *p;
  811. register uint size;
  812. unsigned int pattern[2];
  813. icache_enable();
  814. t_start = get_tbms();
  815. pattern[0] = 0xdeadbeef;
  816. pattern[1] = 0xdeadbeef;
  817. #if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
  818. dma_meminit(pattern[0], dram_size);
  819. #else
  820. debug("ddr init: CPU FP write method\n");
  821. size = dram_size;
  822. for (p = 0; p < (u64*)(size); p++) {
  823. ppcDWstore((u32*)p, pattern);
  824. }
  825. sync();
  826. #endif
  827. t_end = get_tbms();
  828. icache_disable();
  829. debug("\nREADY!!\n");
  830. debug("ddr init duration: %ld ms\n", t_end - t_start);
  831. /* Clear All ECC Errors */
  832. if ((ddr->err_detect & ECC_ERROR_DETECT_MME) == ECC_ERROR_DETECT_MME)
  833. ddr->err_detect |= ECC_ERROR_DETECT_MME;
  834. if ((ddr->err_detect & ECC_ERROR_DETECT_MBE) == ECC_ERROR_DETECT_MBE)
  835. ddr->err_detect |= ECC_ERROR_DETECT_MBE;
  836. if ((ddr->err_detect & ECC_ERROR_DETECT_SBE) == ECC_ERROR_DETECT_SBE)
  837. ddr->err_detect |= ECC_ERROR_DETECT_SBE;
  838. if ((ddr->err_detect & ECC_ERROR_DETECT_MSE) == ECC_ERROR_DETECT_MSE)
  839. ddr->err_detect |= ECC_ERROR_DETECT_MSE;
  840. /* Disable ECC-Interrupts */
  841. ddr->err_int_en &= ECC_ERR_INT_DISABLE;
  842. /* Enable errors for ECC */
  843. ddr->err_disable &= ECC_ERROR_ENABLE;
  844. sync();
  845. isync();
  846. }
  847. #endif /* CONFIG_DDR_ECC */
  848. #endif /* !CONFIG_MPC83XX_SDRAM */