cache.c 4.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Andes Technology Corporation
  4. * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
  5. * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
  6. */
  7. #include <common.h>
  8. #include <cpu_func.h>
  9. #if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
  10. static inline unsigned long CACHE_SET(unsigned char cache)
  11. {
  12. if (cache == ICACHE)
  13. return 64 << ((GET_ICM_CFG() & ICM_CFG_MSK_ISET) \
  14. >> ICM_CFG_OFF_ISET);
  15. else
  16. return 64 << ((GET_DCM_CFG() & DCM_CFG_MSK_DSET) \
  17. >> DCM_CFG_OFF_DSET);
  18. }
  19. static inline unsigned long CACHE_WAY(unsigned char cache)
  20. {
  21. if (cache == ICACHE)
  22. return 1 + ((GET_ICM_CFG() & ICM_CFG_MSK_IWAY) \
  23. >> ICM_CFG_OFF_IWAY);
  24. else
  25. return 1 + ((GET_DCM_CFG() & DCM_CFG_MSK_DWAY) \
  26. >> DCM_CFG_OFF_DWAY);
  27. }
  28. static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
  29. {
  30. if (cache == ICACHE)
  31. return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
  32. >> ICM_CFG_OFF_ISZ) - 1);
  33. else
  34. return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
  35. >> DCM_CFG_OFF_DSZ) - 1);
  36. }
  37. #endif
  38. #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
  39. void invalidate_icache_all(void)
  40. {
  41. unsigned long end, line_size;
  42. line_size = CACHE_LINE_SIZE(ICACHE);
  43. end = line_size * CACHE_WAY(ICACHE) * CACHE_SET(ICACHE);
  44. do {
  45. end -= line_size;
  46. __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end));
  47. end -= line_size;
  48. __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end));
  49. end -= line_size;
  50. __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end));
  51. end -= line_size;
  52. __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end));
  53. } while (end > 0);
  54. }
  55. void invalidate_icache_range(unsigned long start, unsigned long end)
  56. {
  57. unsigned long line_size;
  58. line_size = CACHE_LINE_SIZE(ICACHE);
  59. while (end > start) {
  60. asm volatile (
  61. "\n\tcctl %0, L1I_VA_INVAL"
  62. :
  63. : "r"(start)
  64. );
  65. start += line_size;
  66. }
  67. }
  68. void icache_enable(void)
  69. {
  70. asm volatile (
  71. "mfsr $p0, $mr8\n\t"
  72. "ori $p0, $p0, 0x01\n\t"
  73. "mtsr $p0, $mr8\n\t"
  74. "isb\n\t"
  75. );
  76. }
  77. void icache_disable(void)
  78. {
  79. asm volatile (
  80. "mfsr $p0, $mr8\n\t"
  81. "li $p1, ~0x01\n\t"
  82. "and $p0, $p0, $p1\n\t"
  83. "mtsr $p0, $mr8\n\t"
  84. "isb\n\t"
  85. );
  86. }
  87. int icache_status(void)
  88. {
  89. int ret;
  90. asm volatile (
  91. "mfsr $p0, $mr8\n\t"
  92. "andi %0, $p0, 0x01\n\t"
  93. : "=r" (ret)
  94. :
  95. : "memory"
  96. );
  97. return ret;
  98. }
  99. #else
  100. void invalidate_icache_all(void)
  101. {
  102. }
  103. void invalidate_icache_range(unsigned long start, unsigned long end)
  104. {
  105. }
  106. void icache_enable(void)
  107. {
  108. }
  109. void icache_disable(void)
  110. {
  111. }
  112. int icache_status(void)
  113. {
  114. return 0;
  115. }
  116. #endif
  117. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  118. void dcache_wbinval_all(void)
  119. {
  120. unsigned long end, line_size;
  121. line_size = CACHE_LINE_SIZE(DCACHE);
  122. end = line_size * CACHE_WAY(DCACHE) * CACHE_SET(DCACHE);
  123. do {
  124. end -= line_size;
  125. __asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end));
  126. __asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end));
  127. end -= line_size;
  128. __asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end));
  129. __asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end));
  130. end -= line_size;
  131. __asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end));
  132. __asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end));
  133. end -= line_size;
  134. __asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end));
  135. __asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end));
  136. } while (end > 0);
  137. }
  138. void flush_dcache_range(unsigned long start, unsigned long end)
  139. {
  140. unsigned long line_size;
  141. line_size = CACHE_LINE_SIZE(DCACHE);
  142. while (end > start) {
  143. asm volatile (
  144. "\n\tcctl %0, L1D_VA_WB"
  145. "\n\tcctl %0, L1D_VA_INVAL" : : "r" (start)
  146. );
  147. start += line_size;
  148. }
  149. }
  150. void invalidate_dcache_range(unsigned long start, unsigned long end)
  151. {
  152. unsigned long line_size;
  153. line_size = CACHE_LINE_SIZE(DCACHE);
  154. while (end > start) {
  155. asm volatile (
  156. "\n\tcctl %0, L1D_VA_INVAL" : : "r"(start)
  157. );
  158. start += line_size;
  159. }
  160. }
  161. void dcache_enable(void)
  162. {
  163. asm volatile (
  164. "mfsr $p0, $mr8\n\t"
  165. "ori $p0, $p0, 0x02\n\t"
  166. "mtsr $p0, $mr8\n\t"
  167. "isb\n\t"
  168. );
  169. }
  170. void dcache_disable(void)
  171. {
  172. asm volatile (
  173. "mfsr $p0, $mr8\n\t"
  174. "li $p1, ~0x02\n\t"
  175. "and $p0, $p0, $p1\n\t"
  176. "mtsr $p0, $mr8\n\t"
  177. "isb\n\t"
  178. );
  179. }
  180. int dcache_status(void)
  181. {
  182. int ret;
  183. asm volatile (
  184. "mfsr $p0, $mr8\n\t"
  185. "andi %0, $p0, 0x02\n\t"
  186. : "=r" (ret)
  187. :
  188. : "memory"
  189. );
  190. return ret;
  191. }
  192. #else
  193. void dcache_wbinval_all(void)
  194. {
  195. }
  196. void flush_dcache_range(unsigned long start, unsigned long end)
  197. {
  198. }
  199. void invalidate_dcache_range(unsigned long start, unsigned long end)
  200. {
  201. }
  202. void dcache_enable(void)
  203. {
  204. }
  205. void dcache_disable(void)
  206. {
  207. }
  208. int dcache_status(void)
  209. {
  210. return 0;
  211. }
  212. #endif
  213. void flush_dcache_all(void)
  214. {
  215. dcache_wbinval_all();
  216. }
  217. void cache_flush(void)
  218. {
  219. flush_dcache_all();
  220. invalidate_icache_all();
  221. }
  222. void flush_cache(unsigned long addr, unsigned long size)
  223. {
  224. flush_dcache_range(addr, addr + size);
  225. invalidate_icache_range(addr, addr + size);
  226. }