cpu_init.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. *
  4. * (C) Copyright 2000-2003
  5. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  6. *
  7. * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc.
  8. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  9. */
  10. #include <common.h>
  11. #include <cpu_func.h>
  12. #include <watchdog.h>
  13. #include <asm/immap.h>
  14. #include <asm/processor.h>
  15. #include <asm/rtc.h>
  16. #include <asm/io.h>
  17. #include <linux/compiler.h>
  18. #if defined(CONFIG_CMD_NET)
  19. #include <config.h>
  20. #include <net.h>
  21. #include <asm/fec.h>
  22. #endif
  23. void init_fbcs(void)
  24. {
  25. fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS;
  26. #if !defined(CONFIG_SERIAL_BOOT)
  27. #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
  28. out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
  29. out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
  30. out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
  31. #endif
  32. #endif
  33. #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
  34. /* Latch chipselect */
  35. out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
  36. out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
  37. out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
  38. #endif
  39. #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
  40. out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
  41. out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
  42. out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
  43. #endif
  44. #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
  45. out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
  46. out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
  47. out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
  48. #endif
  49. #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
  50. out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
  51. out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
  52. out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
  53. #endif
  54. #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
  55. out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
  56. out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
  57. out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
  58. #endif
  59. }
  60. #ifdef CONFIG_CF_DSPI
  61. void cfspi_port_conf(void)
  62. {
  63. gpio_t *gpio = (gpio_t *)MMAP_GPIO;
  64. #ifdef CONFIG_MCF5445x
  65. out_8(&gpio->par_dspi,
  66. GPIO_PAR_DSPI_SIN_SIN |
  67. GPIO_PAR_DSPI_SOUT_SOUT |
  68. GPIO_PAR_DSPI_SCK_SCK);
  69. #endif
  70. #ifdef CONFIG_MCF5441x
  71. pm_t *pm = (pm_t *)MMAP_PM;
  72. out_8(&gpio->par_dspi0,
  73. GPIO_PAR_DSPI0_SIN_DSPI0SIN | GPIO_PAR_DSPI0_SOUT_DSPI0SOUT |
  74. GPIO_PAR_DSPI0_SCK_DSPI0SCK);
  75. out_8(&gpio->srcr_dspiow, 3);
  76. /* DSPI0 */
  77. out_8(&pm->pmcr0, 23);
  78. #endif
  79. }
  80. #endif
  81. /*
  82. * Breath some life into the CPU...
  83. *
  84. * Set up the memory map,
  85. * initialize a bunch of registers,
  86. * initialize the UPM's
  87. */
  88. void cpu_init_f(void)
  89. {
  90. gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  91. #ifdef CONFIG_MCF5441x
  92. scm_t *scm = (scm_t *) MMAP_SCM;
  93. pm_t *pm = (pm_t *) MMAP_PM;
  94. /* Disable Switch */
  95. *(unsigned long *)(MMAP_L2_SW0 + 0x00000024) = 0;
  96. /* Disable core watchdog */
  97. out_be16(&scm->cwcr, 0);
  98. out_8(&gpio->par_fbctl,
  99. GPIO_PAR_FBCTL_ALE_FB_ALE | GPIO_PAR_FBCTL_OE_FB_OE |
  100. GPIO_PAR_FBCTL_FBCLK | GPIO_PAR_FBCTL_RW |
  101. GPIO_PAR_FBCTL_TA_TA);
  102. out_8(&gpio->par_be,
  103. GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
  104. GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
  105. /* eDMA */
  106. out_8(&pm->pmcr0, 17);
  107. /* INTR0 - INTR2 */
  108. out_8(&pm->pmcr0, 18);
  109. out_8(&pm->pmcr0, 19);
  110. out_8(&pm->pmcr0, 20);
  111. /* I2C */
  112. out_8(&pm->pmcr0, 22);
  113. out_8(&pm->pmcr1, 4);
  114. out_8(&pm->pmcr1, 7);
  115. /* DTMR0 - DTMR3*/
  116. out_8(&pm->pmcr0, 28);
  117. out_8(&pm->pmcr0, 29);
  118. out_8(&pm->pmcr0, 30);
  119. out_8(&pm->pmcr0, 31);
  120. /* PIT0 - PIT3 */
  121. out_8(&pm->pmcr0, 32);
  122. out_8(&pm->pmcr0, 33);
  123. out_8(&pm->pmcr0, 34);
  124. out_8(&pm->pmcr0, 35);
  125. /* Edge Port */
  126. out_8(&pm->pmcr0, 36);
  127. out_8(&pm->pmcr0, 37);
  128. /* USB OTG */
  129. out_8(&pm->pmcr0, 44);
  130. /* USB Host */
  131. out_8(&pm->pmcr0, 45);
  132. /* ESDHC */
  133. out_8(&pm->pmcr0, 51);
  134. /* ENET0 - ENET1 */
  135. out_8(&pm->pmcr0, 53);
  136. out_8(&pm->pmcr0, 54);
  137. /* NAND */
  138. out_8(&pm->pmcr0, 63);
  139. #ifdef CONFIG_SYS_I2C_0
  140. out_8(&gpio->par_cani2c, 0xF0);
  141. /* I2C0 pull up */
  142. out_be16(&gpio->pcr_b, 0x003C);
  143. /* I2C0 max speed */
  144. out_8(&gpio->srcr_cani2c, 0x03);
  145. #endif
  146. #ifdef CONFIG_SYS_I2C_2
  147. /* I2C2 */
  148. out_8(&gpio->par_ssi0h, 0xA0);
  149. /* I2C2, UART7 */
  150. out_8(&gpio->par_ssi0h, 0xA8);
  151. /* UART7 */
  152. out_8(&gpio->par_ssi0l, 0x2);
  153. /* UART8, UART9 */
  154. out_8(&gpio->par_cani2c, 0xAA);
  155. /* UART4, UART0 */
  156. out_8(&gpio->par_uart0, 0xAF);
  157. /* UART5, UART1 */
  158. out_8(&gpio->par_uart1, 0xAF);
  159. /* UART6, UART2 */
  160. out_8(&gpio->par_uart2, 0xAF);
  161. /* I2C2 pull up */
  162. out_be16(&gpio->pcr_h, 0xF000);
  163. #endif
  164. #ifdef CONFIG_SYS_I2C_5
  165. /* I2C5 */
  166. out_8(&gpio->par_uart1, 0x0A);
  167. /* I2C5 pull up */
  168. out_be16(&gpio->pcr_e, 0x0003);
  169. out_be16(&gpio->pcr_f, 0xC000);
  170. #endif
  171. /* Lowest slew rate for UART0,1,2 */
  172. out_8(&gpio->srcr_uart, 0x00);
  173. #ifdef CONFIG_FSL_ESDHC_IMX
  174. /* eSDHC pin as faster speed */
  175. out_8(&gpio->srcr_sdhc, 0x03);
  176. /* All esdhc pins as SD */
  177. out_8(&gpio->par_sdhch, 0xff);
  178. out_8(&gpio->par_sdhcl, 0xff);
  179. #endif
  180. #endif /* CONFIG_MCF5441x */
  181. #ifdef CONFIG_MCF5445x
  182. scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
  183. out_be32(&scm1->mpr, 0x77777777);
  184. out_be32(&scm1->pacra, 0);
  185. out_be32(&scm1->pacrb, 0);
  186. out_be32(&scm1->pacrc, 0);
  187. out_be32(&scm1->pacrd, 0);
  188. out_be32(&scm1->pacre, 0);
  189. out_be32(&scm1->pacrf, 0);
  190. out_be32(&scm1->pacrg, 0);
  191. /* FlexBus */
  192. out_8(&gpio->par_be,
  193. GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
  194. GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
  195. out_8(&gpio->par_fbctl,
  196. GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA |
  197. GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS);
  198. #ifdef CONFIG_CF_SPI
  199. cfspi_port_conf();
  200. #endif
  201. #ifdef CONFIG_SYS_FSL_I2C
  202. out_be16(&gpio->par_feci2c,
  203. GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
  204. #endif
  205. #endif /* CONFIG_MCF5445x */
  206. /* FlexBus Chipselect */
  207. init_fbcs();
  208. #ifdef CONFIG_SYS_CS0_BASE
  209. /*
  210. * now the flash base address is no longer at 0 (Newer ColdFire family
  211. * boot at address 0 instead of 0xFFnn_nnnn). The vector table must
  212. * also move to the new location.
  213. */
  214. if (CONFIG_SYS_CS0_BASE != 0)
  215. setvbr(CONFIG_SYS_CS0_BASE);
  216. #endif
  217. icache_enable();
  218. }
  219. /*
  220. * initialize higher level parts of CPU like timers
  221. */
  222. int cpu_init_r(void)
  223. {
  224. #ifdef CONFIG_MCFRTC
  225. rtc_t *rtc = (rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
  226. rtcex_t *rtcex = (rtcex_t *)&rtc->extended;
  227. out_be32(&rtcex->gocu, (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xffff);
  228. out_be32(&rtcex->gocl, CONFIG_SYS_RTC_OSCILLATOR & 0xffff);
  229. #endif
  230. return (0);
  231. }
  232. void uart_port_conf(int port)
  233. {
  234. gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  235. #ifdef CONFIG_MCF5441x
  236. pm_t *pm = (pm_t *) MMAP_PM;
  237. #endif
  238. /* Setup Ports: */
  239. switch (port) {
  240. #ifdef CONFIG_MCF5441x
  241. case 0:
  242. /* UART0 */
  243. out_8(&pm->pmcr0, 24);
  244. clrbits_8(&gpio->par_uart0,
  245. ~(GPIO_PAR_UART0_U0RXD_MASK | GPIO_PAR_UART0_U0TXD_MASK));
  246. setbits_8(&gpio->par_uart0,
  247. GPIO_PAR_UART0_U0RXD_U0RXD | GPIO_PAR_UART0_U0TXD_U0TXD);
  248. break;
  249. case 1:
  250. /* UART1 */
  251. out_8(&pm->pmcr0, 25);
  252. clrbits_8(&gpio->par_uart1,
  253. ~(GPIO_PAR_UART1_U1RXD_MASK | GPIO_PAR_UART1_U1TXD_MASK));
  254. setbits_8(&gpio->par_uart1,
  255. GPIO_PAR_UART1_U1RXD_U1RXD | GPIO_PAR_UART1_U1TXD_U1TXD);
  256. break;
  257. case 2:
  258. /* UART2 */
  259. out_8(&pm->pmcr0, 26);
  260. clrbits_8(&gpio->par_uart2,
  261. ~(GPIO_PAR_UART2_U2RXD_MASK | GPIO_PAR_UART2_U2TXD_MASK));
  262. setbits_8(&gpio->par_uart2,
  263. GPIO_PAR_UART2_U2RXD_U2RXD | GPIO_PAR_UART2_U2TXD_U2TXD);
  264. break;
  265. case 3:
  266. /* UART3 */
  267. out_8(&pm->pmcr0, 27);
  268. clrbits_8(&gpio->par_dspi0,
  269. ~(GPIO_PAR_DSPI0_SIN_MASK | GPIO_PAR_DSPI0_SOUT_MASK));
  270. setbits_8(&gpio->par_dspi0,
  271. GPIO_PAR_DSPI0_SIN_U3RXD | GPIO_PAR_DSPI0_SOUT_U3TXD);
  272. break;
  273. case 4:
  274. /* UART4 */
  275. out_8(&pm->pmcr1, 24);
  276. clrbits_8(&gpio->par_uart0,
  277. ~(GPIO_PAR_UART0_U0CTS_MASK | GPIO_PAR_UART0_U0RTS_MASK));
  278. setbits_8(&gpio->par_uart0,
  279. GPIO_PAR_UART0_U0CTS_U4TXD | GPIO_PAR_UART0_U0RTS_U4RXD);
  280. break;
  281. case 5:
  282. /* UART5 */
  283. out_8(&pm->pmcr1, 25);
  284. clrbits_8(&gpio->par_uart1,
  285. ~(GPIO_PAR_UART1_U1CTS_MASK | GPIO_PAR_UART1_U1RTS_MASK));
  286. setbits_8(&gpio->par_uart1,
  287. GPIO_PAR_UART1_U1CTS_U5TXD | GPIO_PAR_UART1_U1RTS_U5RXD);
  288. break;
  289. case 6:
  290. /* UART6 */
  291. out_8(&pm->pmcr1, 26);
  292. clrbits_8(&gpio->par_uart2,
  293. ~(GPIO_PAR_UART2_U2CTS_MASK | GPIO_PAR_UART2_U2RTS_MASK));
  294. setbits_8(&gpio->par_uart2,
  295. GPIO_PAR_UART2_U2CTS_U6TXD | GPIO_PAR_UART2_U2RTS_U6RXD);
  296. break;
  297. case 7:
  298. /* UART7 */
  299. out_8(&pm->pmcr1, 27);
  300. clrbits_8(&gpio->par_ssi0h, ~GPIO_PAR_SSI0H_RXD_MASK);
  301. clrbits_8(&gpio->par_ssi0l, ~GPIO_PAR_SSI0L_BCLK_MASK);
  302. setbits_8(&gpio->par_ssi0h, GPIO_PAR_SSI0H_FS_U7TXD);
  303. setbits_8(&gpio->par_ssi0l, GPIO_PAR_SSI0L_BCLK_U7RXD);
  304. break;
  305. case 8:
  306. /* UART8 */
  307. out_8(&pm->pmcr0, 28);
  308. clrbits_8(&gpio->par_cani2c,
  309. ~(GPIO_PAR_CANI2C_I2C0SCL_MASK | GPIO_PAR_CANI2C_I2C0SDA_MASK));
  310. setbits_8(&gpio->par_cani2c,
  311. GPIO_PAR_CANI2C_I2C0SCL_U8TXD | GPIO_PAR_CANI2C_I2C0SDA_U8RXD);
  312. break;
  313. case 9:
  314. /* UART9 */
  315. out_8(&pm->pmcr1, 29);
  316. clrbits_8(&gpio->par_cani2c,
  317. ~(GPIO_PAR_CANI2C_CAN1TX_MASK | GPIO_PAR_CANI2C_CAN1RX_MASK));
  318. setbits_8(&gpio->par_cani2c,
  319. GPIO_PAR_CANI2C_CAN1TX_U9TXD | GPIO_PAR_CANI2C_CAN1RX_U9RXD);
  320. break;
  321. #endif
  322. #ifdef CONFIG_MCF5445x
  323. case 0:
  324. clrbits_8(&gpio->par_uart,
  325. GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
  326. setbits_8(&gpio->par_uart,
  327. GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
  328. break;
  329. case 1:
  330. #ifdef CONFIG_SYS_UART1_PRI_GPIO
  331. clrbits_8(&gpio->par_uart,
  332. GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
  333. setbits_8(&gpio->par_uart,
  334. GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
  335. #elif defined(CONFIG_SYS_UART1_ALT1_GPIO)
  336. clrbits_be16(&gpio->par_ssi,
  337. ~(GPIO_PAR_SSI_SRXD_UNMASK | GPIO_PAR_SSI_STXD_UNMASK));
  338. setbits_be16(&gpio->par_ssi,
  339. GPIO_PAR_SSI_SRXD_U1RXD | GPIO_PAR_SSI_STXD_U1TXD);
  340. #endif
  341. break;
  342. case 2:
  343. #if defined(CONFIG_SYS_UART2_ALT1_GPIO)
  344. clrbits_8(&gpio->par_timer,
  345. ~(GPIO_PAR_TIMER_T3IN_UNMASK | GPIO_PAR_TIMER_T2IN_UNMASK));
  346. setbits_8(&gpio->par_timer,
  347. GPIO_PAR_TIMER_T3IN_U2RXD | GPIO_PAR_TIMER_T2IN_U2TXD);
  348. #elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
  349. clrbits_8(&gpio->par_timer,
  350. ~(GPIO_PAR_FECI2C_SCL_UNMASK | GPIO_PAR_FECI2C_SDA_UNMASK));
  351. setbits_8(&gpio->par_timer,
  352. GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD);
  353. #endif
  354. break;
  355. #endif /* CONFIG_MCF5445x */
  356. }
  357. }
  358. #if defined(CONFIG_CMD_NET)
  359. int fecpin_setclear(struct eth_device *dev, int setclear)
  360. {
  361. gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  362. #ifdef CONFIG_MCF5445x
  363. struct fec_info_s *info = (struct fec_info_s *)dev->priv;
  364. if (setclear) {
  365. #ifdef CONFIG_SYS_FEC_NO_SHARED_PHY
  366. if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
  367. setbits_be16(&gpio->par_feci2c,
  368. GPIO_PAR_FECI2C_MDC0_MDC0 |
  369. GPIO_PAR_FECI2C_MDIO0_MDIO0);
  370. else
  371. setbits_be16(&gpio->par_feci2c,
  372. GPIO_PAR_FECI2C_MDC1_MDC1 |
  373. GPIO_PAR_FECI2C_MDIO1_MDIO1);
  374. #else
  375. setbits_be16(&gpio->par_feci2c,
  376. GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
  377. #endif
  378. if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
  379. setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_RMII_GPIO);
  380. else
  381. setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_RMII_ATA);
  382. } else {
  383. clrbits_be16(&gpio->par_feci2c,
  384. GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
  385. if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
  386. #ifdef CONFIG_SYS_FEC_FULL_MII
  387. setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_MII);
  388. #else
  389. clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC0_UNMASK);
  390. #endif
  391. } else {
  392. #ifdef CONFIG_SYS_FEC_FULL_MII
  393. setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_MII);
  394. #else
  395. clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC1_UNMASK);
  396. #endif
  397. }
  398. }
  399. #endif /* CONFIG_MCF5445x */
  400. #ifdef CONFIG_MCF5441x
  401. if (setclear) {
  402. out_8(&gpio->par_fec, 0x03);
  403. out_8(&gpio->srcr_fec, 0x0F);
  404. clrsetbits_8(&gpio->par_simp0h, ~GPIO_PAR_SIMP0H_DAT_MASK,
  405. GPIO_PAR_SIMP0H_DAT_GPIO);
  406. clrsetbits_8(&gpio->pddr_g, ~GPIO_PDDR_G4_MASK,
  407. GPIO_PDDR_G4_OUTPUT);
  408. clrbits_8(&gpio->podr_g, ~GPIO_PODR_G4_MASK);
  409. } else
  410. clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC_MASK);
  411. #endif
  412. return 0;
  413. }
  414. #endif